2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/ctype.h>
24 #include <linux/sched.h>
25 #include <linux/sysfs.h>
26 #include <linux/types.h>
27 #include <linux/init.h>
28 #include <linux/kmod.h>
29 #include <linux/poll.h>
30 #include <linux/cpu.h>
31 #include <linux/smp.h>
34 #include <asm/processor.h>
41 /* Handle unconfigured int18 (should never happen) */
42 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
44 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
48 /* Call the installed machine check handler for this CPU setup. */
49 void (*machine_check_vector)(struct pt_regs *, long error_code) =
50 unexpected_machine_check;
54 #ifdef CONFIG_X86_NEW_MCE
56 #define MISC_MCELOG_MINOR 227
60 DEFINE_PER_CPU(unsigned, mce_exception_count);
64 * 0: always panic on uncorrected errors, log corrected errors
65 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
66 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
67 * 3: never panic or SIGBUS, log all errors (for testing only)
69 static int tolerant = 1;
72 static unsigned long notify_user;
74 static int mce_bootlog = -1;
76 static char trigger[128];
77 static char *trigger_argv[2] = { trigger, NULL };
79 static unsigned long dont_init_banks;
81 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
83 /* MCA banks polled by the period polling timer for corrected events */
84 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
85 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
88 static inline int skip_bank_init(int i)
90 return i < BITS_PER_LONG && test_bit(i, &dont_init_banks);
93 /* Do initial initialization of a struct mce */
94 void mce_setup(struct mce *m)
96 memset(m, 0, sizeof(struct mce));
97 m->cpu = smp_processor_id();
101 DEFINE_PER_CPU(struct mce, injectm);
102 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
105 * Lockless MCE logging infrastructure.
106 * This avoids deadlocks on printk locks without having to break locks. Also
107 * separate MCEs from kernel messages to avoid bogus bug reports.
110 static struct mce_log mcelog = {
115 void mce_log(struct mce *mce)
117 unsigned next, entry;
122 entry = rcu_dereference(mcelog.next);
125 * When the buffer fills up discard new entries.
126 * Assume that the earlier errors are the more
129 if (entry >= MCE_LOG_LEN) {
130 set_bit(MCE_OVERFLOW,
131 (unsigned long *)&mcelog.flags);
134 /* Old left over entry. Skip: */
135 if (mcelog.entry[entry].finished) {
143 if (cmpxchg(&mcelog.next, entry, next) == entry)
146 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
148 mcelog.entry[entry].finished = 1;
151 set_bit(0, ¬ify_user);
154 static void print_mce(struct mce *m)
156 printk(KERN_EMERG "\n"
157 KERN_EMERG "HARDWARE ERROR\n"
159 "CPU %d: Machine Check Exception: %16Lx Bank %d: %016Lx\n",
160 m->cpu, m->mcgstatus, m->bank, m->status);
162 printk(KERN_EMERG "RIP%s %02x:<%016Lx> ",
163 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
165 if (m->cs == __KERNEL_CS)
166 print_symbol("{%s}", m->ip);
169 printk(KERN_EMERG "TSC %llx ", m->tsc);
171 printk("ADDR %llx ", m->addr);
173 printk("MISC %llx ", m->misc);
175 printk(KERN_EMERG "This is not a software problem!\n");
176 printk(KERN_EMERG "Run through mcelog --ascii to decode "
177 "and contact your hardware vendor\n");
180 static void mce_panic(char *msg, struct mce *backup, u64 start)
186 for (i = 0; i < MCE_LOG_LEN; i++) {
187 u64 tsc = mcelog.entry[i].tsc;
189 if ((s64)(tsc - start) < 0)
191 print_mce(&mcelog.entry[i]);
192 if (backup && mcelog.entry[i].tsc == backup->tsc)
200 /* Support code for software error injection */
202 static int msr_to_offset(u32 msr)
204 unsigned bank = __get_cpu_var(injectm.bank);
206 return offsetof(struct mce, ip);
207 if (msr == MSR_IA32_MC0_STATUS + bank*4)
208 return offsetof(struct mce, status);
209 if (msr == MSR_IA32_MC0_ADDR + bank*4)
210 return offsetof(struct mce, addr);
211 if (msr == MSR_IA32_MC0_MISC + bank*4)
212 return offsetof(struct mce, misc);
213 if (msr == MSR_IA32_MCG_STATUS)
214 return offsetof(struct mce, mcgstatus);
218 /* MSR access wrappers used for error injection */
219 static u64 mce_rdmsrl(u32 msr)
222 if (__get_cpu_var(injectm).finished) {
223 int offset = msr_to_offset(msr);
226 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
232 static void mce_wrmsrl(u32 msr, u64 v)
234 if (__get_cpu_var(injectm).finished) {
235 int offset = msr_to_offset(msr);
237 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
243 int mce_available(struct cpuinfo_x86 *c)
247 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
250 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
252 if (regs && (m->mcgstatus & MCG_STATUS_RIPV)) {
260 /* Assume the RIP in the MSR is exact. Is this true? */
261 m->mcgstatus |= MCG_STATUS_EIPV;
262 m->ip = mce_rdmsrl(rip_msr);
268 * Poll for corrected events or events that happened before reset.
269 * Those are just logged through /dev/mcelog.
271 * This is executed in standard interrupt context.
273 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
280 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
281 for (i = 0; i < banks; i++) {
282 if (!bank[i] || !test_bit(i, *b))
291 m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
292 if (!(m.status & MCI_STATUS_VAL))
296 * Uncorrected events are handled by the exception handler
297 * when it is enabled. But when the exception is disabled log
300 * TBD do the same check for MCI_STATUS_EN here?
302 if ((m.status & MCI_STATUS_UC) && !(flags & MCP_UC))
305 if (m.status & MCI_STATUS_MISCV)
306 m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4);
307 if (m.status & MCI_STATUS_ADDRV)
308 m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4);
310 if (!(flags & MCP_TIMESTAMP))
313 * Don't get the IP here because it's unlikely to
314 * have anything to do with the actual error location.
316 if (!(flags & MCP_DONTLOG)) {
318 add_taint(TAINT_MACHINE_CHECK);
322 * Clear state for this bank.
324 mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
328 * Don't clear MCG_STATUS here because it's only defined for
334 EXPORT_SYMBOL_GPL(machine_check_poll);
337 * The actual machine check handler. This only handles real
338 * exceptions when something got corrupted coming in through int 18.
340 * This is executed in NMI context not subject to normal locking rules. This
341 * implies that most kernel services cannot be safely used. Don't even
342 * think about putting a printk in there!
344 void do_machine_check(struct pt_regs *regs, long error_code)
346 struct mce m, panicm;
347 int panicm_found = 0;
351 * If no_way_out gets set, there is no safe way to recover from this
352 * MCE. If tolerant is cranked up, we'll try anyway.
356 * If kill_it gets set, there might be a way to recover from this
360 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
362 atomic_inc(&mce_entry);
364 __get_cpu_var(mce_exception_count)++;
366 if (notify_die(DIE_NMI, "machine check", regs, error_code,
367 18, SIGKILL) == NOTIFY_STOP)
374 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
376 /* if the restart IP is not valid, we're done for */
377 if (!(m.mcgstatus & MCG_STATUS_RIPV))
383 for (i = 0; i < banks; i++) {
384 __clear_bit(i, toclear);
392 m.status = mce_rdmsrl(MSR_IA32_MC0_STATUS + i*4);
393 if ((m.status & MCI_STATUS_VAL) == 0)
397 * Non uncorrected errors are handled by machine_check_poll
400 if ((m.status & MCI_STATUS_UC) == 0)
404 * Set taint even when machine check was not enabled.
406 add_taint(TAINT_MACHINE_CHECK);
408 __set_bit(i, toclear);
410 if (m.status & MCI_STATUS_EN) {
411 /* if PCC was set, there's no way out */
412 no_way_out |= !!(m.status & MCI_STATUS_PCC);
414 * If this error was uncorrectable and there was
415 * an overflow, we're in trouble. If no overflow,
416 * we might get away with just killing a task.
418 if (m.status & MCI_STATUS_UC) {
419 if (tolerant < 1 || m.status & MCI_STATUS_OVER)
425 * Machine check event was not enabled. Clear, but
431 if (m.status & MCI_STATUS_MISCV)
432 m.misc = mce_rdmsrl(MSR_IA32_MC0_MISC + i*4);
433 if (m.status & MCI_STATUS_ADDRV)
434 m.addr = mce_rdmsrl(MSR_IA32_MC0_ADDR + i*4);
436 mce_get_rip(&m, regs);
440 * Did this bank cause the exception?
442 * Assume that the bank with uncorrectable errors did it,
443 * and that there is only a single one:
445 if ((m.status & MCI_STATUS_UC) &&
446 (m.status & MCI_STATUS_EN)) {
453 * If we didn't find an uncorrectable error, pick
454 * the last one (shouldn't happen, just being safe).
460 * If we have decided that we just CAN'T continue, and the user
461 * has not set tolerant to an insane level, give up and die.
463 if (no_way_out && tolerant < 3)
464 mce_panic("Machine check", &panicm, mcestart);
467 * If the error seems to be unrecoverable, something should be
468 * done. Try to kill as little as possible. If we can kill just
469 * one task, do that. If the user has set the tolerance very
470 * high, don't try to do anything at all.
472 if (kill_it && tolerant < 3) {
476 * If the EIPV bit is set, it means the saved IP is the
477 * instruction which caused the MCE.
479 if (m.mcgstatus & MCG_STATUS_EIPV)
480 user_space = panicm.ip && (panicm.cs & 3);
483 * If we know that the error was in user space, send a
484 * SIGBUS. Otherwise, panic if tolerance is low.
486 * force_sig() takes an awful lot of locks and has a slight
487 * risk of deadlocking.
490 force_sig(SIGBUS, current);
491 } else if (panic_on_oops || tolerant < 2) {
492 mce_panic("Uncorrected machine check",
497 /* notify userspace ASAP */
498 set_thread_flag(TIF_MCE_NOTIFY);
500 /* the last thing we do is clear state */
501 for (i = 0; i < banks; i++) {
502 if (test_bit(i, toclear))
503 mce_wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
505 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
507 atomic_dec(&mce_entry);
510 EXPORT_SYMBOL_GPL(do_machine_check);
512 #ifdef CONFIG_X86_MCE_INTEL
514 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
515 * @cpu: The CPU on which the event occurred.
516 * @status: Event status information
518 * This function should be called by the thermal interrupt after the
519 * event has been processed and the decision was made to log the event
522 * The status parameter will be saved to the 'status' field of 'struct mce'
523 * and historically has been the register value of the
524 * MSR_IA32_THERMAL_STATUS (Intel) msr.
526 void mce_log_therm_throt_event(__u64 status)
531 m.bank = MCE_THERMAL_BANK;
535 #endif /* CONFIG_X86_MCE_INTEL */
538 * Periodic polling timer for "silent" machine check errors. If the
539 * poller finds an MCE, poll 2x faster. When the poller finds no more
540 * errors, poll 2x slower (up to check_interval seconds).
542 static int check_interval = 5 * 60; /* 5 minutes */
544 static DEFINE_PER_CPU(int, next_interval); /* in jiffies */
545 static DEFINE_PER_CPU(struct timer_list, mce_timer);
547 static void mcheck_timer(unsigned long data)
549 struct timer_list *t = &per_cpu(mce_timer, data);
552 WARN_ON(smp_processor_id() != data);
554 if (mce_available(¤t_cpu_data)) {
555 machine_check_poll(MCP_TIMESTAMP,
556 &__get_cpu_var(mce_poll_banks));
560 * Alert userspace if needed. If we logged an MCE, reduce the
561 * polling interval, otherwise increase the polling interval.
563 n = &__get_cpu_var(next_interval);
564 if (mce_notify_user())
565 *n = max(*n/2, HZ/100);
567 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
569 t->expires = jiffies + *n;
573 static void mce_do_trigger(struct work_struct *work)
575 call_usermodehelper(trigger, trigger_argv, NULL, UMH_NO_WAIT);
578 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
581 * Notify the user(s) about new machine check events.
582 * Can be called from interrupt context, but not from machine check/NMI
585 int mce_notify_user(void)
587 /* Not more than two messages every minute */
588 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
590 clear_thread_flag(TIF_MCE_NOTIFY);
592 if (test_and_clear_bit(0, ¬ify_user)) {
593 wake_up_interruptible(&mce_wait);
596 * There is no risk of missing notifications because
597 * work_pending is always cleared before the function is
600 if (trigger[0] && !work_pending(&mce_trigger_work))
601 schedule_work(&mce_trigger_work);
603 if (__ratelimit(&ratelimit))
604 printk(KERN_INFO "Machine check events logged\n");
610 EXPORT_SYMBOL_GPL(mce_notify_user);
613 * Initialize Machine Checks for a CPU.
615 static int mce_cap_init(void)
620 rdmsrl(MSR_IA32_MCG_CAP, cap);
622 b = cap & MCG_BANKCNT_MASK;
623 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
625 if (b > MAX_NR_BANKS) {
627 "MCE: Using only %u machine check banks out of %u\n",
632 /* Don't support asymmetric configurations today */
633 WARN_ON(banks != 0 && b != banks);
636 bank = kmalloc(banks * sizeof(u64), GFP_KERNEL);
639 memset(bank, 0xff, banks * sizeof(u64));
642 /* Use accurate RIP reporting if available. */
643 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
644 rip_msr = MSR_IA32_MCG_EIP;
649 static void mce_init(void)
651 mce_banks_t all_banks;
656 * Log the machine checks left over from the previous reset.
658 bitmap_fill(all_banks, MAX_NR_BANKS);
659 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
661 set_in_cr4(X86_CR4_MCE);
663 rdmsrl(MSR_IA32_MCG_CAP, cap);
665 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
667 for (i = 0; i < banks; i++) {
668 if (skip_bank_init(i))
670 wrmsrl(MSR_IA32_MC0_CTL+4*i, bank[i]);
671 wrmsrl(MSR_IA32_MC0_STATUS+4*i, 0);
675 /* Add per CPU specific workarounds here */
676 static void mce_cpu_quirks(struct cpuinfo_x86 *c)
678 /* This should be disabled by the BIOS, but isn't always */
679 if (c->x86_vendor == X86_VENDOR_AMD) {
680 if (c->x86 == 15 && banks > 4) {
682 * disable GART TBL walk error reporting, which
683 * trips off incorrectly with the IOMMU & 3ware
686 clear_bit(10, (unsigned long *)&bank[4]);
688 if (c->x86 <= 17 && mce_bootlog < 0) {
690 * Lots of broken BIOS around that don't clear them
691 * by default and leave crap in there. Don't log:
696 * Various K7s with broken bank 0 around. Always disable
703 if (c->x86_vendor == X86_VENDOR_INTEL) {
705 * SDM documents that on family 6 bank 0 should not be written
706 * because it aliases to another special BIOS controlled
708 * But it's not aliased anymore on model 0x1a+
709 * Don't ignore bank 0 completely because there could be a
710 * valid event later, merely don't write CTL0.
713 if (c->x86 == 6 && c->x86_model < 0x1A)
714 __set_bit(0, &dont_init_banks);
718 static void __cpuinit mce_ancient_init(struct cpuinfo_x86 *c)
722 switch (c->x86_vendor) {
723 case X86_VENDOR_INTEL:
724 if (mce_p5_enabled())
725 intel_p5_mcheck_init(c);
727 case X86_VENDOR_CENTAUR:
728 winchip_mcheck_init(c);
733 static void mce_cpu_features(struct cpuinfo_x86 *c)
735 switch (c->x86_vendor) {
736 case X86_VENDOR_INTEL:
737 mce_intel_feature_init(c);
740 mce_amd_feature_init(c);
747 static void mce_init_timer(void)
749 struct timer_list *t = &__get_cpu_var(mce_timer);
750 int *n = &__get_cpu_var(next_interval);
752 *n = check_interval * HZ;
755 setup_timer(t, mcheck_timer, smp_processor_id());
756 t->expires = round_jiffies(jiffies + *n);
761 * Called for each booted CPU to set up machine checks.
762 * Must be called with preempt off:
764 void __cpuinit mcheck_init(struct cpuinfo_x86 *c)
771 if (!mce_available(c))
774 if (mce_cap_init() < 0) {
780 machine_check_vector = do_machine_check;
788 * Character device to read and clear the MCE log.
791 static DEFINE_SPINLOCK(mce_state_lock);
792 static int open_count; /* #times opened */
793 static int open_exclu; /* already open exclusive? */
795 static int mce_open(struct inode *inode, struct file *file)
797 spin_lock(&mce_state_lock);
799 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
800 spin_unlock(&mce_state_lock);
805 if (file->f_flags & O_EXCL)
809 spin_unlock(&mce_state_lock);
811 return nonseekable_open(inode, file);
814 static int mce_release(struct inode *inode, struct file *file)
816 spin_lock(&mce_state_lock);
821 spin_unlock(&mce_state_lock);
826 static void collect_tscs(void *data)
828 unsigned long *cpu_tsc = (unsigned long *)data;
830 rdtscll(cpu_tsc[smp_processor_id()]);
833 static DEFINE_MUTEX(mce_read_mutex);
835 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
838 char __user *buf = ubuf;
839 unsigned long *cpu_tsc;
843 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
847 mutex_lock(&mce_read_mutex);
848 next = rcu_dereference(mcelog.next);
850 /* Only supports full reads right now */
851 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce)) {
852 mutex_unlock(&mce_read_mutex);
861 for (i = prev; i < next; i++) {
862 unsigned long start = jiffies;
864 while (!mcelog.entry[i].finished) {
865 if (time_after_eq(jiffies, start + 2)) {
866 memset(mcelog.entry + i, 0,
873 err |= copy_to_user(buf, mcelog.entry + i,
875 buf += sizeof(struct mce);
880 memset(mcelog.entry + prev, 0,
881 (next - prev) * sizeof(struct mce));
883 next = cmpxchg(&mcelog.next, prev, 0);
884 } while (next != prev);
889 * Collect entries that were still getting written before the
892 on_each_cpu(collect_tscs, cpu_tsc, 1);
894 for (i = next; i < MCE_LOG_LEN; i++) {
895 if (mcelog.entry[i].finished &&
896 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
897 err |= copy_to_user(buf, mcelog.entry+i,
900 buf += sizeof(struct mce);
901 memset(&mcelog.entry[i], 0, sizeof(struct mce));
904 mutex_unlock(&mce_read_mutex);
907 return err ? -EFAULT : buf - ubuf;
910 static unsigned int mce_poll(struct file *file, poll_table *wait)
912 poll_wait(file, &mce_wait, wait);
913 if (rcu_dereference(mcelog.next))
914 return POLLIN | POLLRDNORM;
918 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
920 int __user *p = (int __user *)arg;
922 if (!capable(CAP_SYS_ADMIN))
926 case MCE_GET_RECORD_LEN:
927 return put_user(sizeof(struct mce), p);
928 case MCE_GET_LOG_LEN:
929 return put_user(MCE_LOG_LEN, p);
930 case MCE_GETCLEAR_FLAGS: {
934 flags = mcelog.flags;
935 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
937 return put_user(flags, p);
944 /* Modified in mce-inject.c, so not static or const */
945 struct file_operations mce_chrdev_ops = {
947 .release = mce_release,
950 .unlocked_ioctl = mce_ioctl,
952 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
954 static struct miscdevice mce_log_device = {
961 * mce=off disables machine check
962 * mce=TOLERANCELEVEL (number, see above)
963 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
964 * mce=nobootlog Don't log MCEs from before booting.
966 static int __init mcheck_enable(char *str)
972 if (!strcmp(str, "off"))
974 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
975 mce_bootlog = (str[0] == 'b');
976 else if (isdigit(str[0]))
977 get_option(&str, &tolerant);
979 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
985 __setup("mce", mcheck_enable);
992 * Disable machine checks on suspend and shutdown. We can't really handle
995 static int mce_disable(void)
999 for (i = 0; i < banks; i++) {
1000 if (!skip_bank_init(i))
1001 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
1006 static int mce_suspend(struct sys_device *dev, pm_message_t state)
1008 return mce_disable();
1011 static int mce_shutdown(struct sys_device *dev)
1013 return mce_disable();
1017 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1018 * Only one CPU is active at this time, the others get re-added later using
1021 static int mce_resume(struct sys_device *dev)
1024 mce_cpu_features(¤t_cpu_data);
1029 static void mce_cpu_restart(void *data)
1031 del_timer_sync(&__get_cpu_var(mce_timer));
1032 if (mce_available(¤t_cpu_data))
1037 /* Reinit MCEs after user configuration changes */
1038 static void mce_restart(void)
1040 on_each_cpu(mce_cpu_restart, NULL, 1);
1043 static struct sysdev_class mce_sysclass = {
1044 .suspend = mce_suspend,
1045 .shutdown = mce_shutdown,
1046 .resume = mce_resume,
1047 .name = "machinecheck",
1050 DEFINE_PER_CPU(struct sys_device, mce_dev);
1053 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1055 static struct sysdev_attribute *bank_attrs;
1057 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1060 u64 b = bank[attr - bank_attrs];
1062 return sprintf(buf, "%llx\n", b);
1065 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1066 const char *buf, size_t size)
1070 if (strict_strtoull(buf, 0, &new) < 0)
1073 bank[attr - bank_attrs] = new;
1080 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1082 strcpy(buf, trigger);
1084 return strlen(trigger) + 1;
1087 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1088 const char *buf, size_t siz)
1093 strncpy(trigger, buf, sizeof(trigger));
1094 trigger[sizeof(trigger)-1] = 0;
1095 len = strlen(trigger);
1096 p = strchr(trigger, '\n');
1104 static ssize_t store_int_with_restart(struct sys_device *s,
1105 struct sysdev_attribute *attr,
1106 const char *buf, size_t size)
1108 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1113 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1114 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1116 static struct sysdev_ext_attribute attr_check_interval = {
1117 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1118 store_int_with_restart),
1122 static struct sysdev_attribute *mce_attrs[] = {
1123 &attr_tolerant.attr, &attr_check_interval.attr, &attr_trigger,
1127 static cpumask_var_t mce_dev_initialized;
1129 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1130 static __cpuinit int mce_create_device(unsigned int cpu)
1135 if (!mce_available(&boot_cpu_data))
1138 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1139 per_cpu(mce_dev, cpu).id = cpu;
1140 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1142 err = sysdev_register(&per_cpu(mce_dev, cpu));
1146 for (i = 0; mce_attrs[i]; i++) {
1147 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1151 for (i = 0; i < banks; i++) {
1152 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1157 cpumask_set_cpu(cpu, mce_dev_initialized);
1162 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
1165 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1167 sysdev_unregister(&per_cpu(mce_dev, cpu));
1172 static __cpuinit void mce_remove_device(unsigned int cpu)
1176 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
1179 for (i = 0; mce_attrs[i]; i++)
1180 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1182 for (i = 0; i < banks; i++)
1183 sysdev_remove_file(&per_cpu(mce_dev, cpu), &bank_attrs[i]);
1185 sysdev_unregister(&per_cpu(mce_dev, cpu));
1186 cpumask_clear_cpu(cpu, mce_dev_initialized);
1189 /* Make sure there are no machine checks on offlined CPUs. */
1190 static void mce_disable_cpu(void *h)
1192 unsigned long action = *(unsigned long *)h;
1195 if (!mce_available(¤t_cpu_data))
1197 if (!(action & CPU_TASKS_FROZEN))
1199 for (i = 0; i < banks; i++) {
1200 if (!skip_bank_init(i))
1201 wrmsrl(MSR_IA32_MC0_CTL + i*4, 0);
1205 static void mce_reenable_cpu(void *h)
1207 unsigned long action = *(unsigned long *)h;
1210 if (!mce_available(¤t_cpu_data))
1213 if (!(action & CPU_TASKS_FROZEN))
1215 for (i = 0; i < banks; i++) {
1216 if (!skip_bank_init(i))
1217 wrmsrl(MSR_IA32_MC0_CTL + i*4, bank[i]);
1221 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
1222 static int __cpuinit
1223 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
1225 unsigned int cpu = (unsigned long)hcpu;
1226 struct timer_list *t = &per_cpu(mce_timer, cpu);
1230 case CPU_ONLINE_FROZEN:
1231 mce_create_device(cpu);
1232 if (threshold_cpu_callback)
1233 threshold_cpu_callback(action, cpu);
1236 case CPU_DEAD_FROZEN:
1237 if (threshold_cpu_callback)
1238 threshold_cpu_callback(action, cpu);
1239 mce_remove_device(cpu);
1241 case CPU_DOWN_PREPARE:
1242 case CPU_DOWN_PREPARE_FROZEN:
1244 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
1246 case CPU_DOWN_FAILED:
1247 case CPU_DOWN_FAILED_FROZEN:
1248 t->expires = round_jiffies(jiffies +
1249 __get_cpu_var(next_interval));
1250 add_timer_on(t, cpu);
1251 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
1254 /* intentionally ignoring frozen here */
1255 cmci_rediscover(cpu);
1261 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
1262 .notifier_call = mce_cpu_callback,
1265 static __init int mce_init_banks(void)
1269 bank_attrs = kzalloc(sizeof(struct sysdev_attribute) * banks,
1274 for (i = 0; i < banks; i++) {
1275 struct sysdev_attribute *a = &bank_attrs[i];
1277 a->attr.name = kasprintf(GFP_KERNEL, "bank%d", i);
1281 a->attr.mode = 0644;
1282 a->show = show_bank;
1283 a->store = set_bank;
1289 kfree(bank_attrs[i].attr.name);
1296 static __init int mce_init_device(void)
1301 if (!mce_available(&boot_cpu_data))
1304 alloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
1306 err = mce_init_banks();
1310 err = sysdev_class_register(&mce_sysclass);
1314 for_each_online_cpu(i) {
1315 err = mce_create_device(i);
1320 register_hotcpu_notifier(&mce_cpu_notifier);
1321 misc_register(&mce_log_device);
1326 device_initcall(mce_init_device);
1328 #else /* CONFIG_X86_OLD_MCE: */
1331 EXPORT_SYMBOL_GPL(nr_mce_banks); /* non-fatal.o */
1333 /* This has to be run for each processor */
1334 void mcheck_init(struct cpuinfo_x86 *c)
1336 if (mce_disabled == 1)
1339 switch (c->x86_vendor) {
1340 case X86_VENDOR_AMD:
1344 case X86_VENDOR_INTEL:
1346 intel_p5_mcheck_init(c);
1348 intel_p6_mcheck_init(c);
1350 intel_p4_mcheck_init(c);
1353 case X86_VENDOR_CENTAUR:
1355 winchip_mcheck_init(c);
1361 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", nr_mce_banks);
1364 static int __init mcheck_enable(char *str)
1370 __setup("mce", mcheck_enable);
1372 #endif /* CONFIG_X86_OLD_MCE */
1375 * Old style boot options parsing. Only for compatibility.
1377 static int __init mcheck_disable(char *str)
1382 __setup("nomce", mcheck_disable);