2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/interrupt.h>
14 #include <linux/ratelimit.h>
15 #include <linux/kallsyms.h>
16 #include <linux/rcupdate.h>
17 #include <linux/kobject.h>
18 #include <linux/uaccess.h>
19 #include <linux/kdebug.h>
20 #include <linux/kernel.h>
21 #include <linux/percpu.h>
22 #include <linux/string.h>
23 #include <linux/sysdev.h>
24 #include <linux/syscore_ops.h>
25 #include <linux/delay.h>
26 #include <linux/ctype.h>
27 #include <linux/sched.h>
28 #include <linux/sysfs.h>
29 #include <linux/types.h>
30 #include <linux/slab.h>
31 #include <linux/init.h>
32 #include <linux/kmod.h>
33 #include <linux/poll.h>
34 #include <linux/nmi.h>
35 #include <linux/cpu.h>
36 #include <linux/smp.h>
39 #include <linux/debugfs.h>
40 #include <linux/edac_mce.h>
42 #include <asm/processor.h>
43 #include <asm/hw_irq.h>
50 #include "mce-internal.h"
52 static DEFINE_MUTEX(mce_read_mutex);
54 #define rcu_dereference_check_mce(p) \
55 rcu_dereference_index_check((p), \
56 rcu_read_lock_sched_held() || \
57 lockdep_is_held(&mce_read_mutex))
59 #define CREATE_TRACE_POINTS
60 #include <trace/events/mce.h>
62 int mce_disabled __read_mostly;
64 #define MISC_MCELOG_MINOR 227
66 #define SPINUNIT 100 /* 100ns */
70 DEFINE_PER_CPU(unsigned, mce_exception_count);
74 * 0: always panic on uncorrected errors, log corrected errors
75 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
76 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
77 * 3: never panic or SIGBUS, log all errors (for testing only)
79 static int tolerant __read_mostly = 1;
80 static int banks __read_mostly;
81 static int rip_msr __read_mostly;
82 static int mce_bootlog __read_mostly = -1;
83 static int monarch_timeout __read_mostly = -1;
84 static int mce_panic_timeout __read_mostly;
85 static int mce_dont_log_ce __read_mostly;
86 int mce_cmci_disabled __read_mostly;
87 int mce_ignore_ce __read_mostly;
88 int mce_ser __read_mostly;
90 struct mce_bank *mce_banks __read_mostly;
92 /* User mode helper program triggered by machine check event */
93 static unsigned long mce_need_notify;
94 static char mce_helper[128];
95 static char *mce_helper_argv[2] = { mce_helper, NULL };
97 static DECLARE_WAIT_QUEUE_HEAD(mce_wait);
98 static DEFINE_PER_CPU(struct mce, mces_seen);
99 static int cpu_missing;
102 * CPU/chipset specific EDAC code can register a notifier call here to print
103 * MCE errors in a human-readable form.
105 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
106 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
108 /* MCA banks polled by the period polling timer for corrected events */
109 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
110 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
113 static DEFINE_PER_CPU(struct work_struct, mce_work);
115 /* Do initial initialization of a struct mce */
116 void mce_setup(struct mce *m)
118 memset(m, 0, sizeof(struct mce));
119 m->cpu = m->extcpu = smp_processor_id();
121 /* We hope get_seconds stays lockless */
122 m->time = get_seconds();
123 m->cpuvendor = boot_cpu_data.x86_vendor;
124 m->cpuid = cpuid_eax(1);
126 m->socketid = cpu_data(m->extcpu).phys_proc_id;
128 m->apicid = cpu_data(m->extcpu).initial_apicid;
129 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
132 DEFINE_PER_CPU(struct mce, injectm);
133 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
136 * Lockless MCE logging infrastructure.
137 * This avoids deadlocks on printk locks without having to break locks. Also
138 * separate MCEs from kernel messages to avoid bogus bug reports.
141 static struct mce_log mcelog = {
142 .signature = MCE_LOG_SIGNATURE,
144 .recordlen = sizeof(struct mce),
147 void mce_log(struct mce *mce)
149 unsigned next, entry;
151 /* Emit the trace record: */
152 trace_mce_record(mce);
157 entry = rcu_dereference_check_mce(mcelog.next);
160 * If edac_mce is enabled, it will check the error type
161 * and will process it, if it is a known error.
162 * Otherwise, the error will be sent through mcelog
165 if (edac_mce_parse(mce))
169 * When the buffer fills up discard new entries.
170 * Assume that the earlier errors are the more
173 if (entry >= MCE_LOG_LEN) {
174 set_bit(MCE_OVERFLOW,
175 (unsigned long *)&mcelog.flags);
178 /* Old left over entry. Skip: */
179 if (mcelog.entry[entry].finished) {
187 if (cmpxchg(&mcelog.next, entry, next) == entry)
190 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
192 mcelog.entry[entry].finished = 1;
196 set_bit(0, &mce_need_notify);
199 static void print_mce(struct mce *m)
203 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
204 m->extcpu, m->mcgstatus, m->bank, m->status);
207 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
208 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
211 if (m->cs == __KERNEL_CS)
212 print_symbol("{%s}", m->ip);
216 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
218 pr_cont("ADDR %llx ", m->addr);
220 pr_cont("MISC %llx ", m->misc);
223 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
224 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid);
227 * Print out human-readable details about the MCE error,
228 * (if the CPU has an implementation for that)
230 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
231 if (ret == NOTIFY_STOP)
234 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
237 #define PANIC_TIMEOUT 5 /* 5 seconds */
239 static atomic_t mce_paniced;
241 static int fake_panic;
242 static atomic_t mce_fake_paniced;
244 /* Panic in progress. Enable interrupts and wait for final IPI */
245 static void wait_for_panic(void)
247 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
251 while (timeout-- > 0)
253 if (panic_timeout == 0)
254 panic_timeout = mce_panic_timeout;
255 panic("Panicing machine check CPU died");
258 static void mce_panic(char *msg, struct mce *final, char *exp)
264 * Make sure only one CPU runs in machine check panic
266 if (atomic_inc_return(&mce_paniced) > 1)
273 /* Don't log too much for fake panic */
274 if (atomic_inc_return(&mce_fake_paniced) > 1)
277 /* First print corrected ones that are still unlogged */
278 for (i = 0; i < MCE_LOG_LEN; i++) {
279 struct mce *m = &mcelog.entry[i];
280 if (!(m->status & MCI_STATUS_VAL))
282 if (!(m->status & MCI_STATUS_UC)) {
285 apei_err = apei_write_mce(m);
288 /* Now print uncorrected but with the final one last */
289 for (i = 0; i < MCE_LOG_LEN; i++) {
290 struct mce *m = &mcelog.entry[i];
291 if (!(m->status & MCI_STATUS_VAL))
293 if (!(m->status & MCI_STATUS_UC))
295 if (!final || memcmp(m, final, sizeof(struct mce))) {
298 apei_err = apei_write_mce(m);
304 apei_err = apei_write_mce(final);
307 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
309 pr_emerg(HW_ERR "Machine check: %s\n", exp);
311 if (panic_timeout == 0)
312 panic_timeout = mce_panic_timeout;
315 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
318 /* Support code for software error injection */
320 static int msr_to_offset(u32 msr)
322 unsigned bank = __this_cpu_read(injectm.bank);
325 return offsetof(struct mce, ip);
326 if (msr == MSR_IA32_MCx_STATUS(bank))
327 return offsetof(struct mce, status);
328 if (msr == MSR_IA32_MCx_ADDR(bank))
329 return offsetof(struct mce, addr);
330 if (msr == MSR_IA32_MCx_MISC(bank))
331 return offsetof(struct mce, misc);
332 if (msr == MSR_IA32_MCG_STATUS)
333 return offsetof(struct mce, mcgstatus);
337 /* MSR access wrappers used for error injection */
338 static u64 mce_rdmsrl(u32 msr)
342 if (__this_cpu_read(injectm.finished)) {
343 int offset = msr_to_offset(msr);
347 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
350 if (rdmsrl_safe(msr, &v)) {
351 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
353 * Return zero in case the access faulted. This should
354 * not happen normally but can happen if the CPU does
355 * something weird, or if the code is buggy.
363 static void mce_wrmsrl(u32 msr, u64 v)
365 if (__this_cpu_read(injectm.finished)) {
366 int offset = msr_to_offset(msr);
369 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
376 * Simple lockless ring to communicate PFNs from the exception handler with the
377 * process context work function. This is vastly simplified because there's
378 * only a single reader and a single writer.
380 #define MCE_RING_SIZE 16 /* we use one entry less */
383 unsigned short start;
385 unsigned long ring[MCE_RING_SIZE];
387 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
389 /* Runs with CPU affinity in workqueue */
390 static int mce_ring_empty(void)
392 struct mce_ring *r = &__get_cpu_var(mce_ring);
394 return r->start == r->end;
397 static int mce_ring_get(unsigned long *pfn)
404 r = &__get_cpu_var(mce_ring);
405 if (r->start == r->end)
407 *pfn = r->ring[r->start];
408 r->start = (r->start + 1) % MCE_RING_SIZE;
415 /* Always runs in MCE context with preempt off */
416 static int mce_ring_add(unsigned long pfn)
418 struct mce_ring *r = &__get_cpu_var(mce_ring);
421 next = (r->end + 1) % MCE_RING_SIZE;
422 if (next == r->start)
424 r->ring[r->end] = pfn;
430 int mce_available(struct cpuinfo_x86 *c)
434 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
437 static void mce_schedule_work(void)
439 if (!mce_ring_empty()) {
440 struct work_struct *work = &__get_cpu_var(mce_work);
441 if (!work_pending(work))
447 * Get the address of the instruction at the time of the machine check
450 static inline void mce_get_rip(struct mce *m, struct pt_regs *regs)
453 if (regs && (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV))) {
461 m->ip = mce_rdmsrl(rip_msr);
464 #ifdef CONFIG_X86_LOCAL_APIC
466 * Called after interrupts have been reenabled again
467 * when a MCE happened during an interrupts off region
470 asmlinkage void smp_mce_self_interrupt(struct pt_regs *regs)
481 static void mce_report_event(struct pt_regs *regs)
483 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
486 * Triggering the work queue here is just an insurance
487 * policy in case the syscall exit notify handler
488 * doesn't run soon enough or ends up running on the
489 * wrong CPU (can happen when audit sleeps)
495 #ifdef CONFIG_X86_LOCAL_APIC
497 * Without APIC do not notify. The event will be picked
504 * When interrupts are disabled we cannot use
505 * kernel services safely. Trigger an self interrupt
506 * through the APIC to instead do the notification
507 * after interrupts are reenabled again.
509 apic->send_IPI_self(MCE_SELF_VECTOR);
512 * Wait for idle afterwards again so that we don't leave the
513 * APIC in a non idle state because the normal APIC writes
516 apic_wait_icr_idle();
520 DEFINE_PER_CPU(unsigned, mce_poll_count);
523 * Poll for corrected events or events that happened before reset.
524 * Those are just logged through /dev/mcelog.
526 * This is executed in standard interrupt context.
528 * Note: spec recommends to panic for fatal unsignalled
529 * errors here. However this would be quite problematic --
530 * we would need to reimplement the Monarch handling and
531 * it would mess up the exclusion between exception handler
532 * and poll hander -- * so we skip this for now.
533 * These cases should not happen anyways, or only when the CPU
534 * is already totally * confused. In this case it's likely it will
535 * not fully execute the machine check handler either.
537 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
542 percpu_inc(mce_poll_count);
546 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
547 for (i = 0; i < banks; i++) {
548 if (!mce_banks[i].ctl || !test_bit(i, *b))
557 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
558 if (!(m.status & MCI_STATUS_VAL))
562 * Uncorrected or signalled events are handled by the exception
563 * handler when it is enabled, so don't process those here.
565 * TBD do the same check for MCI_STATUS_EN here?
567 if (!(flags & MCP_UC) &&
568 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
571 if (m.status & MCI_STATUS_MISCV)
572 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
573 if (m.status & MCI_STATUS_ADDRV)
574 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
576 if (!(flags & MCP_TIMESTAMP))
579 * Don't get the IP here because it's unlikely to
580 * have anything to do with the actual error location.
582 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce) {
584 atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, &m);
588 * Clear state for this bank.
590 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
594 * Don't clear MCG_STATUS here because it's only defined for
600 EXPORT_SYMBOL_GPL(machine_check_poll);
603 * Do a quick check if any of the events requires a panic.
604 * This decides if we keep the events around or clear them.
606 static int mce_no_way_out(struct mce *m, char **msg)
610 for (i = 0; i < banks; i++) {
611 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
612 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
619 * Variable to establish order between CPUs while scanning.
620 * Each CPU spins initially until executing is equal its number.
622 static atomic_t mce_executing;
625 * Defines order of CPUs on entry. First CPU becomes Monarch.
627 static atomic_t mce_callin;
630 * Check if a timeout waiting for other CPUs happened.
632 static int mce_timed_out(u64 *t)
635 * The others already did panic for some reason.
636 * Bail out like in a timeout.
637 * rmb() to tell the compiler that system_state
638 * might have been modified by someone else.
641 if (atomic_read(&mce_paniced))
643 if (!monarch_timeout)
645 if ((s64)*t < SPINUNIT) {
646 /* CHECKME: Make panic default for 1 too? */
648 mce_panic("Timeout synchronizing machine check over CPUs",
655 touch_nmi_watchdog();
660 * The Monarch's reign. The Monarch is the CPU who entered
661 * the machine check handler first. It waits for the others to
662 * raise the exception too and then grades them. When any
663 * error is fatal panic. Only then let the others continue.
665 * The other CPUs entering the MCE handler will be controlled by the
666 * Monarch. They are called Subjects.
668 * This way we prevent any potential data corruption in a unrecoverable case
669 * and also makes sure always all CPU's errors are examined.
671 * Also this detects the case of a machine check event coming from outer
672 * space (not detected by any CPUs) In this case some external agent wants
673 * us to shut down, so panic too.
675 * The other CPUs might still decide to panic if the handler happens
676 * in a unrecoverable place, but in this case the system is in a semi-stable
677 * state and won't corrupt anything by itself. It's ok to let the others
678 * continue for a bit first.
680 * All the spin loops have timeouts; when a timeout happens a CPU
681 * typically elects itself to be Monarch.
683 static void mce_reign(void)
686 struct mce *m = NULL;
687 int global_worst = 0;
692 * This CPU is the Monarch and the other CPUs have run
693 * through their handlers.
694 * Grade the severity of the errors of all the CPUs.
696 for_each_possible_cpu(cpu) {
697 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
699 if (severity > global_worst) {
701 global_worst = severity;
702 m = &per_cpu(mces_seen, cpu);
707 * Cannot recover? Panic here then.
708 * This dumps all the mces in the log buffer and stops the
711 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
712 mce_panic("Fatal Machine check", m, msg);
715 * For UC somewhere we let the CPU who detects it handle it.
716 * Also must let continue the others, otherwise the handling
717 * CPU could deadlock on a lock.
721 * No machine check event found. Must be some external
722 * source or one CPU is hung. Panic.
724 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
725 mce_panic("Machine check from unknown source", NULL, NULL);
728 * Now clear all the mces_seen so that they don't reappear on
731 for_each_possible_cpu(cpu)
732 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
735 static atomic_t global_nwo;
738 * Start of Monarch synchronization. This waits until all CPUs have
739 * entered the exception handler and then determines if any of them
740 * saw a fatal event that requires panic. Then it executes them
741 * in the entry order.
742 * TBD double check parallel CPU hotunplug
744 static int mce_start(int *no_way_out)
747 int cpus = num_online_cpus();
748 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
753 atomic_add(*no_way_out, &global_nwo);
755 * global_nwo should be updated before mce_callin
758 order = atomic_inc_return(&mce_callin);
763 while (atomic_read(&mce_callin) != cpus) {
764 if (mce_timed_out(&timeout)) {
765 atomic_set(&global_nwo, 0);
772 * mce_callin should be read before global_nwo
778 * Monarch: Starts executing now, the others wait.
780 atomic_set(&mce_executing, 1);
783 * Subject: Now start the scanning loop one by one in
784 * the original callin order.
785 * This way when there are any shared banks it will be
786 * only seen by one CPU before cleared, avoiding duplicates.
788 while (atomic_read(&mce_executing) < order) {
789 if (mce_timed_out(&timeout)) {
790 atomic_set(&global_nwo, 0);
798 * Cache the global no_way_out state.
800 *no_way_out = atomic_read(&global_nwo);
806 * Synchronize between CPUs after main scanning loop.
807 * This invokes the bulk of the Monarch processing.
809 static int mce_end(int order)
812 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
820 * Allow others to run.
822 atomic_inc(&mce_executing);
825 /* CHECKME: Can this race with a parallel hotplug? */
826 int cpus = num_online_cpus();
829 * Monarch: Wait for everyone to go through their scanning
832 while (atomic_read(&mce_executing) <= cpus) {
833 if (mce_timed_out(&timeout))
843 * Subject: Wait for Monarch to finish.
845 while (atomic_read(&mce_executing) != 0) {
846 if (mce_timed_out(&timeout))
852 * Don't reset anything. That's done by the Monarch.
858 * Reset all global state.
861 atomic_set(&global_nwo, 0);
862 atomic_set(&mce_callin, 0);
866 * Let others run again.
868 atomic_set(&mce_executing, 0);
873 * Check if the address reported by the CPU is in a format we can parse.
874 * It would be possible to add code for most other cases, but all would
875 * be somewhat complicated (e.g. segment offset would require an instruction
876 * parser). So only support physical addresses up to page granuality for now.
878 static int mce_usable_address(struct mce *m)
880 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
882 if ((m->misc & 0x3f) > PAGE_SHIFT)
884 if (((m->misc >> 6) & 7) != MCM_ADDR_PHYS)
889 static void mce_clear_state(unsigned long *toclear)
893 for (i = 0; i < banks; i++) {
894 if (test_bit(i, toclear))
895 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
900 * The actual machine check handler. This only handles real
901 * exceptions when something got corrupted coming in through int 18.
903 * This is executed in NMI context not subject to normal locking rules. This
904 * implies that most kernel services cannot be safely used. Don't even
905 * think about putting a printk in there!
907 * On Intel systems this is entered on all CPUs in parallel through
908 * MCE broadcast. However some CPUs might be broken beyond repair,
909 * so be always careful when synchronizing with others.
911 void do_machine_check(struct pt_regs *regs, long error_code)
913 struct mce m, *final;
918 * Establish sequential order between the CPUs entering the machine
923 * If no_way_out gets set, there is no safe way to recover from this
924 * MCE. If tolerant is cranked up, we'll try anyway.
928 * If kill_it gets set, there might be a way to recover from this
932 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
933 char *msg = "Unknown";
935 atomic_inc(&mce_entry);
937 percpu_inc(mce_exception_count);
939 if (notify_die(DIE_NMI, "machine check", regs, error_code,
940 18, SIGKILL) == NOTIFY_STOP)
947 m.mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
948 final = &__get_cpu_var(mces_seen);
951 no_way_out = mce_no_way_out(&m, &msg);
956 * When no restart IP must always kill or panic.
958 if (!(m.mcgstatus & MCG_STATUS_RIPV))
962 * Go through all the banks in exclusion of the other CPUs.
963 * This way we don't report duplicated events on shared banks
964 * because the first one to see it will clear it.
966 order = mce_start(&no_way_out);
967 for (i = 0; i < banks; i++) {
968 __clear_bit(i, toclear);
969 if (!mce_banks[i].ctl)
976 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
977 if ((m.status & MCI_STATUS_VAL) == 0)
981 * Non uncorrected or non signaled errors are handled by
982 * machine_check_poll. Leave them alone, unless this panics.
984 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
989 * Set taint even when machine check was not enabled.
991 add_taint(TAINT_MACHINE_CHECK);
993 severity = mce_severity(&m, tolerant, NULL);
996 * When machine check was for corrected handler don't touch,
997 * unless we're panicing.
999 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
1001 __set_bit(i, toclear);
1002 if (severity == MCE_NO_SEVERITY) {
1004 * Machine check event was not enabled. Clear, but
1011 * Kill on action required.
1013 if (severity == MCE_AR_SEVERITY)
1016 if (m.status & MCI_STATUS_MISCV)
1017 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
1018 if (m.status & MCI_STATUS_ADDRV)
1019 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
1022 * Action optional error. Queue address for later processing.
1023 * When the ring overflows we just ignore the AO error.
1024 * RED-PEN add some logging mechanism when
1025 * usable_address or mce_add_ring fails.
1026 * RED-PEN don't ignore overflow for tolerant == 0
1028 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1029 mce_ring_add(m.addr >> PAGE_SHIFT);
1031 mce_get_rip(&m, regs);
1034 if (severity > worst) {
1041 mce_clear_state(toclear);
1044 * Do most of the synchronization with other CPUs.
1045 * When there's any problem use only local no_way_out state.
1047 if (mce_end(order) < 0)
1048 no_way_out = worst >= MCE_PANIC_SEVERITY;
1051 * If we have decided that we just CAN'T continue, and the user
1052 * has not set tolerant to an insane level, give up and die.
1054 * This is mainly used in the case when the system doesn't
1055 * support MCE broadcasting or it has been disabled.
1057 if (no_way_out && tolerant < 3)
1058 mce_panic("Fatal machine check on current CPU", final, msg);
1061 * If the error seems to be unrecoverable, something should be
1062 * done. Try to kill as little as possible. If we can kill just
1063 * one task, do that. If the user has set the tolerance very
1064 * high, don't try to do anything at all.
1067 if (kill_it && tolerant < 3)
1068 force_sig(SIGBUS, current);
1070 /* notify userspace ASAP */
1071 set_thread_flag(TIF_MCE_NOTIFY);
1074 mce_report_event(regs);
1075 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1077 atomic_dec(&mce_entry);
1080 EXPORT_SYMBOL_GPL(do_machine_check);
1082 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1083 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1085 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1089 * Called after mce notification in process context. This code
1090 * is allowed to sleep. Call the high level VM handler to process
1091 * any corrupted pages.
1092 * Assume that the work queue code only calls this one at a time
1094 * Note we don't disable preemption, so this code might run on the wrong
1095 * CPU. In this case the event is picked up by the scheduled work queue.
1096 * This is merely a fast path to expedite processing in some common
1099 void mce_notify_process(void)
1103 while (mce_ring_get(&pfn))
1104 memory_failure(pfn, MCE_VECTOR);
1107 static void mce_process_work(struct work_struct *dummy)
1109 mce_notify_process();
1112 #ifdef CONFIG_X86_MCE_INTEL
1114 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1115 * @cpu: The CPU on which the event occurred.
1116 * @status: Event status information
1118 * This function should be called by the thermal interrupt after the
1119 * event has been processed and the decision was made to log the event
1122 * The status parameter will be saved to the 'status' field of 'struct mce'
1123 * and historically has been the register value of the
1124 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1126 void mce_log_therm_throt_event(__u64 status)
1131 m.bank = MCE_THERMAL_BANK;
1135 #endif /* CONFIG_X86_MCE_INTEL */
1138 * Periodic polling timer for "silent" machine check errors. If the
1139 * poller finds an MCE, poll 2x faster. When the poller finds no more
1140 * errors, poll 2x slower (up to check_interval seconds).
1142 static int check_interval = 5 * 60; /* 5 minutes */
1144 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1145 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1147 static void mce_start_timer(unsigned long data)
1149 struct timer_list *t = &per_cpu(mce_timer, data);
1152 WARN_ON(smp_processor_id() != data);
1154 if (mce_available(__this_cpu_ptr(&cpu_info))) {
1155 machine_check_poll(MCP_TIMESTAMP,
1156 &__get_cpu_var(mce_poll_banks));
1160 * Alert userspace if needed. If we logged an MCE, reduce the
1161 * polling interval, otherwise increase the polling interval.
1163 n = &__get_cpu_var(mce_next_interval);
1164 if (mce_notify_irq())
1165 *n = max(*n/2, HZ/100);
1167 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1169 t->expires = jiffies + *n;
1170 add_timer_on(t, smp_processor_id());
1173 static void mce_do_trigger(struct work_struct *work)
1175 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1178 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1181 * Notify the user(s) about new machine check events.
1182 * Can be called from interrupt context, but not from machine check/NMI
1185 int mce_notify_irq(void)
1187 /* Not more than two messages every minute */
1188 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1190 clear_thread_flag(TIF_MCE_NOTIFY);
1192 if (test_and_clear_bit(0, &mce_need_notify)) {
1193 wake_up_interruptible(&mce_wait);
1196 * There is no risk of missing notifications because
1197 * work_pending is always cleared before the function is
1200 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1201 schedule_work(&mce_trigger_work);
1203 if (__ratelimit(&ratelimit))
1204 pr_info(HW_ERR "Machine check events logged\n");
1210 EXPORT_SYMBOL_GPL(mce_notify_irq);
1212 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1216 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1219 for (i = 0; i < banks; i++) {
1220 struct mce_bank *b = &mce_banks[i];
1229 * Initialize Machine Checks for a CPU.
1231 static int __cpuinit __mcheck_cpu_cap_init(void)
1236 rdmsrl(MSR_IA32_MCG_CAP, cap);
1238 b = cap & MCG_BANKCNT_MASK;
1240 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1242 if (b > MAX_NR_BANKS) {
1244 "MCE: Using only %u machine check banks out of %u\n",
1249 /* Don't support asymmetric configurations today */
1250 WARN_ON(banks != 0 && b != banks);
1253 int err = __mcheck_cpu_mce_banks_init();
1259 /* Use accurate RIP reporting if available. */
1260 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1261 rip_msr = MSR_IA32_MCG_EIP;
1263 if (cap & MCG_SER_P)
1269 static void __mcheck_cpu_init_generic(void)
1271 mce_banks_t all_banks;
1276 * Log the machine checks left over from the previous reset.
1278 bitmap_fill(all_banks, MAX_NR_BANKS);
1279 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1281 set_in_cr4(X86_CR4_MCE);
1283 rdmsrl(MSR_IA32_MCG_CAP, cap);
1284 if (cap & MCG_CTL_P)
1285 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1287 for (i = 0; i < banks; i++) {
1288 struct mce_bank *b = &mce_banks[i];
1292 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1293 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1297 /* Add per CPU specific workarounds here */
1298 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1300 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1301 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1305 /* This should be disabled by the BIOS, but isn't always */
1306 if (c->x86_vendor == X86_VENDOR_AMD) {
1307 if (c->x86 == 15 && banks > 4) {
1309 * disable GART TBL walk error reporting, which
1310 * trips off incorrectly with the IOMMU & 3ware
1313 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1315 if (c->x86 <= 17 && mce_bootlog < 0) {
1317 * Lots of broken BIOS around that don't clear them
1318 * by default and leave crap in there. Don't log:
1323 * Various K7s with broken bank 0 around. Always disable
1326 if (c->x86 == 6 && banks > 0)
1327 mce_banks[0].ctl = 0;
1330 if (c->x86_vendor == X86_VENDOR_INTEL) {
1332 * SDM documents that on family 6 bank 0 should not be written
1333 * because it aliases to another special BIOS controlled
1335 * But it's not aliased anymore on model 0x1a+
1336 * Don't ignore bank 0 completely because there could be a
1337 * valid event later, merely don't write CTL0.
1340 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1341 mce_banks[0].init = 0;
1344 * All newer Intel systems support MCE broadcasting. Enable
1345 * synchronization with a one second timeout.
1347 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1348 monarch_timeout < 0)
1349 monarch_timeout = USEC_PER_SEC;
1352 * There are also broken BIOSes on some Pentium M and
1355 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1358 if (monarch_timeout < 0)
1359 monarch_timeout = 0;
1360 if (mce_bootlog != 0)
1361 mce_panic_timeout = 30;
1366 static void __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1370 switch (c->x86_vendor) {
1371 case X86_VENDOR_INTEL:
1372 intel_p5_mcheck_init(c);
1374 case X86_VENDOR_CENTAUR:
1375 winchip_mcheck_init(c);
1380 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1382 switch (c->x86_vendor) {
1383 case X86_VENDOR_INTEL:
1384 mce_intel_feature_init(c);
1386 case X86_VENDOR_AMD:
1387 mce_amd_feature_init(c);
1394 static void __mcheck_cpu_init_timer(void)
1396 struct timer_list *t = &__get_cpu_var(mce_timer);
1397 int *n = &__get_cpu_var(mce_next_interval);
1399 setup_timer(t, mce_start_timer, smp_processor_id());
1404 *n = check_interval * HZ;
1407 t->expires = round_jiffies(jiffies + *n);
1408 add_timer_on(t, smp_processor_id());
1411 /* Handle unconfigured int18 (should never happen) */
1412 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1414 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1415 smp_processor_id());
1418 /* Call the installed machine check handler for this CPU setup. */
1419 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1420 unexpected_machine_check;
1423 * Called for each booted CPU to set up machine checks.
1424 * Must be called with preempt off:
1426 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1431 __mcheck_cpu_ancient_init(c);
1433 if (!mce_available(c))
1436 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1441 machine_check_vector = do_machine_check;
1443 __mcheck_cpu_init_generic();
1444 __mcheck_cpu_init_vendor(c);
1445 __mcheck_cpu_init_timer();
1446 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1451 * Character device to read and clear the MCE log.
1454 static DEFINE_SPINLOCK(mce_state_lock);
1455 static int open_count; /* #times opened */
1456 static int open_exclu; /* already open exclusive? */
1458 static int mce_open(struct inode *inode, struct file *file)
1460 spin_lock(&mce_state_lock);
1462 if (open_exclu || (open_count && (file->f_flags & O_EXCL))) {
1463 spin_unlock(&mce_state_lock);
1468 if (file->f_flags & O_EXCL)
1472 spin_unlock(&mce_state_lock);
1474 return nonseekable_open(inode, file);
1477 static int mce_release(struct inode *inode, struct file *file)
1479 spin_lock(&mce_state_lock);
1484 spin_unlock(&mce_state_lock);
1489 static void collect_tscs(void *data)
1491 unsigned long *cpu_tsc = (unsigned long *)data;
1493 rdtscll(cpu_tsc[smp_processor_id()]);
1496 static int mce_apei_read_done;
1498 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1499 static int __mce_read_apei(char __user **ubuf, size_t usize)
1505 if (usize < sizeof(struct mce))
1508 rc = apei_read_mce(&m, &record_id);
1509 /* Error or no more MCE record */
1511 mce_apei_read_done = 1;
1515 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1518 * In fact, we should have cleared the record after that has
1519 * been flushed to the disk or sent to network in
1520 * /sbin/mcelog, but we have no interface to support that now,
1521 * so just clear it to avoid duplication.
1523 rc = apei_clear_mce(record_id);
1525 mce_apei_read_done = 1;
1528 *ubuf += sizeof(struct mce);
1533 static ssize_t mce_read(struct file *filp, char __user *ubuf, size_t usize,
1536 char __user *buf = ubuf;
1537 unsigned long *cpu_tsc;
1538 unsigned prev, next;
1541 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1545 mutex_lock(&mce_read_mutex);
1547 if (!mce_apei_read_done) {
1548 err = __mce_read_apei(&buf, usize);
1549 if (err || buf != ubuf)
1553 next = rcu_dereference_check_mce(mcelog.next);
1555 /* Only supports full reads right now */
1557 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1563 for (i = prev; i < next; i++) {
1564 unsigned long start = jiffies;
1566 while (!mcelog.entry[i].finished) {
1567 if (time_after_eq(jiffies, start + 2)) {
1568 memset(mcelog.entry + i, 0,
1569 sizeof(struct mce));
1575 err |= copy_to_user(buf, mcelog.entry + i,
1576 sizeof(struct mce));
1577 buf += sizeof(struct mce);
1582 memset(mcelog.entry + prev, 0,
1583 (next - prev) * sizeof(struct mce));
1585 next = cmpxchg(&mcelog.next, prev, 0);
1586 } while (next != prev);
1588 synchronize_sched();
1591 * Collect entries that were still getting written before the
1594 on_each_cpu(collect_tscs, cpu_tsc, 1);
1596 for (i = next; i < MCE_LOG_LEN; i++) {
1597 if (mcelog.entry[i].finished &&
1598 mcelog.entry[i].tsc < cpu_tsc[mcelog.entry[i].cpu]) {
1599 err |= copy_to_user(buf, mcelog.entry+i,
1600 sizeof(struct mce));
1602 buf += sizeof(struct mce);
1603 memset(&mcelog.entry[i], 0, sizeof(struct mce));
1611 mutex_unlock(&mce_read_mutex);
1614 return err ? err : buf - ubuf;
1617 static unsigned int mce_poll(struct file *file, poll_table *wait)
1619 poll_wait(file, &mce_wait, wait);
1620 if (rcu_access_index(mcelog.next))
1621 return POLLIN | POLLRDNORM;
1622 if (!mce_apei_read_done && apei_check_mce())
1623 return POLLIN | POLLRDNORM;
1627 static long mce_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
1629 int __user *p = (int __user *)arg;
1631 if (!capable(CAP_SYS_ADMIN))
1635 case MCE_GET_RECORD_LEN:
1636 return put_user(sizeof(struct mce), p);
1637 case MCE_GET_LOG_LEN:
1638 return put_user(MCE_LOG_LEN, p);
1639 case MCE_GETCLEAR_FLAGS: {
1643 flags = mcelog.flags;
1644 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1646 return put_user(flags, p);
1653 /* Modified in mce-inject.c, so not static or const */
1654 struct file_operations mce_chrdev_ops = {
1656 .release = mce_release,
1659 .unlocked_ioctl = mce_ioctl,
1660 .llseek = no_llseek,
1662 EXPORT_SYMBOL_GPL(mce_chrdev_ops);
1664 static struct miscdevice mce_log_device = {
1671 * mce=off Disables machine check
1672 * mce=no_cmci Disables CMCI
1673 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1674 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1675 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1676 * monarchtimeout is how long to wait for other CPUs on machine
1677 * check, or 0 to not wait
1678 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1679 * mce=nobootlog Don't log MCEs from before booting.
1681 static int __init mcheck_enable(char *str)
1689 if (!strcmp(str, "off"))
1691 else if (!strcmp(str, "no_cmci"))
1692 mce_cmci_disabled = 1;
1693 else if (!strcmp(str, "dont_log_ce"))
1694 mce_dont_log_ce = 1;
1695 else if (!strcmp(str, "ignore_ce"))
1697 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1698 mce_bootlog = (str[0] == 'b');
1699 else if (isdigit(str[0])) {
1700 get_option(&str, &tolerant);
1703 get_option(&str, &monarch_timeout);
1706 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1712 __setup("mce", mcheck_enable);
1714 int __init mcheck_init(void)
1716 mcheck_intel_therm_init();
1726 * Disable machine checks on suspend and shutdown. We can't really handle
1729 static int mce_disable_error_reporting(void)
1733 for (i = 0; i < banks; i++) {
1734 struct mce_bank *b = &mce_banks[i];
1737 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1742 static int mce_suspend(void)
1744 return mce_disable_error_reporting();
1747 static void mce_shutdown(void)
1749 mce_disable_error_reporting();
1753 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1754 * Only one CPU is active at this time, the others get re-added later using
1757 static void mce_resume(void)
1759 __mcheck_cpu_init_generic();
1760 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
1763 static struct syscore_ops mce_syscore_ops = {
1764 .suspend = mce_suspend,
1765 .shutdown = mce_shutdown,
1766 .resume = mce_resume,
1769 static void mce_cpu_restart(void *data)
1771 del_timer_sync(&__get_cpu_var(mce_timer));
1772 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1774 __mcheck_cpu_init_generic();
1775 __mcheck_cpu_init_timer();
1778 /* Reinit MCEs after user configuration changes */
1779 static void mce_restart(void)
1781 on_each_cpu(mce_cpu_restart, NULL, 1);
1784 /* Toggle features for corrected errors */
1785 static void mce_disable_ce(void *all)
1787 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1790 del_timer_sync(&__get_cpu_var(mce_timer));
1794 static void mce_enable_ce(void *all)
1796 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1801 __mcheck_cpu_init_timer();
1804 static struct sysdev_class mce_sysclass = {
1805 .name = "machinecheck",
1808 DEFINE_PER_CPU(struct sys_device, mce_dev);
1811 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1813 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1815 return container_of(attr, struct mce_bank, attr);
1818 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1821 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1824 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1825 const char *buf, size_t size)
1829 if (strict_strtoull(buf, 0, &new) < 0)
1832 attr_to_bank(attr)->ctl = new;
1839 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1841 strcpy(buf, mce_helper);
1843 return strlen(mce_helper) + 1;
1846 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1847 const char *buf, size_t siz)
1851 strncpy(mce_helper, buf, sizeof(mce_helper));
1852 mce_helper[sizeof(mce_helper)-1] = 0;
1853 p = strchr(mce_helper, '\n');
1858 return strlen(mce_helper) + !!p;
1861 static ssize_t set_ignore_ce(struct sys_device *s,
1862 struct sysdev_attribute *attr,
1863 const char *buf, size_t size)
1867 if (strict_strtoull(buf, 0, &new) < 0)
1870 if (mce_ignore_ce ^ !!new) {
1872 /* disable ce features */
1873 on_each_cpu(mce_disable_ce, (void *)1, 1);
1876 /* enable ce features */
1878 on_each_cpu(mce_enable_ce, (void *)1, 1);
1884 static ssize_t set_cmci_disabled(struct sys_device *s,
1885 struct sysdev_attribute *attr,
1886 const char *buf, size_t size)
1890 if (strict_strtoull(buf, 0, &new) < 0)
1893 if (mce_cmci_disabled ^ !!new) {
1896 on_each_cpu(mce_disable_ce, NULL, 1);
1897 mce_cmci_disabled = 1;
1900 mce_cmci_disabled = 0;
1901 on_each_cpu(mce_enable_ce, NULL, 1);
1907 static ssize_t store_int_with_restart(struct sys_device *s,
1908 struct sysdev_attribute *attr,
1909 const char *buf, size_t size)
1911 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1916 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1917 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1918 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1919 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1921 static struct sysdev_ext_attribute attr_check_interval = {
1922 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1923 store_int_with_restart),
1927 static struct sysdev_ext_attribute attr_ignore_ce = {
1928 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1932 static struct sysdev_ext_attribute attr_cmci_disabled = {
1933 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1937 static struct sysdev_attribute *mce_attrs[] = {
1938 &attr_tolerant.attr,
1939 &attr_check_interval.attr,
1941 &attr_monarch_timeout.attr,
1942 &attr_dont_log_ce.attr,
1943 &attr_ignore_ce.attr,
1944 &attr_cmci_disabled.attr,
1948 static cpumask_var_t mce_dev_initialized;
1950 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1951 static __cpuinit int mce_create_device(unsigned int cpu)
1956 if (!mce_available(&boot_cpu_data))
1959 memset(&per_cpu(mce_dev, cpu).kobj, 0, sizeof(struct kobject));
1960 per_cpu(mce_dev, cpu).id = cpu;
1961 per_cpu(mce_dev, cpu).cls = &mce_sysclass;
1963 err = sysdev_register(&per_cpu(mce_dev, cpu));
1967 for (i = 0; mce_attrs[i]; i++) {
1968 err = sysdev_create_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1972 for (j = 0; j < banks; j++) {
1973 err = sysdev_create_file(&per_cpu(mce_dev, cpu),
1974 &mce_banks[j].attr);
1978 cpumask_set_cpu(cpu, mce_dev_initialized);
1983 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[j].attr);
1986 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
1988 sysdev_unregister(&per_cpu(mce_dev, cpu));
1993 static __cpuinit void mce_remove_device(unsigned int cpu)
1997 if (!cpumask_test_cpu(cpu, mce_dev_initialized))
2000 for (i = 0; mce_attrs[i]; i++)
2001 sysdev_remove_file(&per_cpu(mce_dev, cpu), mce_attrs[i]);
2003 for (i = 0; i < banks; i++)
2004 sysdev_remove_file(&per_cpu(mce_dev, cpu), &mce_banks[i].attr);
2006 sysdev_unregister(&per_cpu(mce_dev, cpu));
2007 cpumask_clear_cpu(cpu, mce_dev_initialized);
2010 /* Make sure there are no machine checks on offlined CPUs. */
2011 static void __cpuinit mce_disable_cpu(void *h)
2013 unsigned long action = *(unsigned long *)h;
2016 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2019 if (!(action & CPU_TASKS_FROZEN))
2021 for (i = 0; i < banks; i++) {
2022 struct mce_bank *b = &mce_banks[i];
2025 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2029 static void __cpuinit mce_reenable_cpu(void *h)
2031 unsigned long action = *(unsigned long *)h;
2034 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2037 if (!(action & CPU_TASKS_FROZEN))
2039 for (i = 0; i < banks; i++) {
2040 struct mce_bank *b = &mce_banks[i];
2043 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2047 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2048 static int __cpuinit
2049 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2051 unsigned int cpu = (unsigned long)hcpu;
2052 struct timer_list *t = &per_cpu(mce_timer, cpu);
2056 case CPU_ONLINE_FROZEN:
2057 mce_create_device(cpu);
2058 if (threshold_cpu_callback)
2059 threshold_cpu_callback(action, cpu);
2062 case CPU_DEAD_FROZEN:
2063 if (threshold_cpu_callback)
2064 threshold_cpu_callback(action, cpu);
2065 mce_remove_device(cpu);
2067 case CPU_DOWN_PREPARE:
2068 case CPU_DOWN_PREPARE_FROZEN:
2070 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2072 case CPU_DOWN_FAILED:
2073 case CPU_DOWN_FAILED_FROZEN:
2074 if (!mce_ignore_ce && check_interval) {
2075 t->expires = round_jiffies(jiffies +
2076 __get_cpu_var(mce_next_interval));
2077 add_timer_on(t, cpu);
2079 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2082 /* intentionally ignoring frozen here */
2083 cmci_rediscover(cpu);
2089 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2090 .notifier_call = mce_cpu_callback,
2093 static __init void mce_init_banks(void)
2097 for (i = 0; i < banks; i++) {
2098 struct mce_bank *b = &mce_banks[i];
2099 struct sysdev_attribute *a = &b->attr;
2101 sysfs_attr_init(&a->attr);
2102 a->attr.name = b->attrname;
2103 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2105 a->attr.mode = 0644;
2106 a->show = show_bank;
2107 a->store = set_bank;
2111 static __init int mcheck_init_device(void)
2116 if (!mce_available(&boot_cpu_data))
2119 zalloc_cpumask_var(&mce_dev_initialized, GFP_KERNEL);
2123 err = sysdev_class_register(&mce_sysclass);
2127 for_each_online_cpu(i) {
2128 err = mce_create_device(i);
2133 register_syscore_ops(&mce_syscore_ops);
2134 register_hotcpu_notifier(&mce_cpu_notifier);
2135 misc_register(&mce_log_device);
2140 device_initcall(mcheck_init_device);
2143 * Old style boot options parsing. Only for compatibility.
2145 static int __init mcheck_disable(char *str)
2150 __setup("nomce", mcheck_disable);
2152 #ifdef CONFIG_DEBUG_FS
2153 struct dentry *mce_get_debugfs_dir(void)
2155 static struct dentry *dmce;
2158 dmce = debugfs_create_dir("mce", NULL);
2163 static void mce_reset(void)
2166 atomic_set(&mce_fake_paniced, 0);
2167 atomic_set(&mce_executing, 0);
2168 atomic_set(&mce_callin, 0);
2169 atomic_set(&global_nwo, 0);
2172 static int fake_panic_get(void *data, u64 *val)
2178 static int fake_panic_set(void *data, u64 val)
2185 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2186 fake_panic_set, "%llu\n");
2188 static int __init mcheck_debugfs_init(void)
2190 struct dentry *dmce, *ffake_panic;
2192 dmce = mce_get_debugfs_dir();
2195 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2202 late_initcall(mcheck_debugfs_init);