2 * Routines to indentify additional cpu features that are scattered in
8 #include <asm/processor.h>
26 void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c)
30 const struct cpuid_bit *cb;
32 static const struct cpuid_bit __cpuinitconst cpuid_bits[] = {
33 { X86_FEATURE_IDA, CR_EAX, 1, 0x00000006 },
34 { X86_FEATURE_ARAT, CR_EAX, 2, 0x00000006 },
38 for (cb = cpuid_bits; cb->feature; cb++) {
40 /* Verify that the level is valid */
41 max_level = cpuid_eax(cb->level & 0xffff0000);
42 if (max_level < cb->level ||
43 max_level > (cb->level | 0xffff))
46 cpuid(cb->level, ®s[CR_EAX], ®s[CR_EBX],
47 ®s[CR_ECX], ®s[CR_EDX]);
49 if (regs[cb->reg] & (1 << cb->bit))
50 set_cpu_cap(c, cb->feature);
54 /* leaf 0xb SMT level */
57 /* leaf 0xb sub-leaf types */
58 #define INVALID_TYPE 0
62 #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
63 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
64 #define LEVEL_MAX_SIBLINGS(ebx) ((ebx) & 0xffff)
67 * Check for extended topology enumeration cpuid leaf 0xb and if it
68 * exists, use it for populating initial_apicid and cpu topology
71 void __cpuinit detect_extended_topology(struct cpuinfo_x86 *c)
74 unsigned int eax, ebx, ecx, edx, sub_index;
75 unsigned int ht_mask_width, core_plus_mask_width;
76 unsigned int core_select_mask, core_level_siblings;
79 if (c->cpuid_level < 0xb)
82 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
85 * check if the cpuid leaf 0xb is actually implemented.
87 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE))
90 set_cpu_cap(c, X86_FEATURE_XTOPOLOGY);
93 * initial apic id, which also represents 32-bit extended x2apic id.
95 c->initial_apicid = edx;
98 * Populate HT related information from sub-leaf level 0.
100 core_level_siblings = smp_num_siblings = LEVEL_MAX_SIBLINGS(ebx);
101 core_plus_mask_width = ht_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);
105 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
108 * Check for the Core type in the implemented sub leaves.
110 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
111 core_level_siblings = LEVEL_MAX_SIBLINGS(ebx);
112 core_plus_mask_width = BITS_SHIFT_NEXT_LEVEL(eax);
117 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
119 core_select_mask = (~(-1 << core_plus_mask_width)) >> ht_mask_width;
121 c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, ht_mask_width)
123 c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, core_plus_mask_width);
125 * Reinit the apicid, now that we have extended initial_apicid.
127 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
129 c->x86_max_cores = (core_level_siblings / smp_num_siblings);
132 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
134 if (c->x86_max_cores > 1)
135 printk(KERN_INFO "CPU: Processor Core ID: %d\n",