2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
31 #include <asm/atomic.h>
34 #include <asm/mpspec.h>
36 #include <asm/pgalloc.h>
39 #include <asm/proto.h>
40 #include <asm/timex.h>
44 #include <mach_apic.h>
46 int disable_apic_timer __cpuinitdata;
47 static int apic_calibrate_pmtmr __initdata;
50 /* Local APIC timer works in C2 */
51 int local_apic_timer_c2_ok;
52 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
55 * Debug level, exported for io_apic.c
59 static struct resource lapic_resource = {
61 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
64 static unsigned int calibration_result;
66 static int lapic_next_event(unsigned long delta,
67 struct clock_event_device *evt);
68 static void lapic_timer_setup(enum clock_event_mode mode,
69 struct clock_event_device *evt);
70 static void lapic_timer_broadcast(cpumask_t mask);
71 static void apic_pm_activate(void);
73 static struct clock_event_device lapic_clockevent = {
75 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
76 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
78 .set_mode = lapic_timer_setup,
79 .set_next_event = lapic_next_event,
80 .broadcast = lapic_timer_broadcast,
84 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
86 static unsigned long apic_phys;
88 unsigned long mp_lapic_addr;
90 /* Processor that is doing the boot up */
91 unsigned int boot_cpu_physical_apicid = -1U;
92 EXPORT_SYMBOL(boot_cpu_physical_apicid);
95 * Get the LAPIC version
97 static inline int lapic_get_version(void)
99 return GET_APIC_VERSION(apic_read(APIC_LVR));
103 * Check, if the APIC is integrated or a seperate chip
105 static inline int lapic_is_integrated(void)
111 * Check, whether this is a modern or a first generation APIC
113 static int modern_apic(void)
115 /* AMD systems use old APIC versions, so check the CPU */
116 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
117 boot_cpu_data.x86 >= 0xf)
119 return lapic_get_version() >= 0x14;
122 void apic_wait_icr_idle(void)
124 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
128 u32 safe_apic_wait_icr_idle(void)
135 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
139 } while (timeout++ < 1000);
145 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
147 void __cpuinit enable_NMI_through_LVT0(void)
151 /* unmask and set to NMI */
153 apic_write(APIC_LVT0, v);
157 * lapic_get_maxlvt - get the maximum number of local vector table entries
159 int lapic_get_maxlvt(void)
161 unsigned int v, maxlvt;
163 v = apic_read(APIC_LVR);
164 maxlvt = GET_APIC_MAXLVT(v);
169 * This function sets up the local APIC timer, with a timeout of
170 * 'clocks' APIC bus clock. During calibration we actually call
171 * this function twice on the boot CPU, once with a bogus timeout
172 * value, second time for real. The other (noncalibrating) CPUs
173 * call this function only once, with the real, calibrated value.
175 * We do reads before writes even if unnecessary, to get around the
176 * P5 APIC double write bug.
179 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
181 unsigned int lvtt_value, tmp_value;
183 lvtt_value = LOCAL_TIMER_VECTOR;
185 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
187 lvtt_value |= APIC_LVT_MASKED;
189 apic_write(APIC_LVTT, lvtt_value);
194 tmp_value = apic_read(APIC_TDCR);
195 apic_write(APIC_TDCR, (tmp_value
196 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
200 apic_write(APIC_TMICT, clocks);
204 * Setup extended LVT, AMD specific (K8, family 10h)
206 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
207 * MCE interrupts are supported. Thus MCE offset must be set to 0.
210 #define APIC_EILVT_LVTOFF_MCE 0
211 #define APIC_EILVT_LVTOFF_IBS 1
213 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
215 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
216 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
221 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
223 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
224 return APIC_EILVT_LVTOFF_MCE;
227 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
229 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
230 return APIC_EILVT_LVTOFF_IBS;
234 * Program the next event, relative to now
236 static int lapic_next_event(unsigned long delta,
237 struct clock_event_device *evt)
239 apic_write(APIC_TMICT, delta);
244 * Setup the lapic timer in periodic or oneshot mode
246 static void lapic_timer_setup(enum clock_event_mode mode,
247 struct clock_event_device *evt)
252 /* Lapic used as dummy for broadcast ? */
253 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
256 local_irq_save(flags);
259 case CLOCK_EVT_MODE_PERIODIC:
260 case CLOCK_EVT_MODE_ONESHOT:
261 __setup_APIC_LVTT(calibration_result,
262 mode != CLOCK_EVT_MODE_PERIODIC, 1);
264 case CLOCK_EVT_MODE_UNUSED:
265 case CLOCK_EVT_MODE_SHUTDOWN:
266 v = apic_read(APIC_LVTT);
267 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
268 apic_write(APIC_LVTT, v);
270 case CLOCK_EVT_MODE_RESUME:
271 /* Nothing to do here */
275 local_irq_restore(flags);
279 * Local APIC timer broadcast function
281 static void lapic_timer_broadcast(cpumask_t mask)
284 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
289 * Setup the local APIC timer for this CPU. Copy the initilized values
290 * of the boot CPU and register the clock event in the framework.
292 static void setup_APIC_timer(void)
294 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
296 memcpy(levt, &lapic_clockevent, sizeof(*levt));
297 levt->cpumask = cpumask_of_cpu(smp_processor_id());
299 clockevents_register_device(levt);
303 * In this function we calibrate APIC bus clocks to the external
304 * timer. Unfortunately we cannot use jiffies and the timer irq
305 * to calibrate, since some later bootup code depends on getting
306 * the first irq? Ugh.
308 * We want to do the calibration only once since we
309 * want to have local timer irqs syncron. CPUs connected
310 * by the same APIC bus have the very same bus frequency.
311 * And we want to have irqs off anyways, no accidental
315 #define TICK_COUNT 100000000
317 static void __init calibrate_APIC_clock(void)
319 unsigned apic, apic_start;
320 unsigned long tsc, tsc_start;
326 * Put whatever arbitrary (but long enough) timeout
327 * value into the APIC clock, we just want to get the
328 * counter running for calibration.
330 * No interrupt enable !
332 __setup_APIC_LVTT(250000000, 0, 0);
334 apic_start = apic_read(APIC_TMCCT);
335 #ifdef CONFIG_X86_PM_TIMER
336 if (apic_calibrate_pmtmr && pmtmr_ioport) {
337 pmtimer_wait(5000); /* 5ms wait */
338 apic = apic_read(APIC_TMCCT);
339 result = (apic_start - apic) * 1000L / 5;
346 apic = apic_read(APIC_TMCCT);
348 } while ((tsc - tsc_start) < TICK_COUNT &&
349 (apic_start - apic) < TICK_COUNT);
351 result = (apic_start - apic) * 1000L * tsc_khz /
357 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
359 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
360 result / 1000 / 1000, result / 1000 % 1000);
362 /* Calculate the scaled math multiplication factor */
363 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, 32);
364 lapic_clockevent.max_delta_ns =
365 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
366 lapic_clockevent.min_delta_ns =
367 clockevent_delta2ns(0xF, &lapic_clockevent);
369 calibration_result = result / HZ;
373 * Setup the boot APIC
375 * Calibrate and verify the result.
377 void __init setup_boot_APIC_clock(void)
380 * The local apic timer can be disabled via the kernel commandline.
381 * Register the lapic timer as a dummy clock event source on SMP
382 * systems, so the broadcast mechanism is used. On UP systems simply
385 if (disable_apic_timer) {
386 printk(KERN_INFO "Disabling APIC timer\n");
387 /* No broadcast on UP ! */
388 if (num_possible_cpus() > 1) {
389 lapic_clockevent.mult = 1;
395 printk(KERN_INFO "Using local APIC timer interrupts.\n");
396 calibrate_APIC_clock();
399 * Do a sanity check on the APIC calibration result
401 if (calibration_result < (1000000 / HZ)) {
403 "APIC frequency too slow, disabling apic timer\n");
404 /* No broadcast on UP ! */
405 if (num_possible_cpus() > 1)
411 * If nmi_watchdog is set to IO_APIC, we need the
412 * PIT/HPET going. Otherwise register lapic as a dummy
415 if (nmi_watchdog != NMI_IO_APIC)
416 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
418 printk(KERN_WARNING "APIC timer registered as dummy,"
419 " due to nmi_watchdog=1!\n");
425 * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
426 * C1E flag only in the secondary CPU, so when we detect the wreckage
427 * we already have enabled the boot CPU local apic timer. Check, if
428 * disable_apic_timer is set and the DUMMY flag is cleared. If yes,
429 * set the DUMMY flag again and force the broadcast mode in the
432 void __cpuinit check_boot_apic_timer_broadcast(void)
434 if (!disable_apic_timer ||
435 (lapic_clockevent.features & CLOCK_EVT_FEAT_DUMMY))
438 printk(KERN_INFO "AMD C1E detected late. Force timer broadcast.\n");
439 lapic_clockevent.features |= CLOCK_EVT_FEAT_DUMMY;
442 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
443 &boot_cpu_physical_apicid);
447 void __cpuinit setup_secondary_APIC_clock(void)
449 check_boot_apic_timer_broadcast();
454 * The guts of the apic timer interrupt
456 static void local_apic_timer_interrupt(void)
458 int cpu = smp_processor_id();
459 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
462 * Normally we should not be here till LAPIC has been initialized but
463 * in some cases like kdump, its possible that there is a pending LAPIC
464 * timer interrupt from previous kernel's context and is delivered in
465 * new kernel the moment interrupts are enabled.
467 * Interrupts are enabled early and LAPIC is setup much later, hence
468 * its possible that when we get here evt->event_handler is NULL.
469 * Check for event_handler being NULL and discard the interrupt as
472 if (!evt->event_handler) {
474 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
476 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
481 * the NMI deadlock-detector uses this.
483 add_pda(apic_timer_irqs, 1);
485 evt->event_handler(evt);
489 * Local APIC timer interrupt. This is the most natural way for doing
490 * local interrupts, but local timer interrupts can be emulated by
491 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
493 * [ if a single-CPU system runs an SMP kernel then we call the local
494 * interrupt as well. Thus we cannot inline the local irq ... ]
496 void smp_apic_timer_interrupt(struct pt_regs *regs)
498 struct pt_regs *old_regs = set_irq_regs(regs);
501 * NOTE! We'd better ACK the irq immediately,
502 * because timer handling can be slow.
506 * update_process_times() expects us to have done irq_enter().
507 * Besides, if we don't timer interrupts ignore the global
508 * interrupt lock, which is the WrongThing (tm) to do.
512 local_apic_timer_interrupt();
514 set_irq_regs(old_regs);
517 int setup_profiling_timer(unsigned int multiplier)
524 * Local APIC start and shutdown
528 * clear_local_APIC - shutdown the local APIC
530 * This is called, when a CPU is disabled and before rebooting, so the state of
531 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
532 * leftovers during boot.
534 void clear_local_APIC(void)
536 int maxlvt = lapic_get_maxlvt();
539 /* APIC hasn't been mapped yet */
543 maxlvt = lapic_get_maxlvt();
545 * Masking an LVT entry can trigger a local APIC error
546 * if the vector is zero. Mask LVTERR first to prevent this.
549 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
550 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
553 * Careful: we have to set masks only first to deassert
554 * any level-triggered sources.
556 v = apic_read(APIC_LVTT);
557 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
558 v = apic_read(APIC_LVT0);
559 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
560 v = apic_read(APIC_LVT1);
561 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
563 v = apic_read(APIC_LVTPC);
564 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
568 * Clean APIC state for other OSs:
570 apic_write(APIC_LVTT, APIC_LVT_MASKED);
571 apic_write(APIC_LVT0, APIC_LVT_MASKED);
572 apic_write(APIC_LVT1, APIC_LVT_MASKED);
574 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
576 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
577 apic_write(APIC_ESR, 0);
582 * disable_local_APIC - clear and disable the local APIC
584 void disable_local_APIC(void)
591 * Disable APIC (implies clearing of registers
594 value = apic_read(APIC_SPIV);
595 value &= ~APIC_SPIV_APIC_ENABLED;
596 apic_write(APIC_SPIV, value);
599 void lapic_shutdown(void)
606 local_irq_save(flags);
608 disable_local_APIC();
610 local_irq_restore(flags);
614 * This is to verify that we're looking at a real local APIC.
615 * Check these against your board if the CPUs aren't getting
616 * started for no apparent reason.
618 int __init verify_local_APIC(void)
620 unsigned int reg0, reg1;
623 * The version register is read-only in a real APIC.
625 reg0 = apic_read(APIC_LVR);
626 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
627 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
628 reg1 = apic_read(APIC_LVR);
629 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
632 * The two version reads above should print the same
633 * numbers. If the second one is different, then we
634 * poke at a non-APIC.
640 * Check if the version looks reasonably.
642 reg1 = GET_APIC_VERSION(reg0);
643 if (reg1 == 0x00 || reg1 == 0xff)
645 reg1 = lapic_get_maxlvt();
646 if (reg1 < 0x02 || reg1 == 0xff)
650 * The ID register is read/write in a real APIC.
652 reg0 = apic_read(APIC_ID);
653 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
654 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
655 reg1 = apic_read(APIC_ID);
656 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
657 apic_write(APIC_ID, reg0);
658 if (reg1 != (reg0 ^ APIC_ID_MASK))
662 * The next two are just to see if we have sane values.
663 * They're only really relevant if we're in Virtual Wire
664 * compatibility mode, but most boxes are anymore.
666 reg0 = apic_read(APIC_LVT0);
667 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
668 reg1 = apic_read(APIC_LVT1);
669 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
675 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
677 void __init sync_Arb_IDs(void)
679 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
686 apic_wait_icr_idle();
688 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
689 apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
694 * An initial setup of the virtual wire mode.
696 void __init init_bsp_APIC(void)
701 * Don't do the setup now if we have a SMP BIOS as the
702 * through-I/O-APIC virtual wire mode might be active.
704 if (smp_found_config || !cpu_has_apic)
707 value = apic_read(APIC_LVR);
710 * Do not trust the local APIC being empty at bootup.
717 value = apic_read(APIC_SPIV);
718 value &= ~APIC_VECTOR_MASK;
719 value |= APIC_SPIV_APIC_ENABLED;
720 value |= APIC_SPIV_FOCUS_DISABLED;
721 value |= SPURIOUS_APIC_VECTOR;
722 apic_write(APIC_SPIV, value);
725 * Set up the virtual wire mode.
727 apic_write(APIC_LVT0, APIC_DM_EXTINT);
729 apic_write(APIC_LVT1, value);
733 * setup_local_APIC - setup the local APIC
735 void __cpuinit setup_local_APIC(void)
740 value = apic_read(APIC_LVR);
742 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
745 * Double-check whether this APIC is really registered.
746 * This is meaningless in clustered apic mode, so we skip it.
748 if (!apic_id_registered())
752 * Intel recommends to set DFR, LDR and TPR before enabling
753 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
754 * document number 292116). So here it goes...
759 * Set Task Priority to 'accept all'. We never change this
762 value = apic_read(APIC_TASKPRI);
763 value &= ~APIC_TPRI_MASK;
764 apic_write(APIC_TASKPRI, value);
767 * After a crash, we no longer service the interrupts and a pending
768 * interrupt from previous kernel might still have ISR bit set.
770 * Most probably by now CPU has serviced that pending interrupt and
771 * it might not have done the ack_APIC_irq() because it thought,
772 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
773 * does not clear the ISR bit and cpu thinks it has already serivced
774 * the interrupt. Hence a vector might get locked. It was noticed
775 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
777 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
778 value = apic_read(APIC_ISR + i*0x10);
779 for (j = 31; j >= 0; j--) {
786 * Now that we are all set up, enable the APIC
788 value = apic_read(APIC_SPIV);
789 value &= ~APIC_VECTOR_MASK;
793 value |= APIC_SPIV_APIC_ENABLED;
795 /* We always use processor focus */
798 * Set spurious IRQ vector
800 value |= SPURIOUS_APIC_VECTOR;
801 apic_write(APIC_SPIV, value);
806 * set up through-local-APIC on the BP's LINT0. This is not
807 * strictly necessary in pure symmetric-IO mode, but sometimes
808 * we delegate interrupts to the 8259A.
811 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
813 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
814 if (!smp_processor_id() && !value) {
815 value = APIC_DM_EXTINT;
816 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
819 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
820 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
823 apic_write(APIC_LVT0, value);
826 * only the BP should see the LINT1 NMI signal, obviously.
828 if (!smp_processor_id())
831 value = APIC_DM_NMI | APIC_LVT_MASKED;
832 apic_write(APIC_LVT1, value);
835 void __cpuinit lapic_setup_esr(void)
837 unsigned maxlvt = lapic_get_maxlvt();
839 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR);
841 * spec says clear errors after enabling vector.
844 apic_write(APIC_ESR, 0);
847 void __cpuinit end_local_APIC_setup(void)
850 nmi_watchdog_default();
851 setup_apic_nmi_watchdog(NULL);
856 * Detect and enable local APICs on non-SMP boards.
857 * Original code written by Keir Fraser.
858 * On AMD64 we trust the BIOS - if it says no APIC it is likely
859 * not correctly set up (usually the APIC timer won't work etc.)
861 static int __init detect_init_APIC(void)
864 printk(KERN_INFO "No local APIC present\n");
868 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
869 boot_cpu_physical_apicid = 0;
873 void __init early_init_lapic_mapping(void)
875 unsigned long apic_phys;
878 * If no local APIC can be found then go out
879 * : it means there is no mpatable and MADT
881 if (!smp_found_config)
884 apic_phys = mp_lapic_addr;
886 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
887 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
888 APIC_BASE, apic_phys);
891 * Fetch the APIC ID of the BSP in case we have a
892 * default configuration (or the MP table is broken).
894 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
898 * init_apic_mappings - initialize APIC mappings
900 void __init init_apic_mappings(void)
903 * If no local APIC can be found then set up a fake all
904 * zeroes page to simulate the local APIC and another
905 * one for the IO-APIC.
907 if (!smp_found_config && detect_init_APIC()) {
908 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
909 apic_phys = __pa(apic_phys);
911 apic_phys = mp_lapic_addr;
913 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
914 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
915 APIC_BASE, apic_phys);
918 * Fetch the APIC ID of the BSP in case we have a
919 * default configuration (or the MP table is broken).
921 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
925 * This initializes the IO-APIC and APIC hardware if this is
928 int __init APIC_init_uniprocessor(void)
931 printk(KERN_INFO "Apic disabled\n");
936 printk(KERN_INFO "Apic disabled by BIOS\n");
942 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
943 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
948 * Now enable IO-APICs, actually call clear_IO_APIC
949 * We need clear_IO_APIC before enabling vector on BP
951 if (!skip_ioapic_setup && nr_ioapics)
954 end_local_APIC_setup();
956 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
960 setup_boot_APIC_clock();
961 check_nmi_watchdog();
966 * Local APIC interrupts
970 * This interrupt should _never_ happen with our APIC/SMP architecture
972 asmlinkage void smp_spurious_interrupt(void)
978 * Check if this really is a spurious interrupt and ACK it
979 * if it is a vectored one. Just in case...
980 * Spurious interrupts should not be ACKed.
982 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
983 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
986 add_pda(irq_spurious_count, 1);
991 * This interrupt should never happen with our APIC/SMP architecture
993 asmlinkage void smp_error_interrupt(void)
999 /* First tickle the hardware, only then report what went on. -- REW */
1000 v = apic_read(APIC_ESR);
1001 apic_write(APIC_ESR, 0);
1002 v1 = apic_read(APIC_ESR);
1004 atomic_inc(&irq_err_count);
1006 /* Here is what the APIC error bits mean:
1009 2: Send accept error
1010 3: Receive accept error
1012 5: Send illegal vector
1013 6: Received illegal vector
1014 7: Illegal register address
1016 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1017 smp_processor_id(), v , v1);
1021 void disconnect_bsp_APIC(int virt_wire_setup)
1023 /* Go back to Virtual Wire compatibility mode */
1024 unsigned long value;
1026 /* For the spurious interrupt use vector F, and enable it */
1027 value = apic_read(APIC_SPIV);
1028 value &= ~APIC_VECTOR_MASK;
1029 value |= APIC_SPIV_APIC_ENABLED;
1031 apic_write(APIC_SPIV, value);
1033 if (!virt_wire_setup) {
1035 * For LVT0 make it edge triggered, active high,
1036 * external and enabled
1038 value = apic_read(APIC_LVT0);
1039 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1040 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1041 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1042 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1043 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1044 apic_write(APIC_LVT0, value);
1047 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1050 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1051 value = apic_read(APIC_LVT1);
1052 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1053 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1054 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1055 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1056 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1057 apic_write(APIC_LVT1, value);
1066 /* 'active' is true if the local APIC was enabled by us and
1067 not the BIOS; this signifies that we are also responsible
1068 for disabling it before entering apm/acpi suspend */
1070 /* r/w apic fields */
1071 unsigned int apic_id;
1072 unsigned int apic_taskpri;
1073 unsigned int apic_ldr;
1074 unsigned int apic_dfr;
1075 unsigned int apic_spiv;
1076 unsigned int apic_lvtt;
1077 unsigned int apic_lvtpc;
1078 unsigned int apic_lvt0;
1079 unsigned int apic_lvt1;
1080 unsigned int apic_lvterr;
1081 unsigned int apic_tmict;
1082 unsigned int apic_tdcr;
1083 unsigned int apic_thmr;
1086 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1088 unsigned long flags;
1091 if (!apic_pm_state.active)
1094 maxlvt = lapic_get_maxlvt();
1096 apic_pm_state.apic_id = apic_read(APIC_ID);
1097 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1098 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1099 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1100 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1101 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1103 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1104 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1105 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1106 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1107 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1108 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1109 #ifdef CONFIG_X86_MCE_INTEL
1111 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1113 local_irq_save(flags);
1114 disable_local_APIC();
1115 local_irq_restore(flags);
1119 static int lapic_resume(struct sys_device *dev)
1122 unsigned long flags;
1125 if (!apic_pm_state.active)
1128 maxlvt = lapic_get_maxlvt();
1130 local_irq_save(flags);
1131 rdmsr(MSR_IA32_APICBASE, l, h);
1132 l &= ~MSR_IA32_APICBASE_BASE;
1133 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1134 wrmsr(MSR_IA32_APICBASE, l, h);
1135 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1136 apic_write(APIC_ID, apic_pm_state.apic_id);
1137 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1138 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1139 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1140 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1141 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1142 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1143 #ifdef CONFIG_X86_MCE_INTEL
1145 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1148 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1149 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1150 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1151 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1152 apic_write(APIC_ESR, 0);
1153 apic_read(APIC_ESR);
1154 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1155 apic_write(APIC_ESR, 0);
1156 apic_read(APIC_ESR);
1157 local_irq_restore(flags);
1161 static struct sysdev_class lapic_sysclass = {
1163 .resume = lapic_resume,
1164 .suspend = lapic_suspend,
1167 static struct sys_device device_lapic = {
1169 .cls = &lapic_sysclass,
1172 static void __cpuinit apic_pm_activate(void)
1174 apic_pm_state.active = 1;
1177 static int __init init_lapic_sysfs(void)
1183 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1185 error = sysdev_class_register(&lapic_sysclass);
1187 error = sysdev_register(&device_lapic);
1190 device_initcall(init_lapic_sysfs);
1192 #else /* CONFIG_PM */
1194 static void apic_pm_activate(void) { }
1196 #endif /* CONFIG_PM */
1199 * apic_is_clustered_box() -- Check if we can expect good TSC
1201 * Thus far, the major user of this is IBM's Summit2 series:
1203 * Clustered boxes may have unsynced TSC problems if they are
1204 * multi-chassis. Use available data to take a good guess.
1205 * If in doubt, go HPET.
1207 __cpuinit int apic_is_clustered_box(void)
1209 int i, clusters, zeros;
1211 u16 *bios_cpu_apicid;
1212 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
1215 * there is not this kind of box with AMD CPU yet.
1216 * Some AMD box with quadcore cpu and 8 sockets apicid
1217 * will be [4, 0x23] or [8, 0x27] could be thought to
1218 * vsmp box still need checking...
1220 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
1223 bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
1224 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
1226 for (i = 0; i < NR_CPUS; i++) {
1227 /* are we being called early in kernel startup? */
1228 if (bios_cpu_apicid) {
1229 id = bios_cpu_apicid[i];
1231 else if (i < nr_cpu_ids) {
1233 id = per_cpu(x86_bios_cpu_apicid, i);
1240 if (id != BAD_APICID)
1241 __set_bit(APIC_CLUSTERID(id), clustermap);
1244 /* Problem: Partially populated chassis may not have CPUs in some of
1245 * the APIC clusters they have been allocated. Only present CPUs have
1246 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1247 * Since clusters are allocated sequentially, count zeros only if
1248 * they are bounded by ones.
1252 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
1253 if (test_bit(i, clustermap)) {
1254 clusters += 1 + zeros;
1260 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1261 * not guaranteed to be synced between boards
1263 if (is_vsmp_box() && clusters > 1)
1267 * If clusters > 2, then should be multi-chassis.
1268 * May have to revisit this when multi-core + hyperthreaded CPUs come
1269 * out, but AFAIK this will work even for them.
1271 return (clusters > 2);
1275 * APIC command line parameters
1277 static int __init apic_set_verbosity(char *str)
1280 skip_ioapic_setup = 0;
1284 if (strcmp("debug", str) == 0)
1285 apic_verbosity = APIC_DEBUG;
1286 else if (strcmp("verbose", str) == 0)
1287 apic_verbosity = APIC_VERBOSE;
1289 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
1290 " use apic=verbose or apic=debug\n", str);
1296 early_param("apic", apic_set_verbosity);
1298 static __init int setup_disableapic(char *str)
1301 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1304 early_param("disableapic", setup_disableapic);
1306 /* same as disableapic, for compatibility */
1307 static __init int setup_nolapic(char *str)
1309 return setup_disableapic(str);
1311 early_param("nolapic", setup_nolapic);
1313 static int __init parse_lapic_timer_c2_ok(char *arg)
1315 local_apic_timer_c2_ok = 1;
1318 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1320 static __init int setup_noapictimer(char *str)
1322 if (str[0] != ' ' && str[0] != 0)
1324 disable_apic_timer = 1;
1327 __setup("noapictimer", setup_noapictimer);
1329 static __init int setup_apicpmtimer(char *s)
1331 apic_calibrate_pmtmr = 1;
1335 __setup("apicpmtimer", setup_apicpmtimer);
1337 static int __init lapic_insert_resource(void)
1342 /* Put local APIC into the resource map. */
1343 lapic_resource.start = apic_phys;
1344 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
1345 insert_resource(&iomem_resource, &lapic_resource);
1351 * need call insert after e820_reserve_resources()
1352 * that is using request_resource
1354 late_initcall(lapic_insert_resource);