2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/cpu.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmi.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
51 #if (SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F
52 # error SPURIOUS_APIC_VECTOR definition error
56 * Knob to control our willingness to enable the local APIC.
58 * -1=force-disable, +1=force-enable
60 static int enable_local_apic __initdata = 0;
62 /* Local APIC timer verification ok */
63 static int local_apic_timer_verify_ok;
64 /* Disable local APIC timer from the kernel commandline or via dmi quirk
65 or using CPU MSR check */
66 int local_apic_timer_disabled;
67 /* Local APIC timer works in C2 */
68 int local_apic_timer_c2_ok;
69 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
72 * Debug level, exported for io_apic.c
76 static unsigned int calibration_result;
78 static int lapic_next_event(unsigned long delta,
79 struct clock_event_device *evt);
80 static void lapic_timer_setup(enum clock_event_mode mode,
81 struct clock_event_device *evt);
82 static void lapic_timer_broadcast(cpumask_t mask);
83 static void apic_pm_activate(void);
86 * The local apic timer can be used for any function which is CPU local.
88 static struct clock_event_device lapic_clockevent = {
90 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
91 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
93 .set_mode = lapic_timer_setup,
94 .set_next_event = lapic_next_event,
95 .broadcast = lapic_timer_broadcast,
99 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
101 /* Local APIC was disabled by the BIOS and enabled by the kernel */
102 static int enabled_via_apicbase;
105 * Get the LAPIC version
107 static inline int lapic_get_version(void)
109 return GET_APIC_VERSION(apic_read(APIC_LVR));
113 * Check, if the APIC is integrated or a seperate chip
115 static inline int lapic_is_integrated(void)
117 return APIC_INTEGRATED(lapic_get_version());
121 * Check, whether this is a modern or a first generation APIC
123 static int modern_apic(void)
125 /* AMD systems use old APIC versions, so check the CPU */
126 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
127 boot_cpu_data.x86 >= 0xf)
129 return lapic_get_version() >= 0x14;
132 void apic_wait_icr_idle(void)
134 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
138 u32 safe_apic_wait_icr_idle(void)
145 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
149 } while (timeout++ < 1000);
155 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
157 void enable_NMI_through_LVT0 (void * dummy)
159 unsigned int v = APIC_DM_NMI;
161 /* Level triggered for 82489DX */
162 if (!lapic_is_integrated())
163 v |= APIC_LVT_LEVEL_TRIGGER;
164 apic_write_around(APIC_LVT0, v);
168 * get_physical_broadcast - Get number of physical broadcast IDs
170 int get_physical_broadcast(void)
172 return modern_apic() ? 0xff : 0xf;
176 * lapic_get_maxlvt - get the maximum number of local vector table entries
178 int lapic_get_maxlvt(void)
180 unsigned int v = apic_read(APIC_LVR);
182 /* 82489DXs do not report # of LVT entries. */
183 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
190 /* Clock divisor is set to 16 */
191 #define APIC_DIVISOR 16
194 * This function sets up the local APIC timer, with a timeout of
195 * 'clocks' APIC bus clock. During calibration we actually call
196 * this function twice on the boot CPU, once with a bogus timeout
197 * value, second time for real. The other (noncalibrating) CPUs
198 * call this function only once, with the real, calibrated value.
200 * We do reads before writes even if unnecessary, to get around the
201 * P5 APIC double write bug.
203 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
205 unsigned int lvtt_value, tmp_value;
207 lvtt_value = LOCAL_TIMER_VECTOR;
209 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
210 if (!lapic_is_integrated())
211 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
214 lvtt_value |= APIC_LVT_MASKED;
216 apic_write_around(APIC_LVTT, lvtt_value);
221 tmp_value = apic_read(APIC_TDCR);
222 apic_write_around(APIC_TDCR, (tmp_value
223 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
227 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
231 * Program the next event, relative to now
233 static int lapic_next_event(unsigned long delta,
234 struct clock_event_device *evt)
236 apic_write_around(APIC_TMICT, delta);
241 * Setup the lapic timer in periodic or oneshot mode
243 static void lapic_timer_setup(enum clock_event_mode mode,
244 struct clock_event_device *evt)
249 /* Lapic used for broadcast ? */
250 if (!local_apic_timer_verify_ok)
253 local_irq_save(flags);
256 case CLOCK_EVT_MODE_PERIODIC:
257 case CLOCK_EVT_MODE_ONESHOT:
258 __setup_APIC_LVTT(calibration_result,
259 mode != CLOCK_EVT_MODE_PERIODIC, 1);
261 case CLOCK_EVT_MODE_UNUSED:
262 case CLOCK_EVT_MODE_SHUTDOWN:
263 v = apic_read(APIC_LVTT);
264 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
265 apic_write_around(APIC_LVTT, v);
267 case CLOCK_EVT_MODE_RESUME:
268 /* Nothing to do here */
272 local_irq_restore(flags);
276 * Local APIC timer broadcast function
278 static void lapic_timer_broadcast(cpumask_t mask)
281 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
286 * Setup the local APIC timer for this CPU. Copy the initilized values
287 * of the boot CPU and register the clock event in the framework.
289 static void __devinit setup_APIC_timer(void)
291 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
293 memcpy(levt, &lapic_clockevent, sizeof(*levt));
294 levt->cpumask = cpumask_of_cpu(smp_processor_id());
296 clockevents_register_device(levt);
300 * In this functions we calibrate APIC bus clocks to the external timer.
302 * We want to do the calibration only once since we want to have local timer
303 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
306 * This was previously done by reading the PIT/HPET and waiting for a wrap
307 * around to find out, that a tick has elapsed. I have a box, where the PIT
308 * readout is broken, so it never gets out of the wait loop again. This was
309 * also reported by others.
311 * Monitoring the jiffies value is inaccurate and the clockevents
312 * infrastructure allows us to do a simple substitution of the interrupt
315 * The calibration routine also uses the pm_timer when possible, as the PIT
316 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
317 * back to normal later in the boot process).
320 #define LAPIC_CAL_LOOPS (HZ/10)
322 static __initdata int lapic_cal_loops = -1;
323 static __initdata long lapic_cal_t1, lapic_cal_t2;
324 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
325 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
326 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
329 * Temporary interrupt handler.
331 static void __init lapic_cal_handler(struct clock_event_device *dev)
333 unsigned long long tsc = 0;
334 long tapic = apic_read(APIC_TMCCT);
335 unsigned long pm = acpi_pm_read_early();
340 switch (lapic_cal_loops++) {
342 lapic_cal_t1 = tapic;
343 lapic_cal_tsc1 = tsc;
345 lapic_cal_j1 = jiffies;
348 case LAPIC_CAL_LOOPS:
349 lapic_cal_t2 = tapic;
350 lapic_cal_tsc2 = tsc;
351 if (pm < lapic_cal_pm1)
352 pm += ACPI_PM_OVRRUN;
354 lapic_cal_j2 = jiffies;
360 * Setup the boot APIC
362 * Calibrate and verify the result.
364 void __init setup_boot_APIC_clock(void)
366 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
367 const long pm_100ms = PMTMR_TICKS_PER_SEC/10;
368 const long pm_thresh = pm_100ms/100;
369 void (*real_handler)(struct clock_event_device *dev);
370 unsigned long deltaj;
372 int pm_referenced = 0;
375 * The local apic timer can be disabled via the kernel
376 * commandline or from the CPU detection code. Register the lapic
377 * timer as a dummy clock event source on SMP systems, so the
378 * broadcast mechanism is used. On UP systems simply ignore it.
380 if (local_apic_timer_disabled) {
381 /* No broadcast on UP ! */
382 if (num_possible_cpus() > 1)
387 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
388 "calibrating APIC timer ...\n");
392 /* Replace the global interrupt handler */
393 real_handler = global_clock_event->event_handler;
394 global_clock_event->event_handler = lapic_cal_handler;
397 * Setup the APIC counter to 1e9. There is no way the lapic
398 * can underflow in the 100ms detection time frame
400 __setup_APIC_LVTT(1000000000, 0, 0);
402 /* Let the interrupts run */
405 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
410 /* Restore the real event handler */
411 global_clock_event->event_handler = real_handler;
413 /* Build delta t1-t2 as apic timer counts down */
414 delta = lapic_cal_t1 - lapic_cal_t2;
415 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
417 /* Check, if the PM timer is available */
418 deltapm = lapic_cal_pm2 - lapic_cal_pm1;
419 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
425 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
427 if (deltapm > (pm_100ms - pm_thresh) &&
428 deltapm < (pm_100ms + pm_thresh)) {
429 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
431 res = (((u64) deltapm) * mult) >> 22;
432 do_div(res, 1000000);
433 printk(KERN_WARNING "APIC calibration not consistent "
434 "with PM Timer: %ldms instead of 100ms\n",
436 /* Correct the lapic counter value */
437 res = (((u64) delta ) * pm_100ms);
438 do_div(res, deltapm);
439 printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
440 "%lu (%ld)\n", (unsigned long) res, delta);
446 /* Calculate the scaled math multiplication factor */
447 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 32);
448 lapic_clockevent.max_delta_ns =
449 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
450 lapic_clockevent.min_delta_ns =
451 clockevent_delta2ns(0xF, &lapic_clockevent);
453 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
455 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
456 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
457 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
461 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
462 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
464 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
465 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
468 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
470 calibration_result / (1000000 / HZ),
471 calibration_result % (1000000 / HZ));
473 local_apic_timer_verify_ok = 1;
475 /* We trust the pm timer based calibration */
476 if (!pm_referenced) {
477 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
480 * Setup the apic timer manually
482 levt->event_handler = lapic_cal_handler;
483 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
484 lapic_cal_loops = -1;
486 /* Let the interrupts run */
489 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
494 /* Stop the lapic timer */
495 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
500 deltaj = lapic_cal_j2 - lapic_cal_j1;
501 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
503 /* Check, if the jiffies result is consistent */
504 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
505 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
507 local_apic_timer_verify_ok = 0;
511 if (!local_apic_timer_verify_ok) {
513 "APIC timer disabled due to verification failure.\n");
514 /* No broadcast on UP ! */
515 if (num_possible_cpus() == 1)
519 * If nmi_watchdog is set to IO_APIC, we need the
520 * PIT/HPET going. Otherwise register lapic as a dummy
523 if (nmi_watchdog != NMI_IO_APIC)
524 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
526 printk(KERN_WARNING "APIC timer registered as dummy,"
527 " due to nmi_watchdog=1!\n");
530 /* Setup the lapic or request the broadcast */
534 void __devinit setup_secondary_APIC_clock(void)
540 * The guts of the apic timer interrupt
542 static void local_apic_timer_interrupt(void)
544 int cpu = smp_processor_id();
545 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
548 * Normally we should not be here till LAPIC has been initialized but
549 * in some cases like kdump, its possible that there is a pending LAPIC
550 * timer interrupt from previous kernel's context and is delivered in
551 * new kernel the moment interrupts are enabled.
553 * Interrupts are enabled early and LAPIC is setup much later, hence
554 * its possible that when we get here evt->event_handler is NULL.
555 * Check for event_handler being NULL and discard the interrupt as
558 if (!evt->event_handler) {
560 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
562 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
567 * the NMI deadlock-detector uses this.
569 per_cpu(irq_stat, cpu).apic_timer_irqs++;
571 evt->event_handler(evt);
575 * Local APIC timer interrupt. This is the most natural way for doing
576 * local interrupts, but local timer interrupts can be emulated by
577 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
579 * [ if a single-CPU system runs an SMP kernel then we call the local
580 * interrupt as well. Thus we cannot inline the local irq ... ]
583 void fastcall smp_apic_timer_interrupt(struct pt_regs *regs)
585 struct pt_regs *old_regs = set_irq_regs(regs);
588 * NOTE! We'd better ACK the irq immediately,
589 * because timer handling can be slow.
593 * update_process_times() expects us to have done irq_enter().
594 * Besides, if we don't timer interrupts ignore the global
595 * interrupt lock, which is the WrongThing (tm) to do.
598 local_apic_timer_interrupt();
601 set_irq_regs(old_regs);
604 int setup_profiling_timer(unsigned int multiplier)
610 * Local APIC start and shutdown
614 * clear_local_APIC - shutdown the local APIC
616 * This is called, when a CPU is disabled and before rebooting, so the state of
617 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
618 * leftovers during boot.
620 void clear_local_APIC(void)
622 int maxlvt = lapic_get_maxlvt();
626 * Masking an LVT entry can trigger a local APIC error
627 * if the vector is zero. Mask LVTERR first to prevent this.
630 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
631 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
634 * Careful: we have to set masks only first to deassert
635 * any level-triggered sources.
637 v = apic_read(APIC_LVTT);
638 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
639 v = apic_read(APIC_LVT0);
640 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
641 v = apic_read(APIC_LVT1);
642 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
644 v = apic_read(APIC_LVTPC);
645 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
648 /* lets not touch this if we didn't frob it */
649 #ifdef CONFIG_X86_MCE_P4THERMAL
651 v = apic_read(APIC_LVTTHMR);
652 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
656 * Clean APIC state for other OSs:
658 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
659 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
660 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
662 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
664 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
666 #ifdef CONFIG_X86_MCE_P4THERMAL
668 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
670 /* Integrated APIC (!82489DX) ? */
671 if (lapic_is_integrated()) {
673 /* Clear ESR due to Pentium errata 3AP and 11AP */
674 apic_write(APIC_ESR, 0);
680 * disable_local_APIC - clear and disable the local APIC
682 void disable_local_APIC(void)
689 * Disable APIC (implies clearing of registers
692 value = apic_read(APIC_SPIV);
693 value &= ~APIC_SPIV_APIC_ENABLED;
694 apic_write_around(APIC_SPIV, value);
697 * When LAPIC was disabled by the BIOS and enabled by the kernel,
698 * restore the disabled state.
700 if (enabled_via_apicbase) {
703 rdmsr(MSR_IA32_APICBASE, l, h);
704 l &= ~MSR_IA32_APICBASE_ENABLE;
705 wrmsr(MSR_IA32_APICBASE, l, h);
710 * If Linux enabled the LAPIC against the BIOS default disable it down before
711 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
712 * not power-off. Additionally clear all LVT entries before disable_local_APIC
713 * for the case where Linux didn't enable the LAPIC.
715 void lapic_shutdown(void)
722 local_irq_save(flags);
725 if (enabled_via_apicbase)
726 disable_local_APIC();
728 local_irq_restore(flags);
732 * This is to verify that we're looking at a real local APIC.
733 * Check these against your board if the CPUs aren't getting
734 * started for no apparent reason.
736 int __init verify_local_APIC(void)
738 unsigned int reg0, reg1;
741 * The version register is read-only in a real APIC.
743 reg0 = apic_read(APIC_LVR);
744 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
745 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
746 reg1 = apic_read(APIC_LVR);
747 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
750 * The two version reads above should print the same
751 * numbers. If the second one is different, then we
752 * poke at a non-APIC.
758 * Check if the version looks reasonably.
760 reg1 = GET_APIC_VERSION(reg0);
761 if (reg1 == 0x00 || reg1 == 0xff)
763 reg1 = lapic_get_maxlvt();
764 if (reg1 < 0x02 || reg1 == 0xff)
768 * The ID register is read/write in a real APIC.
770 reg0 = apic_read(APIC_ID);
771 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
774 * The next two are just to see if we have sane values.
775 * They're only really relevant if we're in Virtual Wire
776 * compatibility mode, but most boxes are anymore.
778 reg0 = apic_read(APIC_LVT0);
779 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
780 reg1 = apic_read(APIC_LVT1);
781 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
787 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
789 void __init sync_Arb_IDs(void)
792 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
795 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
800 apic_wait_icr_idle();
802 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
803 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
808 * An initial setup of the virtual wire mode.
810 void __init init_bsp_APIC(void)
815 * Don't do the setup now if we have a SMP BIOS as the
816 * through-I/O-APIC virtual wire mode might be active.
818 if (smp_found_config || !cpu_has_apic)
822 * Do not trust the local APIC being empty at bootup.
829 value = apic_read(APIC_SPIV);
830 value &= ~APIC_VECTOR_MASK;
831 value |= APIC_SPIV_APIC_ENABLED;
833 /* This bit is reserved on P4/Xeon and should be cleared */
834 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
835 (boot_cpu_data.x86 == 15))
836 value &= ~APIC_SPIV_FOCUS_DISABLED;
838 value |= APIC_SPIV_FOCUS_DISABLED;
839 value |= SPURIOUS_APIC_VECTOR;
840 apic_write_around(APIC_SPIV, value);
843 * Set up the virtual wire mode.
845 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
847 if (!lapic_is_integrated()) /* 82489DX */
848 value |= APIC_LVT_LEVEL_TRIGGER;
849 apic_write_around(APIC_LVT1, value);
853 * setup_local_APIC - setup the local APIC
855 void __cpuinit setup_local_APIC(void)
857 unsigned long oldvalue, value, maxlvt, integrated;
860 /* Pound the ESR really hard over the head with a big hammer - mbligh */
862 apic_write(APIC_ESR, 0);
863 apic_write(APIC_ESR, 0);
864 apic_write(APIC_ESR, 0);
865 apic_write(APIC_ESR, 0);
868 integrated = lapic_is_integrated();
871 * Double-check whether this APIC is really registered.
873 if (!apic_id_registered())
877 * Intel recommends to set DFR, LDR and TPR before enabling
878 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
879 * document number 292116). So here it goes...
884 * Set Task Priority to 'accept all'. We never change this
887 value = apic_read(APIC_TASKPRI);
888 value &= ~APIC_TPRI_MASK;
889 apic_write_around(APIC_TASKPRI, value);
892 * After a crash, we no longer service the interrupts and a pending
893 * interrupt from previous kernel might still have ISR bit set.
895 * Most probably by now CPU has serviced that pending interrupt and
896 * it might not have done the ack_APIC_irq() because it thought,
897 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
898 * does not clear the ISR bit and cpu thinks it has already serivced
899 * the interrupt. Hence a vector might get locked. It was noticed
900 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
902 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
903 value = apic_read(APIC_ISR + i*0x10);
904 for (j = 31; j >= 0; j--) {
911 * Now that we are all set up, enable the APIC
913 value = apic_read(APIC_SPIV);
914 value &= ~APIC_VECTOR_MASK;
918 value |= APIC_SPIV_APIC_ENABLED;
921 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
922 * certain networking cards. If high frequency interrupts are
923 * happening on a particular IOAPIC pin, plus the IOAPIC routing
924 * entry is masked/unmasked at a high rate as well then sooner or
925 * later IOAPIC line gets 'stuck', no more interrupts are received
926 * from the device. If focus CPU is disabled then the hang goes
929 * [ This bug can be reproduced easily with a level-triggered
930 * PCI Ne2000 networking cards and PII/PIII processors, dual
934 * Actually disabling the focus CPU check just makes the hang less
935 * frequent as it makes the interrupt distributon model be more
936 * like LRU than MRU (the short-term load is more even across CPUs).
937 * See also the comment in end_level_ioapic_irq(). --macro
940 /* Enable focus processor (bit==0) */
941 value &= ~APIC_SPIV_FOCUS_DISABLED;
944 * Set spurious IRQ vector
946 value |= SPURIOUS_APIC_VECTOR;
947 apic_write_around(APIC_SPIV, value);
952 * set up through-local-APIC on the BP's LINT0. This is not
953 * strictly necessary in pure symmetric-IO mode, but sometimes
954 * we delegate interrupts to the 8259A.
957 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
959 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
960 if (!smp_processor_id() && (pic_mode || !value)) {
961 value = APIC_DM_EXTINT;
962 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
965 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
966 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
969 apic_write_around(APIC_LVT0, value);
972 * only the BP should see the LINT1 NMI signal, obviously.
974 if (!smp_processor_id())
977 value = APIC_DM_NMI | APIC_LVT_MASKED;
978 if (!integrated) /* 82489DX */
979 value |= APIC_LVT_LEVEL_TRIGGER;
980 apic_write_around(APIC_LVT1, value);
982 if (integrated && !esr_disable) { /* !82489DX */
983 maxlvt = lapic_get_maxlvt();
984 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
985 apic_write(APIC_ESR, 0);
986 oldvalue = apic_read(APIC_ESR);
988 /* enables sending errors */
989 value = ERROR_APIC_VECTOR;
990 apic_write_around(APIC_LVTERR, value);
992 * spec says clear errors after enabling vector.
995 apic_write(APIC_ESR, 0);
996 value = apic_read(APIC_ESR);
997 if (value != oldvalue)
998 apic_printk(APIC_VERBOSE, "ESR value before enabling "
999 "vector: 0x%08lx after: 0x%08lx\n",
1004 * Something untraceable is creating bad interrupts on
1005 * secondary quads ... for the moment, just leave the
1006 * ESR disabled - we can't do anything useful with the
1007 * errors anyway - mbligh
1009 printk(KERN_INFO "Leaving ESR disabled.\n");
1011 printk(KERN_INFO "No ESR for 82489DX.\n");
1014 /* Disable the local apic timer */
1015 value = apic_read(APIC_LVTT);
1016 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1017 apic_write_around(APIC_LVTT, value);
1019 setup_apic_nmi_watchdog(NULL);
1024 * Detect and initialize APIC
1026 static int __init detect_init_APIC (void)
1030 /* Disabled by kernel option? */
1031 if (enable_local_apic < 0)
1034 switch (boot_cpu_data.x86_vendor) {
1035 case X86_VENDOR_AMD:
1036 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1037 (boot_cpu_data.x86 == 15))
1040 case X86_VENDOR_INTEL:
1041 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1042 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1049 if (!cpu_has_apic) {
1051 * Over-ride BIOS and try to enable the local APIC only if
1052 * "lapic" specified.
1054 if (enable_local_apic <= 0) {
1055 printk(KERN_INFO "Local APIC disabled by BIOS -- "
1056 "you can enable it with \"lapic\"\n");
1060 * Some BIOSes disable the local APIC in the APIC_BASE
1061 * MSR. This can only be done in software for Intel P6 or later
1062 * and AMD K7 (Model > 1) or later.
1064 rdmsr(MSR_IA32_APICBASE, l, h);
1065 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1067 "Local APIC disabled by BIOS -- reenabling.\n");
1068 l &= ~MSR_IA32_APICBASE_BASE;
1069 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1070 wrmsr(MSR_IA32_APICBASE, l, h);
1071 enabled_via_apicbase = 1;
1075 * The APIC feature bit should now be enabled
1078 features = cpuid_edx(1);
1079 if (!(features & (1 << X86_FEATURE_APIC))) {
1080 printk(KERN_WARNING "Could not enable APIC!\n");
1083 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1084 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1086 /* The BIOS may have set up the APIC at some other address */
1087 rdmsr(MSR_IA32_APICBASE, l, h);
1088 if (l & MSR_IA32_APICBASE_ENABLE)
1089 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1091 if (nmi_watchdog != NMI_NONE && nmi_watchdog != NMI_DISABLED)
1092 nmi_watchdog = NMI_LOCAL_APIC;
1094 printk(KERN_INFO "Found and enabled local APIC!\n");
1101 printk(KERN_INFO "No local APIC present or hardware disabled\n");
1106 * init_apic_mappings - initialize APIC mappings
1108 void __init init_apic_mappings(void)
1110 unsigned long apic_phys;
1113 * If no local APIC can be found then set up a fake all
1114 * zeroes page to simulate the local APIC and another
1115 * one for the IO-APIC.
1117 if (!smp_found_config && detect_init_APIC()) {
1118 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1119 apic_phys = __pa(apic_phys);
1121 apic_phys = mp_lapic_addr;
1123 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1124 printk(KERN_DEBUG "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
1128 * Fetch the APIC ID of the BSP in case we have a
1129 * default configuration (or the MP table is broken).
1131 if (boot_cpu_physical_apicid == -1U)
1132 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
1134 #ifdef CONFIG_X86_IO_APIC
1136 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
1139 for (i = 0; i < nr_ioapics; i++) {
1140 if (smp_found_config) {
1141 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
1144 "WARNING: bogus zero IO-APIC "
1145 "address found in MPTABLE, "
1146 "disabling IO/APIC support!\n");
1147 smp_found_config = 0;
1148 skip_ioapic_setup = 1;
1149 goto fake_ioapic_page;
1153 ioapic_phys = (unsigned long)
1154 alloc_bootmem_pages(PAGE_SIZE);
1155 ioapic_phys = __pa(ioapic_phys);
1157 set_fixmap_nocache(idx, ioapic_phys);
1158 printk(KERN_DEBUG "mapped IOAPIC to %08lx (%08lx)\n",
1159 __fix_to_virt(idx), ioapic_phys);
1167 * This initializes the IO-APIC and APIC hardware if this is
1170 int __init APIC_init_uniprocessor (void)
1172 if (enable_local_apic < 0)
1173 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1175 if (!smp_found_config && !cpu_has_apic)
1179 * Complain if the BIOS pretends there is one.
1181 if (!cpu_has_apic &&
1182 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1183 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1184 boot_cpu_physical_apicid);
1185 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1189 verify_local_APIC();
1194 * Hack: In case of kdump, after a crash, kernel might be booting
1195 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1196 * might be zero if read from MP tables. Get it from LAPIC.
1198 #ifdef CONFIG_CRASH_DUMP
1199 boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
1201 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
1205 #ifdef CONFIG_X86_IO_APIC
1206 if (smp_found_config)
1207 if (!skip_ioapic_setup && nr_ioapics)
1216 * Local APIC interrupts
1220 * This interrupt should _never_ happen with our APIC/SMP architecture
1222 void smp_spurious_interrupt(struct pt_regs *regs)
1228 * Check if this really is a spurious interrupt and ACK it
1229 * if it is a vectored one. Just in case...
1230 * Spurious interrupts should not be ACKed.
1232 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1233 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1236 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1237 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
1238 "should never happen.\n", smp_processor_id());
1239 __get_cpu_var(irq_stat).irq_spurious_count++;
1244 * This interrupt should never happen with our APIC/SMP architecture
1246 void smp_error_interrupt(struct pt_regs *regs)
1248 unsigned long v, v1;
1251 /* First tickle the hardware, only then report what went on. -- REW */
1252 v = apic_read(APIC_ESR);
1253 apic_write(APIC_ESR, 0);
1254 v1 = apic_read(APIC_ESR);
1256 atomic_inc(&irq_err_count);
1258 /* Here is what the APIC error bits mean:
1261 2: Send accept error
1262 3: Receive accept error
1264 5: Send illegal vector
1265 6: Received illegal vector
1266 7: Illegal register address
1268 printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
1269 smp_processor_id(), v , v1);
1274 * Initialize APIC interrupts
1276 void __init apic_intr_init(void)
1281 /* self generated IPI for local APIC timer */
1282 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
1284 /* IPI vectors for APIC spurious and error interrupts */
1285 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
1286 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
1288 /* thermal monitor LVT interrupt */
1289 #ifdef CONFIG_X86_MCE_P4THERMAL
1290 set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
1295 * connect_bsp_APIC - attach the APIC to the interrupt system
1297 void __init connect_bsp_APIC(void)
1301 * Do not trust the local APIC being empty at bootup.
1305 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1306 * local APIC to INT and NMI lines.
1308 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1309 "enabling APIC mode.\n");
1317 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1318 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1320 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1323 void disconnect_bsp_APIC(int virt_wire_setup)
1327 * Put the board back into PIC mode (has an effect only on
1328 * certain older boards). Note that APIC interrupts, including
1329 * IPIs, won't work beyond this point! The only exception are
1332 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1333 "entering PIC mode.\n");
1337 /* Go back to Virtual Wire compatibility mode */
1338 unsigned long value;
1340 /* For the spurious interrupt use vector F, and enable it */
1341 value = apic_read(APIC_SPIV);
1342 value &= ~APIC_VECTOR_MASK;
1343 value |= APIC_SPIV_APIC_ENABLED;
1345 apic_write_around(APIC_SPIV, value);
1347 if (!virt_wire_setup) {
1349 * For LVT0 make it edge triggered, active high,
1350 * external and enabled
1352 value = apic_read(APIC_LVT0);
1353 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1354 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1355 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
1356 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1357 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1358 apic_write_around(APIC_LVT0, value);
1361 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
1365 * For LVT1 make it edge triggered, active high, nmi and
1368 value = apic_read(APIC_LVT1);
1370 APIC_MODE_MASK | APIC_SEND_PENDING |
1371 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1372 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1373 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1374 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1375 apic_write_around(APIC_LVT1, value);
1386 /* r/w apic fields */
1387 unsigned int apic_id;
1388 unsigned int apic_taskpri;
1389 unsigned int apic_ldr;
1390 unsigned int apic_dfr;
1391 unsigned int apic_spiv;
1392 unsigned int apic_lvtt;
1393 unsigned int apic_lvtpc;
1394 unsigned int apic_lvt0;
1395 unsigned int apic_lvt1;
1396 unsigned int apic_lvterr;
1397 unsigned int apic_tmict;
1398 unsigned int apic_tdcr;
1399 unsigned int apic_thmr;
1402 static int lapic_suspend(struct sys_device *dev, pm_message_t state)
1404 unsigned long flags;
1407 if (!apic_pm_state.active)
1410 maxlvt = lapic_get_maxlvt();
1412 apic_pm_state.apic_id = apic_read(APIC_ID);
1413 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
1414 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
1415 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
1416 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
1417 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
1419 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
1420 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
1421 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
1422 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
1423 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
1424 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
1425 #ifdef CONFIG_X86_MCE_P4THERMAL
1427 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
1430 local_irq_save(flags);
1431 disable_local_APIC();
1432 local_irq_restore(flags);
1436 static int lapic_resume(struct sys_device *dev)
1439 unsigned long flags;
1442 if (!apic_pm_state.active)
1445 maxlvt = lapic_get_maxlvt();
1447 local_irq_save(flags);
1450 * Make sure the APICBASE points to the right address
1452 * FIXME! This will be wrong if we ever support suspend on
1453 * SMP! We'll need to do this as part of the CPU restore!
1455 rdmsr(MSR_IA32_APICBASE, l, h);
1456 l &= ~MSR_IA32_APICBASE_BASE;
1457 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
1458 wrmsr(MSR_IA32_APICBASE, l, h);
1460 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
1461 apic_write(APIC_ID, apic_pm_state.apic_id);
1462 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
1463 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
1464 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
1465 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
1466 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
1467 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
1468 #ifdef CONFIG_X86_MCE_P4THERMAL
1470 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
1473 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
1474 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
1475 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
1476 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
1477 apic_write(APIC_ESR, 0);
1478 apic_read(APIC_ESR);
1479 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
1480 apic_write(APIC_ESR, 0);
1481 apic_read(APIC_ESR);
1482 local_irq_restore(flags);
1487 * This device has no shutdown method - fully functioning local APICs
1488 * are needed on every CPU up until machine_halt/restart/poweroff.
1491 static struct sysdev_class lapic_sysclass = {
1493 .resume = lapic_resume,
1494 .suspend = lapic_suspend,
1497 static struct sys_device device_lapic = {
1499 .cls = &lapic_sysclass,
1502 static void __devinit apic_pm_activate(void)
1504 apic_pm_state.active = 1;
1507 static int __init init_lapic_sysfs(void)
1513 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1515 error = sysdev_class_register(&lapic_sysclass);
1517 error = sysdev_register(&device_lapic);
1520 device_initcall(init_lapic_sysfs);
1522 #else /* CONFIG_PM */
1524 static void apic_pm_activate(void) { }
1526 #endif /* CONFIG_PM */
1529 * APIC command line parameters
1531 static int __init parse_lapic(char *arg)
1533 enable_local_apic = 1;
1536 early_param("lapic", parse_lapic);
1538 static int __init parse_nolapic(char *arg)
1540 enable_local_apic = -1;
1541 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1544 early_param("nolapic", parse_nolapic);
1546 static int __init parse_disable_lapic_timer(char *arg)
1548 local_apic_timer_disabled = 1;
1551 early_param("nolapic_timer", parse_disable_lapic_timer);
1553 static int __init parse_lapic_timer_c2_ok(char *arg)
1555 local_apic_timer_c2_ok = 1;
1558 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
1560 static int __init apic_set_verbosity(char *str)
1562 if (strcmp("debug", str) == 0)
1563 apic_verbosity = APIC_DEBUG;
1564 else if (strcmp("verbose", str) == 0)
1565 apic_verbosity = APIC_VERBOSE;
1568 __setup("apic=", apic_set_verbosity);