arch/x86/kernel/apic/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/pci.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34 #include <linux/msi.h>
  35 #include <linux/htirq.h>
  36 #include <linux/freezer.h>
  37 #include <linux/kthread.h>
  38 #include <linux/jiffies.h>      /* time_after() */
  39 #ifdef CONFIG_ACPI
  40 #include <acpi/acpi_bus.h>
  41 #endif
  42 #include <linux/bootmem.h>
  43 #include <linux/dmar.h>
  44 #include <linux/hpet.h>
  45
  46 #include <asm/idle.h>
  47 #include <asm/io.h>
  48 #include <asm/smp.h>
  49 #include <asm/cpu.h>
  50 #include <asm/desc.h>
  51 #include <asm/proto.h>
  52 #include <asm/acpi.h>
  53 #include <asm/dma.h>
  54 #include <asm/timer.h>
  55 #include <asm/i8259.h>
  56 #include <asm/nmi.h>
  57 #include <asm/msidef.h>
  58 #include <asm/hypertransport.h>
  59 #include <asm/setup.h>
  60 #include <asm/irq_remapping.h>
  61 #include <asm/hpet.h>
  62 #include <asm/uv/uv_hub.h>
  63 #include <asm/uv/uv_irq.h>
  64
  65 #include <asm/apic.h>
  66
  67 #define __apicdebuginit(type) static type __init
  68
  69 /*
  70  *      Is the SiS APIC rmw bug present ?
  71  *      -1 = don't know, 0 = no, 1 = yes
  72  */
  73 int sis_apic_bug = -1;
  74
  75 static DEFINE_SPINLOCK(ioapic_lock);
  76 static DEFINE_SPINLOCK(vector_lock);
  77
  78 /*
  79  * # of IRQ routing registers
  80  */
  81 int nr_ioapic_registers[MAX_IO_APICS];
  82
  83 /* I/O APIC entries */
  84 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
  85 int nr_ioapics;
  86
  87 /* MP IRQ source entries */
  88 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
  89
  90 /* # of MP IRQ source entries */
  91 int mp_irq_entries;
  92
  93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
  94 int mp_bus_id_to_type[MAX_MP_BUSSES];
  95 #endif
  96
  97 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
  98
  99 int skip_ioapic_setup;
 100
 101 void arch_disable_smp_support(void)
 102 {
 103 #ifdef CONFIG_PCI
 104         noioapicquirk = 1;
 105         noioapicreroute = -1;
 106 #endif
 107         skip_ioapic_setup = 1;
 108 }
 109
 110 static int __init parse_noapic(char *str)
 111 {
 112         /* disable IO-APIC */
 113         arch_disable_smp_support();
 114         return 0;
 115 }
 116 early_param("noapic", parse_noapic);
 117
 118 struct irq_pin_list;
 119
 120 /*
 121  * This is performance-critical, we want to do it O(1)
 122  *
 123  * the indexing order of this array favors 1:1 mappings
 124  * between pins and IRQs.
 125  */
 126
 127 struct irq_pin_list {
 128         int apic, pin;
 129         struct irq_pin_list *next;
 130 };
 131
 132 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
 133 {
 134         struct irq_pin_list *pin;
 135         int node;
 136
 137         node = cpu_to_node(cpu);
 138
 139         pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
 140
 141         return pin;
 142 }
 143
 144 struct irq_cfg {
 145         struct irq_pin_list *irq_2_pin;
 146         cpumask_var_t domain;
 147         cpumask_var_t old_domain;
 148         unsigned move_cleanup_count;
 149         u8 vector;
 150         u8 move_in_progress : 1;
 151 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 152         u8 move_desc_pending : 1;
 153 #endif
 154 };
 155
 156 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
 157 #ifdef CONFIG_SPARSE_IRQ
 158 static struct irq_cfg irq_cfgx[] = {
 159 #else
 160 static struct irq_cfg irq_cfgx[NR_IRQS] = {
 161 #endif
 162         [0]  = { .vector = IRQ0_VECTOR,  },
 163         [1]  = { .vector = IRQ1_VECTOR,  },
 164         [2]  = { .vector = IRQ2_VECTOR,  },
 165         [3]  = { .vector = IRQ3_VECTOR,  },
 166         [4]  = { .vector = IRQ4_VECTOR,  },
 167         [5]  = { .vector = IRQ5_VECTOR,  },
 168         [6]  = { .vector = IRQ6_VECTOR,  },
 169         [7]  = { .vector = IRQ7_VECTOR,  },
 170         [8]  = { .vector = IRQ8_VECTOR,  },
 171         [9]  = { .vector = IRQ9_VECTOR,  },
 172         [10] = { .vector = IRQ10_VECTOR, },
 173         [11] = { .vector = IRQ11_VECTOR, },
 174         [12] = { .vector = IRQ12_VECTOR, },
 175         [13] = { .vector = IRQ13_VECTOR, },
 176         [14] = { .vector = IRQ14_VECTOR, },
 177         [15] = { .vector = IRQ15_VECTOR, },
 178 };
 179
 180 int __init arch_early_irq_init(void)
 181 {
 182         struct irq_cfg *cfg;
 183         struct irq_desc *desc;
 184         int count;
 185         int i;
 186
 187         cfg = irq_cfgx;
 188         count = ARRAY_SIZE(irq_cfgx);
 189
 190         for (i = 0; i < count; i++) {
 191                 desc = irq_to_desc(i);
 192                 desc->chip_data = &cfg[i];
 193                 alloc_bootmem_cpumask_var(&cfg[i].domain);
 194                 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
 195                 if (i < NR_IRQS_LEGACY)
 196                         cpumask_setall(cfg[i].domain);
 197         }
 198
 199         return 0;
 200 }
 201
 202 #ifdef CONFIG_SPARSE_IRQ
 203 static struct irq_cfg *irq_cfg(unsigned int irq)
 204 {
 205         struct irq_cfg *cfg = NULL;
 206         struct irq_desc *desc;
 207
 208         desc = irq_to_desc(irq);
 209         if (desc)
 210                 cfg = desc->chip_data;
 211
 212         return cfg;
 213 }
 214
 215 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
 216 {
 217         struct irq_cfg *cfg;
 218         int node;
 219
 220         node = cpu_to_node(cpu);
 221
 222         cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
 223         if (cfg) {
 224                 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
 225                         kfree(cfg);
 226                         cfg = NULL;
 227                 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
 228                                                           GFP_ATOMIC, node)) {
 229                         free_cpumask_var(cfg->domain);
 230                         kfree(cfg);
 231                         cfg = NULL;
 232                 } else {
 233                         cpumask_clear(cfg->domain);
 234                         cpumask_clear(cfg->old_domain);
 235                 }
 236         }
 237
 238         return cfg;
 239 }
 240
 241 int arch_init_chip_data(struct irq_desc *desc, int cpu)
 242 {
 243         struct irq_cfg *cfg;
 244
 245         cfg = desc->chip_data;
 246         if (!cfg) {
 247                 desc->chip_data = get_one_free_irq_cfg(cpu);
 248                 if (!desc->chip_data) {
 249                         printk(KERN_ERR "can not alloc irq_cfg\n");
 250                         BUG_ON(1);
 251                 }
 252         }
 253
 254         return 0;
 255 }
 256
 257 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 258
 259 static void
 260 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
 261 {
 262         struct irq_pin_list *old_entry, *head, *tail, *entry;
 263
 264         cfg->irq_2_pin = NULL;
 265         old_entry = old_cfg->irq_2_pin;
 266         if (!old_entry)
 267                 return;
 268
 269         entry = get_one_free_irq_2_pin(cpu);
 270         if (!entry)
 271                 return;
 272
 273         entry->apic     = old_entry->apic;
 274         entry->pin      = old_entry->pin;
 275         head            = entry;
 276         tail            = entry;
 277         old_entry       = old_entry->next;
 278         while (old_entry) {
 279                 entry = get_one_free_irq_2_pin(cpu);
 280                 if (!entry) {
 281                         entry = head;
 282                         while (entry) {
 283                                 head = entry->next;
 284                                 kfree(entry);
 285                                 entry = head;
 286                         }
 287                         /* still use the old one */
 288                         return;
 289                 }
 290                 entry->apic     = old_entry->apic;
 291                 entry->pin      = old_entry->pin;
 292                 tail->next      = entry;
 293                 tail            = entry;
 294                 old_entry       = old_entry->next;
 295         }
 296
 297         tail->next = NULL;
 298         cfg->irq_2_pin = head;
 299 }
 300
 301 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
 302 {
 303         struct irq_pin_list *entry, *next;
 304
 305         if (old_cfg->irq_2_pin == cfg->irq_2_pin)
 306                 return;
 307
 308         entry = old_cfg->irq_2_pin;
 309
 310         while (entry) {
 311                 next = entry->next;
 312                 kfree(entry);
 313                 entry = next;
 314         }
 315         old_cfg->irq_2_pin = NULL;
 316 }
 317
 318 void arch_init_copy_chip_data(struct irq_desc *old_desc,
 319                                  struct irq_desc *desc, int cpu)
 320 {
 321         struct irq_cfg *cfg;
 322         struct irq_cfg *old_cfg;
 323
 324         cfg = get_one_free_irq_cfg(cpu);
 325
 326         if (!cfg)
 327                 return;
 328
 329         desc->chip_data = cfg;
 330
 331         old_cfg = old_desc->chip_data;
 332
 333         memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
 334
 335         init_copy_irq_2_pin(old_cfg, cfg, cpu);
 336 }
 337
 338 static void free_irq_cfg(struct irq_cfg *old_cfg)
 339 {
 340         kfree(old_cfg);
 341 }
 342
 343 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
 344 {
 345         struct irq_cfg *old_cfg, *cfg;
 346
 347         old_cfg = old_desc->chip_data;
 348         cfg = desc->chip_data;
 349
 350         if (old_cfg == cfg)
 351                 return;
 352
 353         if (old_cfg) {
 354                 free_irq_2_pin(old_cfg, cfg);
 355                 free_irq_cfg(old_cfg);
 356                 old_desc->chip_data = NULL;
 357         }
 358 }
 359
 360 static void
 361 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 362 {
 363         struct irq_cfg *cfg = desc->chip_data;
 364
 365         if (!cfg->move_in_progress) {
 366                 /* it means that domain is not changed */
 367                 if (!cpumask_intersects(desc->affinity, mask))
 368                         cfg->move_desc_pending = 1;
 369         }
 370 }
 371 #endif
 372
 373 #else
 374 static struct irq_cfg *irq_cfg(unsigned int irq)
 375 {
 376         return irq < nr_irqs ? irq_cfgx + irq : NULL;
 377 }
 378
 379 #endif
 380
 381 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
 382 static inline void
 383 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 384 {
 385 }
 386 #endif
 387
 388 struct io_apic {
 389         unsigned int index;
 390         unsigned int unused[3];
 391         unsigned int data;
 392         unsigned int unused2[11];
 393         unsigned int eoi;
 394 };
 395
 396 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 397 {
 398         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 399                 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
 400 }
 401
 402 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
 403 {
 404         struct io_apic __iomem *io_apic = io_apic_base(apic);
 405         writel(vector, &io_apic->eoi);
 406 }
 407
 408 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 409 {
 410         struct io_apic __iomem *io_apic = io_apic_base(apic);
 411         writel(reg, &io_apic->index);
 412         return readl(&io_apic->data);
 413 }
 414
 415 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 416 {
 417         struct io_apic __iomem *io_apic = io_apic_base(apic);
 418         writel(reg, &io_apic->index);
 419         writel(value, &io_apic->data);
 420 }
 421
 422 /*
 423  * Re-write a value: to be used for read-modify-write
 424  * cycles where the read already set up the index register.
 425  *
 426  * Older SiS APIC requires we rewrite the index register
 427  */
 428 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 429 {
 430         struct io_apic __iomem *io_apic = io_apic_base(apic);
 431
 432         if (sis_apic_bug)
 433                 writel(reg, &io_apic->index);
 434         writel(value, &io_apic->data);
 435 }
 436
 437 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
 438 {
 439         struct irq_pin_list *entry;
 440         unsigned long flags;
 441
 442         spin_lock_irqsave(&ioapic_lock, flags);
 443         entry = cfg->irq_2_pin;
 444         for (;;) {
 445                 unsigned int reg;
 446                 int pin;
 447
 448                 if (!entry)
 449                         break;
 450                 pin = entry->pin;
 451                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 452                 /* Is the remote IRR bit set? */
 453                 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
 454                         spin_unlock_irqrestore(&ioapic_lock, flags);
 455                         return true;
 456                 }
 457                 if (!entry->next)
 458                         break;
 459                 entry = entry->next;
 460         }
 461         spin_unlock_irqrestore(&ioapic_lock, flags);
 462
 463         return false;
 464 }
 465
 466 union entry_union {
 467         struct { u32 w1, w2; };
 468         struct IO_APIC_route_entry entry;
 469 };
 470
 471 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 472 {
 473         union entry_union eu;
 474         unsigned long flags;
 475         spin_lock_irqsave(&ioapic_lock, flags);
 476         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 477         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 478         spin_unlock_irqrestore(&ioapic_lock, flags);
 479         return eu.entry;
 480 }
 481
 482 /*
 483  * When we write a new IO APIC routing entry, we need to write the high
 484  * word first! If the mask bit in the low word is clear, we will enable
 485  * the interrupt, and we need to make sure the entry is fully populated
 486  * before that happens.
 487  */
 488 static void
 489 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 490 {
 491         union entry_union eu;
 492         eu.entry = e;
 493         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 494         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 495 }
 496
 497 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 498 {
 499         unsigned long flags;
 500         spin_lock_irqsave(&ioapic_lock, flags);
 501         __ioapic_write_entry(apic, pin, e);
 502         spin_unlock_irqrestore(&ioapic_lock, flags);
 503 }
 504
 505 /*
 506  * When we mask an IO APIC routing entry, we need to write the low
 507  * word first, in order to set the mask bit before we change the
 508  * high bits!
 509  */
 510 static void ioapic_mask_entry(int apic, int pin)
 511 {
 512         unsigned long flags;
 513         union entry_union eu = { .entry.mask = 1 };
 514
 515         spin_lock_irqsave(&ioapic_lock, flags);
 516         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 517         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 518         spin_unlock_irqrestore(&ioapic_lock, flags);
 519 }
 520
 521 #ifdef CONFIG_SMP
 522 static void send_cleanup_vector(struct irq_cfg *cfg)
 523 {
 524         cpumask_var_t cleanup_mask;
 525
 526         if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
 527                 unsigned int i;
 528                 cfg->move_cleanup_count = 0;
 529                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
 530                         cfg->move_cleanup_count++;
 531                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
 532                         apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
 533         } else {
 534                 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
 535                 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
 536                 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
 537                 free_cpumask_var(cleanup_mask);
 538         }
 539         cfg->move_in_progress = 0;
 540 }
 541
 542 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
 543 {
 544         int apic, pin;
 545         struct irq_pin_list *entry;
 546         u8 vector = cfg->vector;
 547
 548         entry = cfg->irq_2_pin;
 549         for (;;) {
 550                 unsigned int reg;
 551
 552                 if (!entry)
 553                         break;
 554
 555                 apic = entry->apic;
 556                 pin = entry->pin;
 557                 /*
 558                  * With interrupt-remapping, destination information comes
 559                  * from interrupt-remapping table entry.
 560                  */
 561                 if (!irq_remapped(irq))
 562                         io_apic_write(apic, 0x11 + pin*2, dest);
 563                 reg = io_apic_read(apic, 0x10 + pin*2);
 564                 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
 565                 reg |= vector;
 566                 io_apic_modify(apic, 0x10 + pin*2, reg);
 567                 if (!entry->next)
 568                         break;
 569                 entry = entry->next;
 570         }
 571 }
 572
 573 static int
 574 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
 575
 576 /*
 577  * Either sets desc->affinity to a valid value, and returns
 578  * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
 579  * leaves desc->affinity untouched.
 580  */
 581 static unsigned int
 582 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
 583 {
 584         struct irq_cfg *cfg;
 585         unsigned int irq;
 586
 587         if (!cpumask_intersects(mask, cpu_online_mask))
 588                 return BAD_APICID;
 589
 590         irq = desc->irq;
 591         cfg = desc->chip_data;
 592         if (assign_irq_vector(irq, cfg, mask))
 593                 return BAD_APICID;
 594
 595         /* check that before desc->addinity get updated */
 596         set_extra_move_desc(desc, mask);
 597
 598         cpumask_copy(desc->affinity, mask);
 599
 600         return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
 601 }
 602
 603 static void
 604 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
 605 {
 606         struct irq_cfg *cfg;
 607         unsigned long flags;
 608         unsigned int dest;
 609         unsigned int irq;
 610
 611         irq = desc->irq;
 612         cfg = desc->chip_data;
 613
 614         spin_lock_irqsave(&ioapic_lock, flags);
 615         dest = set_desc_affinity(desc, mask);
 616         if (dest != BAD_APICID) {
 617                 /* Only the high 8 bits are valid. */
 618                 dest = SET_APIC_LOGICAL_ID(dest);
 619                 __target_IO_APIC_irq(irq, dest, cfg);
 620         }
 621         spin_unlock_irqrestore(&ioapic_lock, flags);
 622 }
 623
 624 static void
 625 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
 626 {
 627         struct irq_desc *desc;
 628
 629         desc = irq_to_desc(irq);
 630
 631         set_ioapic_affinity_irq_desc(desc, mask);
 632 }
 633 #endif /* CONFIG_SMP */
 634
 635 /*
 636  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 637  * shared ISA-space IRQs, so we have to support them. We are super
 638  * fast in the common case, and fast for shared ISA-space IRQs.
 639  */
 640 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
 641 {
 642         struct irq_pin_list *entry;
 643
 644         entry = cfg->irq_2_pin;
 645         if (!entry) {
 646                 entry = get_one_free_irq_2_pin(cpu);
 647                 if (!entry) {
 648                         printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
 649                                         apic, pin);
 650                         return;
 651                 }
 652                 cfg->irq_2_pin = entry;
 653                 entry->apic = apic;
 654                 entry->pin = pin;
 655                 return;
 656         }
 657
 658         while (entry->next) {
 659                 /* not again, please */
 660                 if (entry->apic == apic && entry->pin == pin)
 661                         return;
 662
 663                 entry = entry->next;
 664         }
 665
 666         entry->next = get_one_free_irq_2_pin(cpu);
 667         entry = entry->next;
 668         entry->apic = apic;
 669         entry->pin = pin;
 670 }
 671
 672 /*
 673  * Reroute an IRQ to a different pin.
 674  */
 675 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
 676                                       int oldapic, int oldpin,
 677                                       int newapic, int newpin)
 678 {
 679         struct irq_pin_list *entry = cfg->irq_2_pin;
 680         int replaced = 0;
 681
 682         while (entry) {
 683                 if (entry->apic == oldapic && entry->pin == oldpin) {
 684                         entry->apic = newapic;
 685                         entry->pin = newpin;
 686                         replaced = 1;
 687                         /* every one is different, right? */
 688                         break;
 689                 }
 690                 entry = entry->next;
 691         }
 692
 693         /* why? call replace before add? */
 694         if (!replaced)
 695                 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
 696 }
 697
 698 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
 699                                 int mask_and, int mask_or,
 700                                 void (*final)(struct irq_pin_list *entry))
 701 {
 702         int pin;
 703         struct irq_pin_list *entry;
 704
 705         for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
 706                 unsigned int reg;
 707                 pin = entry->pin;
 708                 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
 709                 reg &= mask_and;
 710                 reg |= mask_or;
 711                 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
 712                 if (final)
 713                         final(entry);
 714         }
 715 }
 716
 717 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
 718 {
 719         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
 720 }
 721
 722 #ifdef CONFIG_X86_64
 723 static void io_apic_sync(struct irq_pin_list *entry)
 724 {
 725         /*
 726          * Synchronize the IO-APIC and the CPU by doing
 727          * a dummy read from the IO-APIC
 728          */
 729         struct io_apic __iomem *io_apic;
 730         io_apic = io_apic_base(entry->apic);
 731         readl(&io_apic->data);
 732 }
 733
 734 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 735 {
 736         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
 737 }
 738 #else /* CONFIG_X86_32 */
 739 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 740 {
 741         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
 742 }
 743
 744 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
 745 {
 746         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
 747                         IO_APIC_REDIR_MASKED, NULL);
 748 }
 749
 750 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
 751 {
 752         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
 753                         IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
 754 }
 755 #endif /* CONFIG_X86_32 */
 756
 757 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
 758 {
 759         struct irq_cfg *cfg = desc->chip_data;
 760         unsigned long flags;
 761
 762         BUG_ON(!cfg);
 763
 764         spin_lock_irqsave(&ioapic_lock, flags);
 765         __mask_IO_APIC_irq(cfg);
 766         spin_unlock_irqrestore(&ioapic_lock, flags);
 767 }
 768
 769 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
 770 {
 771         struct irq_cfg *cfg = desc->chip_data;
 772         unsigned long flags;
 773
 774         spin_lock_irqsave(&ioapic_lock, flags);
 775         __unmask_IO_APIC_irq(cfg);
 776         spin_unlock_irqrestore(&ioapic_lock, flags);
 777 }
 778
 779 static void mask_IO_APIC_irq(unsigned int irq)
 780 {
 781         struct irq_desc *desc = irq_to_desc(irq);
 782
 783         mask_IO_APIC_irq_desc(desc);
 784 }
 785 static void unmask_IO_APIC_irq(unsigned int irq)
 786 {
 787         struct irq_desc *desc = irq_to_desc(irq);
 788
 789         unmask_IO_APIC_irq_desc(desc);
 790 }
 791
 792 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 793 {
 794         struct IO_APIC_route_entry entry;
 795
 796         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 797         entry = ioapic_read_entry(apic, pin);
 798         if (entry.delivery_mode == dest_SMI)
 799                 return;
 800         /*
 801          * Disable it in the IO-APIC irq-routing table:
 802          */
 803         ioapic_mask_entry(apic, pin);
 804 }
 805
 806 static void clear_IO_APIC (void)
 807 {
 808         int apic, pin;
 809
 810         for (apic = 0; apic < nr_ioapics; apic++)
 811                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 812                         clear_IO_APIC_pin(apic, pin);
 813 }
 814
 815 #ifdef CONFIG_X86_32
 816 /*
 817  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 818  * specific CPU-side IRQs.
 819  */
 820
 821 #define MAX_PIRQS 8
 822 static int pirq_entries[MAX_PIRQS] = {
 823         [0 ... MAX_PIRQS - 1] = -1
 824 };
 825
 826 static int __init ioapic_pirq_setup(char *str)
 827 {
 828         int i, max;
 829         int ints[MAX_PIRQS+1];
 830
 831         get_options(str, ARRAY_SIZE(ints), ints);
 832
 833         apic_printk(APIC_VERBOSE, KERN_INFO
 834                         "PIRQ redirection, working around broken MP-BIOS.\n");
 835         max = MAX_PIRQS;
 836         if (ints[0] < MAX_PIRQS)
 837                 max = ints[0];
 838
 839         for (i = 0; i < max; i++) {
 840                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 841                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 842                 /*
 843                  * PIRQs are mapped upside down, usually.
 844                  */
 845                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 846         }
 847         return 1;
 848 }
 849
 850 __setup("pirq=", ioapic_pirq_setup);
 851 #endif /* CONFIG_X86_32 */
 852
 853 #ifdef CONFIG_INTR_REMAP
 854 /* I/O APIC RTE contents at the OS boot up */
 855 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
 856
 857 /*
 858  * Saves all the IO-APIC RTE's
 859  */
 860 int save_IO_APIC_setup(void)
 861 {
 862         union IO_APIC_reg_01 reg_01;
 863         unsigned long flags;
 864         int apic, pin;
 865
 866         /*
 867          * The number of IO-APIC IRQ registers (== #pins):
 868          */
 869         for (apic = 0; apic < nr_ioapics; apic++) {
 870                 spin_lock_irqsave(&ioapic_lock, flags);
 871                 reg_01.raw = io_apic_read(apic, 1);
 872                 spin_unlock_irqrestore(&ioapic_lock, flags);
 873                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
 874         }
 875
 876         for (apic = 0; apic < nr_ioapics; apic++) {
 877                 early_ioapic_entries[apic] =
 878                         kzalloc(sizeof(struct IO_APIC_route_entry) *
 879                                 nr_ioapic_registers[apic], GFP_KERNEL);
 880                 if (!early_ioapic_entries[apic])
 881                         goto nomem;
 882         }
 883
 884         for (apic = 0; apic < nr_ioapics; apic++)
 885                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 886                         early_ioapic_entries[apic][pin] =
 887                                 ioapic_read_entry(apic, pin);
 888
 889         return 0;
 890
 891 nomem:
 892         while (apic >= 0)
 893                 kfree(early_ioapic_entries[apic--]);
 894         memset(early_ioapic_entries, 0,
 895                 ARRAY_SIZE(early_ioapic_entries));
 896
 897         return -ENOMEM;
 898 }
 899
 900 void mask_IO_APIC_setup(void)
 901 {
 902         int apic, pin;
 903
 904         for (apic = 0; apic < nr_ioapics; apic++) {
 905                 if (!early_ioapic_entries[apic])
 906                         break;
 907                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 908                         struct IO_APIC_route_entry entry;
 909
 910                         entry = early_ioapic_entries[apic][pin];
 911                         if (!entry.mask) {
 912                                 entry.mask = 1;
 913                                 ioapic_write_entry(apic, pin, entry);
 914                         }
 915                 }
 916         }
 917 }
 918
 919 void restore_IO_APIC_setup(void)
 920 {
 921         int apic, pin;
 922
 923         for (apic = 0; apic < nr_ioapics; apic++) {
 924                 if (!early_ioapic_entries[apic])
 925                         break;
 926                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 927                         ioapic_write_entry(apic, pin,
 928                                            early_ioapic_entries[apic][pin]);
 929                 kfree(early_ioapic_entries[apic]);
 930                 early_ioapic_entries[apic] = NULL;
 931         }
 932 }
 933
 934 void reinit_intr_remapped_IO_APIC(int intr_remapping)
 935 {
 936         /*
 937          * for now plain restore of previous settings.
 938          * TBD: In the case of OS enabling interrupt-remapping,
 939          * IO-APIC RTE's need to be setup to point to interrupt-remapping
 940          * table entries. for now, do a plain restore, and wait for
 941          * the setup_IO_APIC_irqs() to do proper initialization.
 942          */
 943         restore_IO_APIC_setup();
 944 }
 945 #endif
 946
 947 /*
 948  * Find the IRQ entry number of a certain pin.
 949  */
 950 static int find_irq_entry(int apic, int pin, int type)
 951 {
 952         int i;
 953
 954         for (i = 0; i < mp_irq_entries; i++)
 955                 if (mp_irqs[i].irqtype == type &&
 956                     (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
 957                      mp_irqs[i].dstapic == MP_APIC_ALL) &&
 958                     mp_irqs[i].dstirq == pin)
 959                         return i;
 960
 961         return -1;
 962 }
 963
 964 /*
 965  * Find the pin to which IRQ[irq] (ISA) is connected
 966  */
 967 static int __init find_isa_irq_pin(int irq, int type)
 968 {
 969         int i;
 970
 971         for (i = 0; i < mp_irq_entries; i++) {
 972                 int lbus = mp_irqs[i].srcbus;
 973
 974                 if (test_bit(lbus, mp_bus_not_pci) &&
 975                     (mp_irqs[i].irqtype == type) &&
 976                     (mp_irqs[i].srcbusirq == irq))
 977
 978                         return mp_irqs[i].dstirq;
 979         }
 980         return -1;
 981 }
 982
 983 static int __init find_isa_irq_apic(int irq, int type)
 984 {
 985         int i;
 986
 987         for (i = 0; i < mp_irq_entries; i++) {
 988                 int lbus = mp_irqs[i].srcbus;
 989
 990                 if (test_bit(lbus, mp_bus_not_pci) &&
 991                     (mp_irqs[i].irqtype == type) &&
 992                     (mp_irqs[i].srcbusirq == irq))
 993                         break;
 994         }
 995         if (i < mp_irq_entries) {
 996                 int apic;
 997                 for(apic = 0; apic < nr_ioapics; apic++) {
 998                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
 999                                 return apic;
1000                 }
1001         }
1002
1003         return -1;
1004 }
1005
1006 /*
1007  * Find a specific PCI IRQ entry.
1008  * Not an __init, possibly needed by modules
1009  */
1010 static int pin_2_irq(int idx, int apic, int pin);
1011
1012 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1013 {
1014         int apic, i, best_guess = -1;
1015
1016         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1017                 bus, slot, pin);
1018         if (test_bit(bus, mp_bus_not_pci)) {
1019                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1020                 return -1;
1021         }
1022         for (i = 0; i < mp_irq_entries; i++) {
1023                 int lbus = mp_irqs[i].srcbus;
1024
1025                 for (apic = 0; apic < nr_ioapics; apic++)
1026                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1027                             mp_irqs[i].dstapic == MP_APIC_ALL)
1028                                 break;
1029
1030                 if (!test_bit(lbus, mp_bus_not_pci) &&
1031                     !mp_irqs[i].irqtype &&
1032                     (bus == lbus) &&
1033                     (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1034                         int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1035
1036                         if (!(apic || IO_APIC_IRQ(irq)))
1037                                 continue;
1038
1039                         if (pin == (mp_irqs[i].srcbusirq & 3))
1040                                 return irq;
1041                         /*
1042                          * Use the first all-but-pin matching entry as a
1043                          * best-guess fuzzy result for broken mptables.
1044                          */
1045                         if (best_guess < 0)
1046                                 best_guess = irq;
1047                 }
1048         }
1049         return best_guess;
1050 }
1051
1052 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1053
1054 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1055 /*
1056  * EISA Edge/Level control register, ELCR
1057  */
1058 static int EISA_ELCR(unsigned int irq)
1059 {
1060         if (irq < NR_IRQS_LEGACY) {
1061                 unsigned int port = 0x4d0 + (irq >> 3);
1062                 return (inb(port) >> (irq & 7)) & 1;
1063         }
1064         apic_printk(APIC_VERBOSE, KERN_INFO
1065                         "Broken MPtable reports ISA irq %d\n", irq);
1066         return 0;
1067 }
1068
1069 #endif
1070
1071 /* ISA interrupts are always polarity zero edge triggered,
1072  * when listed as conforming in the MP table. */
1073
1074 #define default_ISA_trigger(idx)        (0)
1075 #define default_ISA_polarity(idx)       (0)
1076
1077 /* EISA interrupts are always polarity zero and can be edge or level
1078  * trigger depending on the ELCR value.  If an interrupt is listed as
1079  * EISA conforming in the MP table, that means its trigger type must
1080  * be read in from the ELCR */
1081
1082 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].srcbusirq))
1083 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
1084
1085 /* PCI interrupts are always polarity one level triggered,
1086  * when listed as conforming in the MP table. */
1087
1088 #define default_PCI_trigger(idx)        (1)
1089 #define default_PCI_polarity(idx)       (1)
1090
1091 /* MCA interrupts are always polarity zero level triggered,
1092  * when listed as conforming in the MP table. */
1093
1094 #define default_MCA_trigger(idx)        (1)
1095 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
1096
1097 static int MPBIOS_polarity(int idx)
1098 {
1099         int bus = mp_irqs[idx].srcbus;
1100         int polarity;
1101
1102         /*
1103          * Determine IRQ line polarity (high active or low active):
1104          */
1105         switch (mp_irqs[idx].irqflag & 3)
1106         {
1107                 case 0: /* conforms, ie. bus-type dependent polarity */
1108                         if (test_bit(bus, mp_bus_not_pci))
1109                                 polarity = default_ISA_polarity(idx);
1110                         else
1111                                 polarity = default_PCI_polarity(idx);
1112                         break;
1113                 case 1: /* high active */
1114                 {
1115                         polarity = 0;
1116                         break;
1117                 }
1118                 case 2: /* reserved */
1119                 {
1120                         printk(KERN_WARNING "broken BIOS!!\n");
1121                         polarity = 1;
1122                         break;
1123                 }
1124                 case 3: /* low active */
1125                 {
1126                         polarity = 1;
1127                         break;
1128                 }
1129                 default: /* invalid */
1130                 {
1131                         printk(KERN_WARNING "broken BIOS!!\n");
1132                         polarity = 1;
1133                         break;
1134                 }
1135         }
1136         return polarity;
1137 }
1138
1139 static int MPBIOS_trigger(int idx)
1140 {
1141         int bus = mp_irqs[idx].srcbus;
1142         int trigger;
1143
1144         /*
1145          * Determine IRQ trigger mode (edge or level sensitive):
1146          */
1147         switch ((mp_irqs[idx].irqflag>>2) & 3)
1148         {
1149                 case 0: /* conforms, ie. bus-type dependent */
1150                         if (test_bit(bus, mp_bus_not_pci))
1151                                 trigger = default_ISA_trigger(idx);
1152                         else
1153                                 trigger = default_PCI_trigger(idx);
1154 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1155                         switch (mp_bus_id_to_type[bus]) {
1156                                 case MP_BUS_ISA: /* ISA pin */
1157                                 {
1158                                         /* set before the switch */
1159                                         break;
1160                                 }
1161                                 case MP_BUS_EISA: /* EISA pin */
1162                                 {
1163                                         trigger = default_EISA_trigger(idx);
1164                                         break;
1165                                 }
1166                                 case MP_BUS_PCI: /* PCI pin */
1167                                 {
1168                                         /* set before the switch */
1169                                         break;
1170                                 }
1171                                 case MP_BUS_MCA: /* MCA pin */
1172                                 {
1173                                         trigger = default_MCA_trigger(idx);
1174                                         break;
1175                                 }
1176                                 default:
1177                                 {
1178                                         printk(KERN_WARNING "broken BIOS!!\n");
1179                                         trigger = 1;
1180                                         break;
1181                                 }
1182                         }
1183 #endif
1184                         break;
1185                 case 1: /* edge */
1186                 {
1187                         trigger = 0;
1188                         break;
1189                 }
1190                 case 2: /* reserved */
1191                 {
1192                         printk(KERN_WARNING "broken BIOS!!\n");
1193                         trigger = 1;
1194                         break;
1195                 }
1196                 case 3: /* level */
1197                 {
1198                         trigger = 1;
1199                         break;
1200                 }
1201                 default: /* invalid */
1202                 {
1203                         printk(KERN_WARNING "broken BIOS!!\n");
1204                         trigger = 0;
1205                         break;
1206                 }
1207         }
1208         return trigger;
1209 }
1210
1211 static inline int irq_polarity(int idx)
1212 {
1213         return MPBIOS_polarity(idx);
1214 }
1215
1216 static inline int irq_trigger(int idx)
1217 {
1218         return MPBIOS_trigger(idx);
1219 }
1220
1221 int (*ioapic_renumber_irq)(int ioapic, int irq);
1222 static int pin_2_irq(int idx, int apic, int pin)
1223 {
1224         int irq, i;
1225         int bus = mp_irqs[idx].srcbus;
1226
1227         /*
1228          * Debugging check, we are in big trouble if this message pops up!
1229          */
1230         if (mp_irqs[idx].dstirq != pin)
1231                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1232
1233         if (test_bit(bus, mp_bus_not_pci)) {
1234                 irq = mp_irqs[idx].srcbusirq;
1235         } else {
1236                 /*
1237                  * PCI IRQs are mapped in order
1238                  */
1239                 i = irq = 0;
1240                 while (i < apic)
1241                         irq += nr_ioapic_registers[i++];
1242                 irq += pin;
1243                 /*
1244                  * For MPS mode, so far only needed by ES7000 platform
1245                  */
1246                 if (ioapic_renumber_irq)
1247                         irq = ioapic_renumber_irq(apic, irq);
1248         }
1249
1250 #ifdef CONFIG_X86_32
1251         /*
1252          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1253          */
1254         if ((pin >= 16) && (pin <= 23)) {
1255                 if (pirq_entries[pin-16] != -1) {
1256                         if (!pirq_entries[pin-16]) {
1257                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1258                                                 "disabling PIRQ%d\n", pin-16);
1259                         } else {
1260                                 irq = pirq_entries[pin-16];
1261                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1262                                                 "using PIRQ%d -> IRQ %d\n",
1263                                                 pin-16, irq);
1264                         }
1265                 }
1266         }
1267 #endif
1268
1269         return irq;
1270 }
1271
1272 void lock_vector_lock(void)
1273 {
1274         /* Used to the online set of cpus does not change
1275          * during assign_irq_vector.
1276          */
1277         spin_lock(&vector_lock);
1278 }
1279
1280 void unlock_vector_lock(void)
1281 {
1282         spin_unlock(&vector_lock);
1283 }
1284
1285 static int
1286 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1287 {
1288         /*
1289          * NOTE! The local APIC isn't very good at handling
1290          * multiple interrupts at the same interrupt level.
1291          * As the interrupt level is determined by taking the
1292          * vector number and shifting that right by 4, we
1293          * want to spread these out a bit so that they don't
1294          * all fall in the same interrupt level.
1295          *
1296          * Also, we've got to be careful not to trash gate
1297          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1298          */
1299         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1300         unsigned int old_vector;
1301         int cpu, err;
1302         cpumask_var_t tmp_mask;
1303
1304         if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1305                 return -EBUSY;
1306
1307         if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1308                 return -ENOMEM;
1309
1310         old_vector = cfg->vector;
1311         if (old_vector) {
1312                 cpumask_and(tmp_mask, mask, cpu_online_mask);
1313                 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1314                 if (!cpumask_empty(tmp_mask)) {
1315                         free_cpumask_var(tmp_mask);
1316                         return 0;
1317                 }
1318         }
1319
1320         /* Only try and allocate irqs on cpus that are present */
1321         err = -ENOSPC;
1322         for_each_cpu_and(cpu, mask, cpu_online_mask) {
1323                 int new_cpu;
1324                 int vector, offset;
1325
1326                 apic->vector_allocation_domain(cpu, tmp_mask);
1327
1328                 vector = current_vector;
1329                 offset = current_offset;
1330 next:
1331                 vector += 8;
1332                 if (vector >= first_system_vector) {
1333                         /* If out of vectors on large boxen, must share them. */
1334                         offset = (offset + 1) % 8;
1335                         vector = FIRST_DEVICE_VECTOR + offset;
1336                 }
1337                 if (unlikely(current_vector == vector))
1338                         continue;
1339
1340                 if (test_bit(vector, used_vectors))
1341                         goto next;
1342
1343                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1344                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1345                                 goto next;
1346                 /* Found one! */
1347                 current_vector = vector;
1348                 current_offset = offset;
1349                 if (old_vector) {
1350                         cfg->move_in_progress = 1;
1351                         cpumask_copy(cfg->old_domain, cfg->domain);
1352                 }
1353                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1354                         per_cpu(vector_irq, new_cpu)[vector] = irq;
1355                 cfg->vector = vector;
1356                 cpumask_copy(cfg->domain, tmp_mask);
1357                 err = 0;
1358                 break;
1359         }
1360         free_cpumask_var(tmp_mask);
1361         return err;
1362 }
1363
1364 static int
1365 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1366 {
1367         int err;
1368         unsigned long flags;
1369
1370         spin_lock_irqsave(&vector_lock, flags);
1371         err = __assign_irq_vector(irq, cfg, mask);
1372         spin_unlock_irqrestore(&vector_lock, flags);
1373         return err;
1374 }
1375
1376 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1377 {
1378         int cpu, vector;
1379
1380         BUG_ON(!cfg->vector);
1381
1382         vector = cfg->vector;
1383         for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1384                 per_cpu(vector_irq, cpu)[vector] = -1;
1385
1386         cfg->vector = 0;
1387         cpumask_clear(cfg->domain);
1388
1389         if (likely(!cfg->move_in_progress))
1390                 return;
1391         for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1392                 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1393                                                                 vector++) {
1394                         if (per_cpu(vector_irq, cpu)[vector] != irq)
1395                                 continue;
1396                         per_cpu(vector_irq, cpu)[vector] = -1;
1397                         break;
1398                 }
1399         }
1400         cfg->move_in_progress = 0;
1401 }
1402
1403 void __setup_vector_irq(int cpu)
1404 {
1405         /* Initialize vector_irq on a new cpu */
1406         /* This function must be called with vector_lock held */
1407         int irq, vector;
1408         struct irq_cfg *cfg;
1409         struct irq_desc *desc;
1410
1411         /* Mark the inuse vectors */
1412         for_each_irq_desc(irq, desc) {
1413                 cfg = desc->chip_data;
1414                 if (!cpumask_test_cpu(cpu, cfg->domain))
1415                         continue;
1416                 vector = cfg->vector;
1417                 per_cpu(vector_irq, cpu)[vector] = irq;
1418         }
1419         /* Mark the free vectors */
1420         for (vector = 0; vector < NR_VECTORS; ++vector) {
1421                 irq = per_cpu(vector_irq, cpu)[vector];
1422                 if (irq < 0)
1423                         continue;
1424
1425                 cfg = irq_cfg(irq);
1426                 if (!cpumask_test_cpu(cpu, cfg->domain))
1427                         per_cpu(vector_irq, cpu)[vector] = -1;
1428         }
1429 }
1430
1431 static struct irq_chip ioapic_chip;
1432 static struct irq_chip ir_ioapic_chip;
1433 static struct irq_chip msi_ir_chip;
1434
1435 #define IOAPIC_AUTO     -1
1436 #define IOAPIC_EDGE     0
1437 #define IOAPIC_LEVEL    1
1438
1439 #ifdef CONFIG_X86_32
1440 static inline int IO_APIC_irq_trigger(int irq)
1441 {
1442         int apic, idx, pin;
1443
1444         for (apic = 0; apic < nr_ioapics; apic++) {
1445                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1446                         idx = find_irq_entry(apic, pin, mp_INT);
1447                         if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1448                                 return irq_trigger(idx);
1449                 }
1450         }
1451         /*
1452          * nonexistent IRQs are edge default
1453          */
1454         return 0;
1455 }
1456 #else
1457 static inline int IO_APIC_irq_trigger(int irq)
1458 {
1459         return 1;
1460 }
1461 #endif
1462
1463 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1464 {
1465
1466         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1467             trigger == IOAPIC_LEVEL)
1468                 desc->status |= IRQ_LEVEL;
1469         else
1470                 desc->status &= ~IRQ_LEVEL;
1471
1472         if (irq_remapped(irq)) {
1473                 desc->status |= IRQ_MOVE_PCNTXT;
1474                 if (trigger)
1475                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1476                                                       handle_fasteoi_irq,
1477                                                      "fasteoi");
1478                 else
1479                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1480                                                       handle_edge_irq, "edge");
1481                 return;
1482         }
1483
1484         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1485             trigger == IOAPIC_LEVEL)
1486                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1487                                               handle_fasteoi_irq,
1488                                               "fasteoi");
1489         else
1490                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1491                                               handle_edge_irq, "edge");
1492 }
1493
1494 int setup_ioapic_entry(int apic_id, int irq,
1495                        struct IO_APIC_route_entry *entry,
1496                        unsigned int destination, int trigger,
1497                        int polarity, int vector, int pin)
1498 {
1499         /*
1500          * add it to the IO-APIC irq-routing table:
1501          */
1502         memset(entry,0,sizeof(*entry));
1503
1504         if (intr_remapping_enabled) {
1505                 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1506                 struct irte irte;
1507                 struct IR_IO_APIC_route_entry *ir_entry =
1508                         (struct IR_IO_APIC_route_entry *) entry;
1509                 int index;
1510
1511                 if (!iommu)
1512                         panic("No mapping iommu for ioapic %d\n", apic_id);
1513
1514                 index = alloc_irte(iommu, irq, 1);
1515                 if (index < 0)
1516                         panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1517
1518                 memset(&irte, 0, sizeof(irte));
1519
1520                 irte.present = 1;
1521                 irte.dst_mode = apic->irq_dest_mode;
1522                 /*
1523                  * Trigger mode in the IRTE will always be edge, and the
1524                  * actual level or edge trigger will be setup in the IO-APIC
1525                  * RTE. This will help simplify level triggered irq migration.
1526                  * For more details, see the comments above explainig IO-APIC
1527                  * irq migration in the presence of interrupt-remapping.
1528                  */
1529                 irte.trigger_mode = 0;
1530                 irte.dlvry_mode = apic->irq_delivery_mode;
1531                 irte.vector = vector;
1532                 irte.dest_id = IRTE_DEST(destination);
1533
1534                 modify_irte(irq, &irte);
1535
1536                 ir_entry->index2 = (index >> 15) & 0x1;
1537                 ir_entry->zero = 0;
1538                 ir_entry->format = 1;
1539                 ir_entry->index = (index & 0x7fff);
1540                 /*
1541                  * IO-APIC RTE will be configured with virtual vector.
1542                  * irq handler will do the explicit EOI to the io-apic.
1543                  */
1544                 ir_entry->vector = pin;
1545         } else {
1546                 entry->delivery_mode = apic->irq_delivery_mode;
1547                 entry->dest_mode = apic->irq_dest_mode;
1548                 entry->dest = destination;
1549                 entry->vector = vector;
1550         }
1551
1552         entry->mask = 0;                                /* enable IRQ */
1553         entry->trigger = trigger;
1554         entry->polarity = polarity;
1555
1556         /* Mask level triggered irqs.
1557          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1558          */
1559         if (trigger)
1560                 entry->mask = 1;
1561         return 0;
1562 }
1563
1564 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1565                               int trigger, int polarity)
1566 {
1567         struct irq_cfg *cfg;
1568         struct IO_APIC_route_entry entry;
1569         unsigned int dest;
1570
1571         if (!IO_APIC_IRQ(irq))
1572                 return;
1573
1574         cfg = desc->chip_data;
1575
1576         if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1577                 return;
1578
1579         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1580
1581         apic_printk(APIC_VERBOSE,KERN_DEBUG
1582                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1583                     "IRQ %d Mode:%i Active:%i)\n",
1584                     apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1585                     irq, trigger, polarity);
1586
1587
1588         if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1589                                dest, trigger, polarity, cfg->vector, pin)) {
1590                 printk("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
1591                        mp_ioapics[apic_id].apicid, pin);
1592                 __clear_irq_vector(irq, cfg);
1593                 return;
1594         }
1595
1596         ioapic_register_intr(irq, desc, trigger);
1597         if (irq < NR_IRQS_LEGACY)
1598                 disable_8259A_irq(irq);
1599
1600         ioapic_write_entry(apic_id, pin, entry);
1601 }
1602
1603 static void __init setup_IO_APIC_irqs(void)
1604 {
1605         int apic_id, pin, idx, irq;
1606         int notcon = 0;
1607         struct irq_desc *desc;
1608         struct irq_cfg *cfg;
1609         int cpu = boot_cpu_id;
1610
1611         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1612
1613         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1614                 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1615
1616                         idx = find_irq_entry(apic_id, pin, mp_INT);
1617                         if (idx == -1) {
1618                                 if (!notcon) {
1619                                         notcon = 1;
1620                                         apic_printk(APIC_VERBOSE,
1621                                                 KERN_DEBUG " %d-%d",
1622                                                 mp_ioapics[apic_id].apicid, pin);
1623                                 } else
1624                                         apic_printk(APIC_VERBOSE, " %d-%d",
1625                                                 mp_ioapics[apic_id].apicid, pin);
1626                                 continue;
1627                         }
1628                         if (notcon) {
1629                                 apic_printk(APIC_VERBOSE,
1630                                         " (apicid-pin) not connected\n");
1631                                 notcon = 0;
1632                         }
1633
1634                         irq = pin_2_irq(idx, apic_id, pin);
1635
1636                         /*
1637                          * Skip the timer IRQ if there's a quirk handler
1638                          * installed and if it returns 1:
1639                          */
1640                         if (apic->multi_timer_check &&
1641                                         apic->multi_timer_check(apic_id, irq))
1642                                 continue;
1643
1644                         desc = irq_to_desc_alloc_cpu(irq, cpu);
1645                         if (!desc) {
1646                                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1647                                 continue;
1648                         }
1649                         cfg = desc->chip_data;
1650                         add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1651
1652                         setup_IO_APIC_irq(apic_id, pin, irq, desc,
1653                                         irq_trigger(idx), irq_polarity(idx));
1654                 }
1655         }
1656
1657         if (notcon)
1658                 apic_printk(APIC_VERBOSE,
1659                         " (apicid-pin) not connected\n");
1660 }
1661
1662 /*
1663  * Set up the timer pin, possibly with the 8259A-master behind.
1664  */
1665 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1666                                         int vector)
1667 {
1668         struct IO_APIC_route_entry entry;
1669
1670         if (intr_remapping_enabled)
1671                 return;
1672
1673         memset(&entry, 0, sizeof(entry));
1674
1675         /*
1676          * We use logical delivery to get the timer IRQ
1677          * to the first CPU.
1678          */
1679         entry.dest_mode = apic->irq_dest_mode;
1680         entry.mask = 0;                 /* don't mask IRQ for edge */
1681         entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1682         entry.delivery_mode = apic->irq_delivery_mode;
1683         entry.polarity = 0;
1684         entry.trigger = 0;
1685         entry.vector = vector;
1686
1687         /*
1688          * The timer IRQ doesn't have to know that behind the
1689          * scene we may have a 8259A-master in AEOI mode ...
1690          */
1691         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1692
1693         /*
1694          * Add it to the IO-APIC irq-routing table:
1695          */
1696         ioapic_write_entry(apic_id, pin, entry);
1697 }
1698
1699
1700 __apicdebuginit(void) print_IO_APIC(void)
1701 {
1702         int apic, i;
1703         union IO_APIC_reg_00 reg_00;
1704         union IO_APIC_reg_01 reg_01;
1705         union IO_APIC_reg_02 reg_02;
1706         union IO_APIC_reg_03 reg_03;
1707         unsigned long flags;
1708         struct irq_cfg *cfg;
1709         struct irq_desc *desc;
1710         unsigned int irq;
1711
1712         if (apic_verbosity == APIC_QUIET)
1713                 return;
1714
1715         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1716         for (i = 0; i < nr_ioapics; i++)
1717                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1718                        mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1719
1720         /*
1721          * We are a bit conservative about what we expect.  We have to
1722          * know about every hardware change ASAP.
1723          */
1724         printk(KERN_INFO "testing the IO APIC.......................\n");
1725
1726         for (apic = 0; apic < nr_ioapics; apic++) {
1727
1728         spin_lock_irqsave(&ioapic_lock, flags);
1729         reg_00.raw = io_apic_read(apic, 0);
1730         reg_01.raw = io_apic_read(apic, 1);
1731         if (reg_01.bits.version >= 0x10)
1732                 reg_02.raw = io_apic_read(apic, 2);
1733         if (reg_01.bits.version >= 0x20)
1734                 reg_03.raw = io_apic_read(apic, 3);
1735         spin_unlock_irqrestore(&ioapic_lock, flags);
1736
1737         printk("\n");
1738         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1739         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1740         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1741         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1742         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1743
1744         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1745         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1746
1747         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1748         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1749
1750         /*
1751          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1752          * but the value of reg_02 is read as the previous read register
1753          * value, so ignore it if reg_02 == reg_01.
1754          */
1755         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1756                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1757                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1758         }
1759
1760         /*
1761          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1762          * or reg_03, but the value of reg_0[23] is read as the previous read
1763          * register value, so ignore it if reg_03 == reg_0[12].
1764          */
1765         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1766             reg_03.raw != reg_01.raw) {
1767                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1768                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1769         }
1770
1771         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1772
1773         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1774                           " Stat Dmod Deli Vect:   \n");
1775
1776         for (i = 0; i <= reg_01.bits.entries; i++) {
1777                 struct IO_APIC_route_entry entry;
1778
1779                 entry = ioapic_read_entry(apic, i);
1780
1781                 printk(KERN_DEBUG " %02x %03X ",
1782                         i,
1783                         entry.dest
1784                 );
1785
1786                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1787                         entry.mask,
1788                         entry.trigger,
1789                         entry.irr,
1790                         entry.polarity,
1791                         entry.delivery_status,
1792                         entry.dest_mode,
1793                         entry.delivery_mode,
1794                         entry.vector
1795                 );
1796         }
1797         }
1798         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1799         for_each_irq_desc(irq, desc) {
1800                 struct irq_pin_list *entry;
1801
1802                 cfg = desc->chip_data;
1803                 entry = cfg->irq_2_pin;
1804                 if (!entry)
1805                         continue;
1806                 printk(KERN_DEBUG "IRQ%d ", irq);
1807                 for (;;) {
1808                         printk("-> %d:%d", entry->apic, entry->pin);
1809                         if (!entry->next)
1810                                 break;
1811                         entry = entry->next;
1812                 }
1813                 printk("\n");
1814         }
1815
1816         printk(KERN_INFO ".................................... done.\n");
1817
1818         return;
1819 }
1820
1821 __apicdebuginit(void) print_APIC_bitfield(int base)
1822 {
1823         unsigned int v;
1824         int i, j;
1825
1826         if (apic_verbosity == APIC_QUIET)
1827                 return;
1828
1829         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1830         for (i = 0; i < 8; i++) {
1831                 v = apic_read(base + i*0x10);
1832                 for (j = 0; j < 32; j++) {
1833                         if (v & (1<<j))
1834                                 printk("1");
1835                         else
1836                                 printk("0");
1837                 }
1838                 printk("\n");
1839         }
1840 }
1841
1842 __apicdebuginit(void) print_local_APIC(void *dummy)
1843 {
1844         unsigned int v, ver, maxlvt;
1845         u64 icr;
1846
1847         if (apic_verbosity == APIC_QUIET)
1848                 return;
1849
1850         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1851                 smp_processor_id(), hard_smp_processor_id());
1852         v = apic_read(APIC_ID);
1853         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, read_apic_id());
1854         v = apic_read(APIC_LVR);
1855         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1856         ver = GET_APIC_VERSION(v);
1857         maxlvt = lapic_get_maxlvt();
1858
1859         v = apic_read(APIC_TASKPRI);
1860         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1861
1862         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1863                 if (!APIC_XAPIC(ver)) {
1864                         v = apic_read(APIC_ARBPRI);
1865                         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1866                                v & APIC_ARBPRI_MASK);
1867                 }
1868                 v = apic_read(APIC_PROCPRI);
1869                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1870         }
1871
1872         /*
1873          * Remote read supported only in the 82489DX and local APIC for
1874          * Pentium processors.
1875          */
1876         if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1877                 v = apic_read(APIC_RRR);
1878                 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1879         }
1880
1881         v = apic_read(APIC_LDR);
1882         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1883         if (!x2apic_enabled()) {
1884                 v = apic_read(APIC_DFR);
1885                 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1886         }
1887         v = apic_read(APIC_SPIV);
1888         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1889
1890         printk(KERN_DEBUG "... APIC ISR field:\n");
1891         print_APIC_bitfield(APIC_ISR);
1892         printk(KERN_DEBUG "... APIC TMR field:\n");
1893         print_APIC_bitfield(APIC_TMR);
1894         printk(KERN_DEBUG "... APIC IRR field:\n");
1895         print_APIC_bitfield(APIC_IRR);
1896
1897         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1898                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1899                         apic_write(APIC_ESR, 0);
1900
1901                 v = apic_read(APIC_ESR);
1902                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1903         }
1904
1905         icr = apic_icr_read();
1906         printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1907         printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1908
1909         v = apic_read(APIC_LVTT);
1910         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1911
1912         if (maxlvt > 3) {                       /* PC is LVT#4. */
1913                 v = apic_read(APIC_LVTPC);
1914                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1915         }
1916         v = apic_read(APIC_LVT0);
1917         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1918         v = apic_read(APIC_LVT1);
1919         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1920
1921         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1922                 v = apic_read(APIC_LVTERR);
1923                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1924         }
1925
1926         v = apic_read(APIC_TMICT);
1927         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1928         v = apic_read(APIC_TMCCT);
1929         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1930         v = apic_read(APIC_TDCR);
1931         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1932         printk("\n");
1933 }
1934
1935 __apicdebuginit(void) print_all_local_APICs(void)
1936 {
1937         int cpu;
1938
1939         preempt_disable();
1940         for_each_online_cpu(cpu)
1941                 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1942         preempt_enable();
1943 }
1944
1945 __apicdebuginit(void) print_PIC(void)
1946 {
1947         unsigned int v;
1948         unsigned long flags;
1949
1950         if (apic_verbosity == APIC_QUIET)
1951                 return;
1952
1953         printk(KERN_DEBUG "\nprinting PIC contents\n");
1954
1955         spin_lock_irqsave(&i8259A_lock, flags);
1956
1957         v = inb(0xa1) << 8 | inb(0x21);
1958         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1959
1960         v = inb(0xa0) << 8 | inb(0x20);
1961         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1962
1963         outb(0x0b,0xa0);
1964         outb(0x0b,0x20);
1965         v = inb(0xa0) << 8 | inb(0x20);
1966         outb(0x0a,0xa0);
1967         outb(0x0a,0x20);
1968
1969         spin_unlock_irqrestore(&i8259A_lock, flags);
1970
1971         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1972
1973         v = inb(0x4d1) << 8 | inb(0x4d0);
1974         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1975 }
1976
1977 __apicdebuginit(int) print_all_ICs(void)
1978 {
1979         print_PIC();
1980         print_all_local_APICs();
1981         print_IO_APIC();
1982
1983         return 0;
1984 }
1985
1986 fs_initcall(print_all_ICs);
1987
1988
1989 /* Where if anywhere is the i8259 connect in external int mode */
1990 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1991
1992 void __init enable_IO_APIC(void)
1993 {
1994         union IO_APIC_reg_01 reg_01;
1995         int i8259_apic, i8259_pin;
1996         int apic;
1997         unsigned long flags;
1998
1999         /*
2000          * The number of IO-APIC IRQ registers (== #pins):
2001          */
2002         for (apic = 0; apic < nr_ioapics; apic++) {
2003                 spin_lock_irqsave(&ioapic_lock, flags);
2004                 reg_01.raw = io_apic_read(apic, 1);
2005                 spin_unlock_irqrestore(&ioapic_lock, flags);
2006                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
2007         }
2008         for(apic = 0; apic < nr_ioapics; apic++) {
2009                 int pin;
2010                 /* See if any of the pins is in ExtINT mode */
2011                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
2012                         struct IO_APIC_route_entry entry;
2013                         entry = ioapic_read_entry(apic, pin);
2014
2015                         /* If the interrupt line is enabled and in ExtInt mode
2016                          * I have found the pin where the i8259 is connected.
2017                          */
2018                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2019                                 ioapic_i8259.apic = apic;
2020                                 ioapic_i8259.pin  = pin;
2021                                 goto found_i8259;
2022                         }
2023                 }
2024         }
2025  found_i8259:
2026         /* Look to see what if the MP table has reported the ExtINT */
2027         /* If we could not find the appropriate pin by looking at the ioapic
2028          * the i8259 probably is not connected the ioapic but give the
2029          * mptable a chance anyway.
2030          */
2031         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
2032         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2033         /* Trust the MP table if nothing is setup in the hardware */
2034         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2035                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2036                 ioapic_i8259.pin  = i8259_pin;
2037                 ioapic_i8259.apic = i8259_apic;
2038         }
2039         /* Complain if the MP table and the hardware disagree */
2040         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2041                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2042         {
2043                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2044         }
2045
2046         /*
2047          * Do not trust the IO-APIC being empty at bootup
2048          */
2049         clear_IO_APIC();
2050 }
2051
2052 /*
2053  * Not an __init, needed by the reboot code
2054  */
2055 void disable_IO_APIC(void)
2056 {
2057         /*
2058          * Clear the IO-APIC before rebooting:
2059          */
2060         clear_IO_APIC();
2061
2062         /*
2063          * If the i8259 is routed through an IOAPIC
2064          * Put that IOAPIC in virtual wire mode
2065          * so legacy interrupts can be delivered.
2066          *
2067          * With interrupt-remapping, for now we will use virtual wire A mode,
2068          * as virtual wire B is little complex (need to configure both
2069          * IOAPIC RTE aswell as interrupt-remapping table entry).
2070          * As this gets called during crash dump, keep this simple for now.
2071          */
2072         if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2073                 struct IO_APIC_route_entry entry;
2074
2075                 memset(&entry, 0, sizeof(entry));
2076                 entry.mask            = 0; /* Enabled */
2077                 entry.trigger         = 0; /* Edge */
2078                 entry.irr             = 0;
2079                 entry.polarity        = 0; /* High */
2080                 entry.delivery_status = 0;
2081                 entry.dest_mode       = 0; /* Physical */
2082                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
2083                 entry.vector          = 0;
2084                 entry.dest            = read_apic_id();
2085
2086                 /*
2087                  * Add it to the IO-APIC irq-routing table:
2088                  */
2089                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2090         }
2091
2092         /*
2093          * Use virtual wire A mode when interrupt remapping is enabled.
2094          */
2095         disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1);
2096 }
2097
2098 #ifdef CONFIG_X86_32
2099 /*
2100  * function to set the IO-APIC physical IDs based on the
2101  * values stored in the MPC table.
2102  *
2103  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
2104  */
2105
2106 static void __init setup_ioapic_ids_from_mpc(void)
2107 {
2108         union IO_APIC_reg_00 reg_00;
2109         physid_mask_t phys_id_present_map;
2110         int apic_id;
2111         int i;
2112         unsigned char old_id;
2113         unsigned long flags;
2114
2115         if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2116                 return;
2117
2118         /*
2119          * Don't check I/O APIC IDs for xAPIC systems.  They have
2120          * no meaning without the serial APIC bus.
2121          */
2122         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2123                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2124                 return;
2125         /*
2126          * This is broken; anything with a real cpu count has to
2127          * circumvent this idiocy regardless.
2128          */
2129         phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2130
2131         /*
2132          * Set the IOAPIC ID to the value stored in the MPC table.
2133          */
2134         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2135
2136                 /* Read the register 0 value */
2137                 spin_lock_irqsave(&ioapic_lock, flags);
2138                 reg_00.raw = io_apic_read(apic_id, 0);
2139                 spin_unlock_irqrestore(&ioapic_lock, flags);
2140
2141                 old_id = mp_ioapics[apic_id].apicid;
2142
2143                 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2144                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2145                                 apic_id, mp_ioapics[apic_id].apicid);
2146                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2147                                 reg_00.bits.ID);
2148                         mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2149                 }
2150
2151                 /*
2152                  * Sanity check, is the ID really free? Every APIC in a
2153                  * system must have a unique ID or we get lots of nice
2154                  * 'stuck on smp_invalidate_needed IPI wait' messages.
2155                  */
2156                 if (apic->check_apicid_used(phys_id_present_map,
2157                                         mp_ioapics[apic_id].apicid)) {
2158                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2159                                 apic_id, mp_ioapics[apic_id].apicid);
2160                         for (i = 0; i < get_physical_broadcast(); i++)
2161                                 if (!physid_isset(i, phys_id_present_map))
2162                                         break;
2163                         if (i >= get_physical_broadcast())
2164                                 panic("Max APIC ID exceeded!\n");
2165                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2166                                 i);
2167                         physid_set(i, phys_id_present_map);
2168                         mp_ioapics[apic_id].apicid = i;
2169                 } else {
2170                         physid_mask_t tmp;
2171                         tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2172                         apic_printk(APIC_VERBOSE, "Setting %d in the "
2173                                         "phys_id_present_map\n",
2174                                         mp_ioapics[apic_id].apicid);
2175                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
2176                 }
2177
2178
2179                 /*
2180                  * We need to adjust the IRQ routing table
2181                  * if the ID changed.
2182                  */
2183                 if (old_id != mp_ioapics[apic_id].apicid)
2184                         for (i = 0; i < mp_irq_entries; i++)
2185                                 if (mp_irqs[i].dstapic == old_id)
2186                                         mp_irqs[i].dstapic
2187                                                 = mp_ioapics[apic_id].apicid;
2188
2189                 /*
2190                  * Read the right value from the MPC table and
2191                  * write it into the ID register.
2192                  */
2193                 apic_printk(APIC_VERBOSE, KERN_INFO
2194                         "...changing IO-APIC physical APIC ID to %d ...",
2195                         mp_ioapics[apic_id].apicid);
2196
2197                 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2198                 spin_lock_irqsave(&ioapic_lock, flags);
2199                 io_apic_write(apic_id, 0, reg_00.raw);
2200                 spin_unlock_irqrestore(&ioapic_lock, flags);
2201
2202                 /*
2203                  * Sanity check
2204                  */
2205                 spin_lock_irqsave(&ioapic_lock, flags);
2206                 reg_00.raw = io_apic_read(apic_id, 0);
2207                 spin_unlock_irqrestore(&ioapic_lock, flags);
2208                 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2209                         printk("could not set ID!\n");
2210                 else
2211                         apic_printk(APIC_VERBOSE, " ok.\n");
2212         }
2213 }
2214 #endif
2215
2216 int no_timer_check __initdata;
2217
2218 static int __init notimercheck(char *s)
2219 {
2220         no_timer_check = 1;
2221         return 1;
2222 }
2223 __setup("no_timer_check", notimercheck);
2224
2225 /*
2226  * There is a nasty bug in some older SMP boards, their mptable lies
2227  * about the timer IRQ. We do the following to work around the situation:
2228  *
2229  *      - timer IRQ defaults to IO-APIC IRQ
2230  *      - if this function detects that timer IRQs are defunct, then we fall
2231  *        back to ISA timer IRQs
2232  */
2233 static int __init timer_irq_works(void)
2234 {
2235         unsigned long t1 = jiffies;
2236         unsigned long flags;
2237
2238         if (no_timer_check)
2239                 return 1;
2240
2241         local_save_flags(flags);
2242         local_irq_enable();
2243         /* Let ten ticks pass... */
2244         mdelay((10 * 1000) / HZ);
2245         local_irq_restore(flags);
2246
2247         /*
2248          * Expect a few ticks at least, to be sure some possible
2249          * glue logic does not lock up after one or two first
2250          * ticks in a non-ExtINT mode.  Also the local APIC
2251          * might have cached one ExtINT interrupt.  Finally, at
2252          * least one tick may be lost due to delays.
2253          */
2254
2255         /* jiffies wrap? */
2256         if (time_after(jiffies, t1 + 4))
2257                 return 1;
2258         return 0;
2259 }
2260
2261 /*
2262  * In the SMP+IOAPIC case it might happen that there are an unspecified
2263  * number of pending IRQ events unhandled. These cases are very rare,
2264  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2265  * better to do it this way as thus we do not have to be aware of
2266  * 'pending' interrupts in the IRQ path, except at this point.
2267  */
2268 /*
2269  * Edge triggered needs to resend any interrupt
2270  * that was delayed but this is now handled in the device
2271  * independent code.
2272  */
2273
2274 /*
2275  * Starting up a edge-triggered IO-APIC interrupt is
2276  * nasty - we need to make sure that we get the edge.
2277  * If it is already asserted for some reason, we need
2278  * return 1 to indicate that is was pending.
2279  *
2280  * This is not complete - we should be able to fake
2281  * an edge even if it isn't on the 8259A...
2282  */
2283
2284 static unsigned int startup_ioapic_irq(unsigned int irq)
2285 {
2286         int was_pending = 0;
2287         unsigned long flags;
2288         struct irq_cfg *cfg;
2289
2290         spin_lock_irqsave(&ioapic_lock, flags);
2291         if (irq < NR_IRQS_LEGACY) {
2292                 disable_8259A_irq(irq);
2293                 if (i8259A_irq_pending(irq))
2294                         was_pending = 1;
2295         }
2296         cfg = irq_cfg(irq);
2297         __unmask_IO_APIC_irq(cfg);
2298         spin_unlock_irqrestore(&ioapic_lock, flags);
2299
2300         return was_pending;
2301 }
2302
2303 #ifdef CONFIG_X86_64
2304 static int ioapic_retrigger_irq(unsigned int irq)
2305 {
2306
2307         struct irq_cfg *cfg = irq_cfg(irq);
2308         unsigned long flags;
2309
2310         spin_lock_irqsave(&vector_lock, flags);
2311         apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2312         spin_unlock_irqrestore(&vector_lock, flags);
2313
2314         return 1;
2315 }
2316 #else
2317 static int ioapic_retrigger_irq(unsigned int irq)
2318 {
2319         apic->send_IPI_self(irq_cfg(irq)->vector);
2320
2321         return 1;
2322 }
2323 #endif
2324
2325 /*
2326  * Level and edge triggered IO-APIC interrupts need different handling,
2327  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2328  * handled with the level-triggered descriptor, but that one has slightly
2329  * more overhead. Level-triggered interrupts cannot be handled with the
2330  * edge-triggered handler, without risking IRQ storms and other ugly
2331  * races.
2332  */
2333
2334 #ifdef CONFIG_SMP
2335
2336 #ifdef CONFIG_INTR_REMAP
2337
2338 /*
2339  * Migrate the IO-APIC irq in the presence of intr-remapping.
2340  *
2341  * For both level and edge triggered, irq migration is a simple atomic
2342  * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2343  *
2344  * For level triggered, we eliminate the io-apic RTE modification (with the
2345  * updated vector information), by using a virtual vector (io-apic pin number).
2346  * Real vector that is used for interrupting cpu will be coming from
2347  * the interrupt-remapping table entry.
2348  */
2349 static void
2350 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2351 {
2352         struct irq_cfg *cfg;
2353         struct irte irte;
2354         unsigned int dest;
2355         unsigned int irq;
2356
2357         if (!cpumask_intersects(mask, cpu_online_mask))
2358                 return;
2359
2360         irq = desc->irq;
2361         if (get_irte(irq, &irte))
2362                 return;
2363
2364         cfg = desc->chip_data;
2365         if (assign_irq_vector(irq, cfg, mask))
2366                 return;
2367
2368         set_extra_move_desc(desc, mask);
2369
2370         dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2371
2372         irte.vector = cfg->vector;
2373         irte.dest_id = IRTE_DEST(dest);
2374
2375         /*
2376          * Modified the IRTE and flushes the Interrupt entry cache.
2377          */
2378         modify_irte(irq, &irte);
2379
2380         if (cfg->move_in_progress)
2381                 send_cleanup_vector(cfg);
2382
2383         cpumask_copy(desc->affinity, mask);
2384 }
2385
2386 /*
2387  * Migrates the IRQ destination in the process context.
2388  */
2389 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2390                                             const struct cpumask *mask)
2391 {
2392         migrate_ioapic_irq_desc(desc, mask);
2393 }
2394 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2395                                        const struct cpumask *mask)
2396 {
2397         struct irq_desc *desc = irq_to_desc(irq);
2398
2399         set_ir_ioapic_affinity_irq_desc(desc, mask);
2400 }
2401 #else
2402 static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2403                                                    const struct cpumask *mask)
2404 {
2405 }
2406 #endif
2407
2408 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2409 {
2410         unsigned vector, me;
2411
2412         ack_APIC_irq();
2413         exit_idle();
2414         irq_enter();
2415
2416         me = smp_processor_id();
2417         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2418                 unsigned int irq;
2419                 unsigned int irr;
2420                 struct irq_desc *desc;
2421                 struct irq_cfg *cfg;
2422                 irq = __get_cpu_var(vector_irq)[vector];
2423
2424                 if (irq == -1)
2425                         continue;
2426
2427                 desc = irq_to_desc(irq);
2428                 if (!desc)
2429                         continue;
2430
2431                 cfg = irq_cfg(irq);
2432                 spin_lock(&desc->lock);
2433                 if (!cfg->move_cleanup_count)
2434                         goto unlock;
2435
2436                 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2437                         goto unlock;
2438
2439                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2440                 /*
2441                  * Check if the vector that needs to be cleanedup is
2442                  * registered at the cpu's IRR. If so, then this is not
2443                  * the best time to clean it up. Lets clean it up in the
2444                  * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2445                  * to myself.
2446                  */
2447                 if (irr  & (1 << (vector % 32))) {
2448                         apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2449                         goto unlock;
2450                 }
2451                 __get_cpu_var(vector_irq)[vector] = -1;
2452                 cfg->move_cleanup_count--;
2453 unlock:
2454                 spin_unlock(&desc->lock);
2455         }
2456
2457         irq_exit();
2458 }
2459
2460 static void irq_complete_move(struct irq_desc **descp)
2461 {
2462         struct irq_desc *desc = *descp;
2463         struct irq_cfg *cfg = desc->chip_data;
2464         unsigned vector, me;
2465
2466         if (likely(!cfg->move_in_progress)) {
2467 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2468                 if (likely(!cfg->move_desc_pending))
2469                         return;
2470
2471                 /* domain has not changed, but affinity did */
2472                 me = smp_processor_id();
2473                 if (cpumask_test_cpu(me, desc->affinity)) {
2474                         *descp = desc = move_irq_desc(desc, me);
2475                         /* get the new one */
2476                         cfg = desc->chip_data;
2477                         cfg->move_desc_pending = 0;
2478                 }
2479 #endif
2480                 return;
2481         }
2482
2483         vector = ~get_irq_regs()->orig_ax;
2484         me = smp_processor_id();
2485
2486         if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) {
2487 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2488                 *descp = desc = move_irq_desc(desc, me);
2489                 /* get the new one */
2490                 cfg = desc->chip_data;
2491 #endif
2492                 send_cleanup_vector(cfg);
2493         }
2494 }
2495 #else
2496 static inline void irq_complete_move(struct irq_desc **descp) {}
2497 #endif
2498
2499 #ifdef CONFIG_INTR_REMAP
2500 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2501 {
2502         int apic, pin;
2503         struct irq_pin_list *entry;
2504
2505         entry = cfg->irq_2_pin;
2506         for (;;) {
2507
2508                 if (!entry)
2509                         break;
2510
2511                 apic = entry->apic;
2512                 pin = entry->pin;
2513                 io_apic_eoi(apic, pin);
2514                 entry = entry->next;
2515         }
2516 }
2517
2518 static void
2519 eoi_ioapic_irq(struct irq_desc *desc)
2520 {
2521         struct irq_cfg *cfg;
2522         unsigned long flags;
2523         unsigned int irq;
2524
2525         irq = desc->irq;
2526         cfg = desc->chip_data;
2527
2528         spin_lock_irqsave(&ioapic_lock, flags);
2529         __eoi_ioapic_irq(irq, cfg);
2530         spin_unlock_irqrestore(&ioapic_lock, flags);
2531 }
2532
2533 static void ack_x2apic_level(unsigned int irq)
2534 {
2535         struct irq_desc *desc = irq_to_desc(irq);
2536         ack_x2APIC_irq();
2537         eoi_ioapic_irq(desc);
2538 }
2539
2540 static void ack_x2apic_edge(unsigned int irq)
2541 {
2542         ack_x2APIC_irq();
2543 }
2544
2545 #endif
2546
2547 static void ack_apic_edge(unsigned int irq)
2548 {
2549         struct irq_desc *desc = irq_to_desc(irq);
2550
2551         irq_complete_move(&desc);
2552         move_native_irq(irq);
2553         ack_APIC_irq();
2554 }
2555
2556 atomic_t irq_mis_count;
2557
2558 static void ack_apic_level(unsigned int irq)
2559 {
2560         struct irq_desc *desc = irq_to_desc(irq);
2561
2562 #ifdef CONFIG_X86_32
2563         unsigned long v;
2564         int i;
2565 #endif
2566         struct irq_cfg *cfg;
2567         int do_unmask_irq = 0;
2568
2569         irq_complete_move(&desc);
2570 #ifdef CONFIG_GENERIC_PENDING_IRQ
2571         /* If we are moving the irq we need to mask it */
2572         if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2573                 do_unmask_irq = 1;
2574                 mask_IO_APIC_irq_desc(desc);
2575         }
2576 #endif
2577
2578 #ifdef CONFIG_X86_32
2579         /*
2580         * It appears there is an erratum which affects at least version 0x11
2581         * of I/O APIC (that's the 82093AA and cores integrated into various
2582         * chipsets).  Under certain conditions a level-triggered interrupt is
2583         * erroneously delivered as edge-triggered one but the respective IRR
2584         * bit gets set nevertheless.  As a result the I/O unit expects an EOI
2585         * message but it will never arrive and further interrupts are blocked
2586         * from the source.  The exact reason is so far unknown, but the
2587         * phenomenon was observed when two consecutive interrupt requests
2588         * from a given source get delivered to the same CPU and the source is
2589         * temporarily disabled in between.
2590         *
2591         * A workaround is to simulate an EOI message manually.  We achieve it
2592         * by setting the trigger mode to edge and then to level when the edge
2593         * trigger mode gets detected in the TMR of a local APIC for a
2594         * level-triggered interrupt.  We mask the source for the time of the
2595         * operation to prevent an edge-triggered interrupt escaping meanwhile.
2596         * The idea is from Manfred Spraul.  --macro
2597         */
2598         cfg = desc->chip_data;
2599         i = cfg->vector;
2600
2601         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2602 #endif
2603
2604         /*
2605          * We must acknowledge the irq before we move it or the acknowledge will
2606          * not propagate properly.
2607          */
2608         ack_APIC_irq();
2609
2610         /* Now we can move and renable the irq */
2611         if (unlikely(do_unmask_irq)) {
2612                 /* Only migrate the irq if the ack has been received.
2613                  *
2614                  * On rare occasions the broadcast level triggered ack gets
2615                  * delayed going to ioapics, and if we reprogram the
2616                  * vector while Remote IRR is still set the irq will never
2617                  * fire again.
2618                  *
2619                  * To prevent this scenario we read the Remote IRR bit
2620                  * of the ioapic.  This has two effects.
2621                  * - On any sane system the read of the ioapic will
2622                  *   flush writes (and acks) going to the ioapic from
2623                  *   this cpu.
2624                  * - We get to see if the ACK has actually been delivered.
2625                  *
2626                  * Based on failed experiments of reprogramming the
2627                  * ioapic entry from outside of irq context starting
2628                  * with masking the ioapic entry and then polling until
2629                  * Remote IRR was clear before reprogramming the
2630                  * ioapic I don't trust the Remote IRR bit to be
2631                  * completey accurate.
2632                  *
2633                  * However there appears to be no other way to plug
2634                  * this race, so if the Remote IRR bit is not
2635                  * accurate and is causing problems then it is a hardware bug
2636                  * and you can go talk to the chipset vendor about it.
2637                  */
2638                 cfg = desc->chip_data;
2639                 if (!io_apic_level_ack_pending(cfg))
2640                         move_masked_irq(irq);
2641                 unmask_IO_APIC_irq_desc(desc);
2642         }
2643
2644 #ifdef CONFIG_X86_32
2645         if (!(v & (1 << (i & 0x1f)))) {
2646                 atomic_inc(&irq_mis_count);
2647                 spin_lock(&ioapic_lock);
2648                 __mask_and_edge_IO_APIC_irq(cfg);
2649                 __unmask_and_level_IO_APIC_irq(cfg);
2650                 spin_unlock(&ioapic_lock);
2651         }
2652 #endif
2653 }
2654
2655 static struct irq_chip ioapic_chip __read_mostly = {
2656         .name           = "IO-APIC",
2657         .startup        = startup_ioapic_irq,
2658         .mask           = mask_IO_APIC_irq,
2659         .unmask         = unmask_IO_APIC_irq,
2660         .ack            = ack_apic_edge,
2661         .eoi            = ack_apic_level,
2662 #ifdef CONFIG_SMP
2663         .set_affinity   = set_ioapic_affinity_irq,
2664 #endif
2665         .retrigger      = ioapic_retrigger_irq,
2666 };
2667
2668 #ifdef CONFIG_INTR_REMAP
2669 static struct irq_chip ir_ioapic_chip __read_mostly = {
2670         .name           = "IR-IO-APIC",
2671         .startup        = startup_ioapic_irq,
2672         .mask           = mask_IO_APIC_irq,
2673         .unmask         = unmask_IO_APIC_irq,
2674         .ack            = ack_x2apic_edge,
2675         .eoi            = ack_x2apic_level,
2676 #ifdef CONFIG_SMP
2677         .set_affinity   = set_ir_ioapic_affinity_irq,
2678 #endif
2679         .retrigger      = ioapic_retrigger_irq,
2680 };
2681 #endif
2682
2683 static inline void init_IO_APIC_traps(void)
2684 {
2685         int irq;
2686         struct irq_desc *desc;
2687         struct irq_cfg *cfg;
2688
2689         /*
2690          * NOTE! The local APIC isn't very good at handling
2691          * multiple interrupts at the same interrupt level.
2692          * As the interrupt level is determined by taking the
2693          * vector number and shifting that right by 4, we
2694          * want to spread these out a bit so that they don't
2695          * all fall in the same interrupt level.
2696          *
2697          * Also, we've got to be careful not to trash gate
2698          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2699          */
2700         for_each_irq_desc(irq, desc) {
2701                 cfg = desc->chip_data;
2702                 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2703                         /*
2704                          * Hmm.. We don't have an entry for this,
2705                          * so default to an old-fashioned 8259
2706                          * interrupt if we can..
2707                          */
2708                         if (irq < NR_IRQS_LEGACY)
2709                                 make_8259A_irq(irq);
2710                         else
2711                                 /* Strange. Oh, well.. */
2712                                 desc->chip = &no_irq_chip;
2713                 }
2714         }
2715 }
2716
2717 /*
2718  * The local APIC irq-chip implementation:
2719  */
2720
2721 static void mask_lapic_irq(unsigned int irq)
2722 {
2723         unsigned long v;
2724
2725         v = apic_read(APIC_LVT0);
2726         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2727 }
2728
2729 static void unmask_lapic_irq(unsigned int irq)
2730 {
2731         unsigned long v;
2732
2733         v = apic_read(APIC_LVT0);
2734         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2735 }
2736
2737 static void ack_lapic_irq(unsigned int irq)
2738 {
2739         ack_APIC_irq();
2740 }
2741
2742 static struct irq_chip lapic_chip __read_mostly = {
2743         .name           = "local-APIC",
2744         .mask           = mask_lapic_irq,
2745         .unmask         = unmask_lapic_irq,
2746         .ack            = ack_lapic_irq,
2747 };
2748
2749 static void lapic_register_intr(int irq, struct irq_desc *desc)
2750 {
2751         desc->status &= ~IRQ_LEVEL;
2752         set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2753                                       "edge");
2754 }
2755
2756 static void __init setup_nmi(void)
2757 {
2758         /*
2759          * Dirty trick to enable the NMI watchdog ...
2760          * We put the 8259A master into AEOI mode and
2761          * unmask on all local APICs LVT0 as NMI.
2762          *
2763          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2764          * is from Maciej W. Rozycki - so we do not have to EOI from
2765          * the NMI handler or the timer interrupt.
2766          */
2767         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2768
2769         enable_NMI_through_LVT0();
2770
2771         apic_printk(APIC_VERBOSE, " done.\n");
2772 }
2773
2774 /*
2775  * This looks a bit hackish but it's about the only one way of sending
2776  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2777  * not support the ExtINT mode, unfortunately.  We need to send these
2778  * cycles as some i82489DX-based boards have glue logic that keeps the
2779  * 8259A interrupt line asserted until INTA.  --macro
2780  */
2781 static inline void __init unlock_ExtINT_logic(void)
2782 {
2783         int apic, pin, i;
2784         struct IO_APIC_route_entry entry0, entry1;
2785         unsigned char save_control, save_freq_select;
2786
2787         pin  = find_isa_irq_pin(8, mp_INT);
2788         if (pin == -1) {
2789                 WARN_ON_ONCE(1);
2790                 return;
2791         }
2792         apic = find_isa_irq_apic(8, mp_INT);
2793         if (apic == -1) {
2794                 WARN_ON_ONCE(1);
2795                 return;
2796         }
2797
2798         entry0 = ioapic_read_entry(apic, pin);
2799         clear_IO_APIC_pin(apic, pin);
2800
2801         memset(&entry1, 0, sizeof(entry1));
2802
2803         entry1.dest_mode = 0;                   /* physical delivery */
2804         entry1.mask = 0;                        /* unmask IRQ now */
2805         entry1.dest = hard_smp_processor_id();
2806         entry1.delivery_mode = dest_ExtINT;
2807         entry1.polarity = entry0.polarity;
2808         entry1.trigger = 0;
2809         entry1.vector = 0;
2810
2811         ioapic_write_entry(apic, pin, entry1);
2812
2813         save_control = CMOS_READ(RTC_CONTROL);
2814         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2815         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2816                    RTC_FREQ_SELECT);
2817         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2818
2819         i = 100;
2820         while (i-- > 0) {
2821                 mdelay(10);
2822                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2823                         i -= 10;
2824         }
2825
2826         CMOS_WRITE(save_control, RTC_CONTROL);
2827         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2828         clear_IO_APIC_pin(apic, pin);
2829
2830         ioapic_write_entry(apic, pin, entry0);
2831 }
2832
2833 static int disable_timer_pin_1 __initdata;
2834 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2835 static int __init disable_timer_pin_setup(char *arg)
2836 {
2837         disable_timer_pin_1 = 1;
2838         return 0;
2839 }
2840 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2841
2842 int timer_through_8259 __initdata;
2843
2844 /*
2845  * This code may look a bit paranoid, but it's supposed to cooperate with
2846  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2847  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2848  * fanatically on his truly buggy board.
2849  *
2850  * FIXME: really need to revamp this for all platforms.
2851  */
2852 static inline void __init check_timer(void)
2853 {
2854         struct irq_desc *desc = irq_to_desc(0);
2855         struct irq_cfg *cfg = desc->chip_data;
2856         int cpu = boot_cpu_id;
2857         int apic1, pin1, apic2, pin2;
2858         unsigned long flags;
2859         int no_pin1 = 0;
2860
2861         local_irq_save(flags);
2862
2863         /*
2864          * get/set the timer IRQ vector:
2865          */
2866         disable_8259A_irq(0);
2867         assign_irq_vector(0, cfg, apic->target_cpus());
2868
2869         /*
2870          * As IRQ0 is to be enabled in the 8259A, the virtual
2871          * wire has to be disabled in the local APIC.  Also
2872          * timer interrupts need to be acknowledged manually in
2873          * the 8259A for the i82489DX when using the NMI
2874          * watchdog as that APIC treats NMIs as level-triggered.
2875          * The AEOI mode will finish them in the 8259A
2876          * automatically.
2877          */
2878         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2879         init_8259A(1);
2880 #ifdef CONFIG_X86_32
2881         {
2882                 unsigned int ver;
2883
2884                 ver = apic_read(APIC_LVR);
2885                 ver = GET_APIC_VERSION(ver);
2886                 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2887         }
2888 #endif
2889
2890         pin1  = find_isa_irq_pin(0, mp_INT);
2891         apic1 = find_isa_irq_apic(0, mp_INT);
2892         pin2  = ioapic_i8259.pin;
2893         apic2 = ioapic_i8259.apic;
2894
2895         apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2896                     "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2897                     cfg->vector, apic1, pin1, apic2, pin2);
2898
2899         /*
2900          * Some BIOS writers are clueless and report the ExtINTA
2901          * I/O APIC input from the cascaded 8259A as the timer
2902          * interrupt input.  So just in case, if only one pin
2903          * was found above, try it both directly and through the
2904          * 8259A.
2905          */
2906         if (pin1 == -1) {
2907                 if (intr_remapping_enabled)
2908                         panic("BIOS bug: timer not connected to IO-APIC");
2909                 pin1 = pin2;
2910                 apic1 = apic2;
2911                 no_pin1 = 1;
2912         } else if (pin2 == -1) {
2913                 pin2 = pin1;
2914                 apic2 = apic1;
2915         }
2916
2917         if (pin1 != -1) {
2918                 /*
2919                  * Ok, does IRQ0 through the IOAPIC work?
2920                  */
2921                 if (no_pin1) {
2922                         add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2923                         setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2924                 } else {
2925                         /* for edge trigger, setup_IO_APIC_irq already
2926                          * leave it unmasked.
2927                          * so only need to unmask if it is level-trigger
2928                          * do we really have level trigger timer?
2929                          */
2930                         int idx;
2931                         idx = find_irq_entry(apic1, pin1, mp_INT);
2932                         if (idx != -1 && irq_trigger(idx))
2933                                 unmask_IO_APIC_irq_desc(desc);
2934                 }
2935                 if (timer_irq_works()) {
2936                         if (nmi_watchdog == NMI_IO_APIC) {
2937                                 setup_nmi();
2938                                 enable_8259A_irq(0);
2939                         }
2940                         if (disable_timer_pin_1 > 0)
2941                                 clear_IO_APIC_pin(0, pin1);
2942                         goto out;
2943                 }
2944                 if (intr_remapping_enabled)
2945                         panic("timer doesn't work through Interrupt-remapped IO-APIC");
2946                 local_irq_disable();
2947                 clear_IO_APIC_pin(apic1, pin1);
2948                 if (!no_pin1)
2949                         apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2950                                     "8254 timer not connected to IO-APIC\n");
2951
2952                 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2953                             "(IRQ0) through the 8259A ...\n");
2954                 apic_printk(APIC_QUIET, KERN_INFO
2955                             "..... (found apic %d pin %d) ...\n", apic2, pin2);
2956                 /*
2957                  * legacy devices should be connected to IO APIC #0
2958                  */
2959                 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2960                 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2961                 enable_8259A_irq(0);
2962                 if (timer_irq_works()) {
2963                         apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2964                         timer_through_8259 = 1;
2965                         if (nmi_watchdog == NMI_IO_APIC) {
2966                                 disable_8259A_irq(0);
2967                                 setup_nmi();
2968                                 enable_8259A_irq(0);
2969                         }
2970                         goto out;
2971                 }
2972                 /*
2973                  * Cleanup, just in case ...
2974                  */
2975                 local_irq_disable();
2976                 disable_8259A_irq(0);
2977                 clear_IO_APIC_pin(apic2, pin2);
2978                 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2979         }
2980
2981         if (nmi_watchdog == NMI_IO_APIC) {
2982                 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2983                             "through the IO-APIC - disabling NMI Watchdog!\n");
2984                 nmi_watchdog = NMI_NONE;
2985         }
2986 #ifdef CONFIG_X86_32
2987         timer_ack = 0;
2988 #endif
2989
2990         apic_printk(APIC_QUIET, KERN_INFO
2991                     "...trying to set up timer as Virtual Wire IRQ...\n");
2992
2993         lapic_register_intr(0, desc);
2994         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
2995         enable_8259A_irq(0);
2996
2997         if (timer_irq_works()) {
2998                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2999                 goto out;
3000         }
3001         local_irq_disable();
3002         disable_8259A_irq(0);
3003         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3004         apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3005
3006         apic_printk(APIC_QUIET, KERN_INFO
3007                     "...trying to set up timer as ExtINT IRQ...\n");
3008
3009         init_8259A(0);
3010         make_8259A_irq(0);
3011         apic_write(APIC_LVT0, APIC_DM_EXTINT);
3012
3013         unlock_ExtINT_logic();
3014
3015         if (timer_irq_works()) {
3016                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3017                 goto out;
3018         }
3019         local_irq_disable();
3020         apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3021         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
3022                 "report.  Then try booting with the 'noapic' option.\n");
3023 out:
3024         local_irq_restore(flags);
3025 }
3026
3027 /*
3028  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3029  * to devices.  However there may be an I/O APIC pin available for
3030  * this interrupt regardless.  The pin may be left unconnected, but
3031  * typically it will be reused as an ExtINT cascade interrupt for
3032  * the master 8259A.  In the MPS case such a pin will normally be
3033  * reported as an ExtINT interrupt in the MP table.  With ACPI
3034  * there is no provision for ExtINT interrupts, and in the absence
3035  * of an override it would be treated as an ordinary ISA I/O APIC
3036  * interrupt, that is edge-triggered and unmasked by default.  We
3037  * used to do this, but it caused problems on some systems because
3038  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3039  * the same ExtINT cascade interrupt to drive the local APIC of the
3040  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
3041  * the I/O APIC in all cases now.  No actual device should request
3042  * it anyway.  --macro
3043  */
3044 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
3045
3046 void __init setup_IO_APIC(void)
3047 {
3048
3049         /*
3050          * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3051          */
3052
3053         io_apic_irqs = ~PIC_IRQS;
3054
3055         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3056         /*
3057          * Set up IO-APIC IRQ routing.
3058          */
3059 #ifdef CONFIG_X86_32
3060         if (!acpi_ioapic)
3061                 setup_ioapic_ids_from_mpc();
3062 #endif
3063         sync_Arb_IDs();
3064         setup_IO_APIC_irqs();
3065         init_IO_APIC_traps();
3066         check_timer();
3067 }
3068
3069 /*
3070  *      Called after all the initialization is done. If we didnt find any
3071  *      APIC bugs then we can allow the modify fast path
3072  */
3073
3074 static int __init io_apic_bug_finalize(void)
3075 {
3076         if (sis_apic_bug == -1)
3077                 sis_apic_bug = 0;
3078         return 0;
3079 }
3080
3081 late_initcall(io_apic_bug_finalize);
3082
3083 struct sysfs_ioapic_data {
3084         struct sys_device dev;
3085         struct IO_APIC_route_entry entry[0];
3086 };
3087 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3088
3089 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3090 {
3091         struct IO_APIC_route_entry *entry;
3092         struct sysfs_ioapic_data *data;
3093         int i;
3094
3095         data = container_of(dev, struct sysfs_ioapic_data, dev);
3096         entry = data->entry;
3097         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3098                 *entry = ioapic_read_entry(dev->id, i);
3099
3100         return 0;
3101 }
3102
3103 static int ioapic_resume(struct sys_device *dev)
3104 {
3105         struct IO_APIC_route_entry *entry;
3106         struct sysfs_ioapic_data *data;
3107         unsigned long flags;
3108         union IO_APIC_reg_00 reg_00;
3109         int i;
3110
3111         data = container_of(dev, struct sysfs_ioapic_data, dev);
3112         entry = data->entry;
3113
3114         spin_lock_irqsave(&ioapic_lock, flags);
3115         reg_00.raw = io_apic_read(dev->id, 0);
3116         if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3117                 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3118                 io_apic_write(dev->id, 0, reg_00.raw);
3119         }
3120         spin_unlock_irqrestore(&ioapic_lock, flags);
3121         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3122                 ioapic_write_entry(dev->id, i, entry[i]);
3123
3124         return 0;
3125 }
3126
3127 static struct sysdev_class ioapic_sysdev_class = {
3128         .name = "ioapic",
3129         .suspend = ioapic_suspend,
3130         .resume = ioapic_resume,
3131 };
3132
3133 static int __init ioapic_init_sysfs(void)
3134 {
3135         struct sys_device * dev;
3136         int i, size, error;
3137
3138         error = sysdev_class_register(&ioapic_sysdev_class);
3139         if (error)
3140                 return error;
3141
3142         for (i = 0; i < nr_ioapics; i++ ) {
3143                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3144                         * sizeof(struct IO_APIC_route_entry);
3145                 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3146                 if (!mp_ioapic_data[i]) {
3147                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3148                         continue;
3149                 }
3150                 dev = &mp_ioapic_data[i]->dev;
3151                 dev->id = i;
3152                 dev->cls = &ioapic_sysdev_class;
3153                 error = sysdev_register(dev);
3154                 if (error) {
3155                         kfree(mp_ioapic_data[i]);
3156                         mp_ioapic_data[i] = NULL;
3157                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3158                         continue;
3159                 }
3160         }
3161
3162         return 0;
3163 }
3164
3165 device_initcall(ioapic_init_sysfs);
3166
3167 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3168 /*
3169  * Dynamic irq allocate and deallocation
3170  */
3171 unsigned int create_irq_nr(unsigned int irq_want)
3172 {
3173         /* Allocate an unused irq */
3174         unsigned int irq;
3175         unsigned int new;
3176         unsigned long flags;
3177         struct irq_cfg *cfg_new = NULL;
3178         int cpu = boot_cpu_id;
3179         struct irq_desc *desc_new = NULL;
3180
3181         irq = 0;
3182         if (irq_want < nr_irqs_gsi)
3183                 irq_want = nr_irqs_gsi;
3184
3185         spin_lock_irqsave(&vector_lock, flags);
3186         for (new = irq_want; new < nr_irqs; new++) {
3187                 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3188                 if (!desc_new) {
3189                         printk(KERN_INFO "can not get irq_desc for %d\n", new);
3190                         continue;
3191                 }
3192                 cfg_new = desc_new->chip_data;
3193
3194                 if (cfg_new->vector != 0)
3195                         continue;
3196                 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3197                         irq = new;
3198                 break;
3199         }
3200         spin_unlock_irqrestore(&vector_lock, flags);
3201
3202         if (irq > 0) {
3203                 dynamic_irq_init(irq);
3204                 /* restore it, in case dynamic_irq_init clear it */
3205                 if (desc_new)
3206                         desc_new->chip_data = cfg_new;
3207         }
3208         return irq;
3209 }
3210
3211 int create_irq(void)
3212 {
3213         unsigned int irq_want;
3214         int irq;
3215
3216         irq_want = nr_irqs_gsi;
3217         irq = create_irq_nr(irq_want);
3218
3219         if (irq == 0)
3220                 irq = -1;
3221
3222         return irq;
3223 }
3224
3225 void destroy_irq(unsigned int irq)
3226 {
3227         unsigned long flags;
3228         struct irq_cfg *cfg;
3229         struct irq_desc *desc;
3230
3231         /* store it, in case dynamic_irq_cleanup clear it */
3232         desc = irq_to_desc(irq);
3233         cfg = desc->chip_data;
3234         dynamic_irq_cleanup(irq);
3235         /* connect back irq_cfg */
3236         if (desc)
3237                 desc->chip_data = cfg;
3238
3239         free_irte(irq);
3240         spin_lock_irqsave(&vector_lock, flags);
3241         __clear_irq_vector(irq, cfg);
3242         spin_unlock_irqrestore(&vector_lock, flags);
3243 }
3244
3245 /*
3246  * MSI message composition
3247  */
3248 #ifdef CONFIG_PCI_MSI
3249 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3250 {
3251         struct irq_cfg *cfg;
3252         int err;
3253         unsigned dest;
3254
3255         if (disable_apic)
3256                 return -ENXIO;
3257
3258         cfg = irq_cfg(irq);
3259         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3260         if (err)
3261                 return err;
3262
3263         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3264
3265         if (irq_remapped(irq)) {
3266                 struct irte irte;
3267                 int ir_index;
3268                 u16 sub_handle;
3269
3270                 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3271                 BUG_ON(ir_index == -1);
3272
3273                 memset (&irte, 0, sizeof(irte));
3274
3275                 irte.present = 1;
3276                 irte.dst_mode = apic->irq_dest_mode;
3277                 irte.trigger_mode = 0; /* edge */
3278                 irte.dlvry_mode = apic->irq_delivery_mode;
3279                 irte.vector = cfg->vector;
3280                 irte.dest_id = IRTE_DEST(dest);
3281
3282                 modify_irte(irq, &irte);
3283
3284                 msg->address_hi = MSI_ADDR_BASE_HI;
3285                 msg->data = sub_handle;
3286                 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3287                                   MSI_ADDR_IR_SHV |
3288                                   MSI_ADDR_IR_INDEX1(ir_index) |
3289                                   MSI_ADDR_IR_INDEX2(ir_index);
3290         } else {
3291                 if (x2apic_enabled())
3292                         msg->address_hi = MSI_ADDR_BASE_HI |
3293                                           MSI_ADDR_EXT_DEST_ID(dest);
3294                 else
3295                         msg->address_hi = MSI_ADDR_BASE_HI;
3296
3297                 msg->address_lo =
3298                         MSI_ADDR_BASE_LO |
3299                         ((apic->irq_dest_mode == 0) ?
3300                                 MSI_ADDR_DEST_MODE_PHYSICAL:
3301                                 MSI_ADDR_DEST_MODE_LOGICAL) |
3302                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3303                                 MSI_ADDR_REDIRECTION_CPU:
3304                                 MSI_ADDR_REDIRECTION_LOWPRI) |
3305                         MSI_ADDR_DEST_ID(dest);
3306
3307                 msg->data =
3308                         MSI_DATA_TRIGGER_EDGE |
3309                         MSI_DATA_LEVEL_ASSERT |
3310                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3311                                 MSI_DATA_DELIVERY_FIXED:
3312                                 MSI_DATA_DELIVERY_LOWPRI) |
3313                         MSI_DATA_VECTOR(cfg->vector);
3314         }
3315         return err;
3316 }
3317
3318 #ifdef CONFIG_SMP
3319 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3320 {
3321         struct irq_desc *desc = irq_to_desc(irq);
3322         struct irq_cfg *cfg;
3323         struct msi_msg msg;
3324         unsigned int dest;
3325
3326         dest = set_desc_affinity(desc, mask);
3327         if (dest == BAD_APICID)
3328                 return;
3329
3330         cfg = desc->chip_data;
3331
3332         read_msi_msg_desc(desc, &msg);
3333
3334         msg.data &= ~MSI_DATA_VECTOR_MASK;
3335         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3336         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3337         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3338
3339         write_msi_msg_desc(desc, &msg);
3340 }
3341 #ifdef CONFIG_INTR_REMAP
3342 /*
3343  * Migrate the MSI irq to another cpumask. This migration is
3344  * done in the process context using interrupt-remapping hardware.
3345  */
3346 static void
3347 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3348 {
3349         struct irq_desc *desc = irq_to_desc(irq);
3350         struct irq_cfg *cfg = desc->chip_data;
3351         unsigned int dest;
3352         struct irte irte;
3353
3354         if (get_irte(irq, &irte))
3355                 return;
3356
3357         dest = set_desc_affinity(desc, mask);
3358         if (dest == BAD_APICID)
3359                 return;
3360
3361         irte.vector = cfg->vector;
3362         irte.dest_id = IRTE_DEST(dest);
3363
3364         /*
3365          * atomically update the IRTE with the new destination and vector.
3366          */
3367         modify_irte(irq, &irte);
3368
3369         /*
3370          * After this point, all the interrupts will start arriving
3371          * at the new destination. So, time to cleanup the previous
3372          * vector allocation.
3373          */
3374         if (cfg->move_in_progress)
3375                 send_cleanup_vector(cfg);
3376 }
3377
3378 #endif
3379 #endif /* CONFIG_SMP */
3380
3381 /*
3382  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3383  * which implement the MSI or MSI-X Capability Structure.
3384  */
3385 static struct irq_chip msi_chip = {
3386         .name           = "PCI-MSI",
3387         .unmask         = unmask_msi_irq,
3388         .mask           = mask_msi_irq,
3389         .ack            = ack_apic_edge,
3390 #ifdef CONFIG_SMP
3391         .set_affinity   = set_msi_irq_affinity,
3392 #endif
3393         .retrigger      = ioapic_retrigger_irq,
3394 };
3395
3396 #ifdef CONFIG_INTR_REMAP
3397 static struct irq_chip msi_ir_chip = {
3398         .name           = "IR-PCI-MSI",
3399         .unmask         = unmask_msi_irq,
3400         .mask           = mask_msi_irq,
3401         .ack            = ack_x2apic_edge,
3402 #ifdef CONFIG_SMP
3403         .set_affinity   = ir_set_msi_irq_affinity,
3404 #endif
3405         .retrigger      = ioapic_retrigger_irq,
3406 };
3407 #endif
3408
3409 /*
3410  * Map the PCI dev to the corresponding remapping hardware unit
3411  * and allocate 'nvec' consecutive interrupt-remapping table entries
3412  * in it.
3413  */
3414 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3415 {
3416         struct intel_iommu *iommu;
3417         int index;
3418
3419         iommu = map_dev_to_ir(dev);
3420         if (!iommu) {
3421                 printk(KERN_ERR
3422                        "Unable to map PCI %s to iommu\n", pci_name(dev));
3423                 return -ENOENT;
3424         }
3425
3426         index = alloc_irte(iommu, irq, nvec);
3427         if (index < 0) {
3428                 printk(KERN_ERR
3429                        "Unable to allocate %d IRTE for PCI %s\n", nvec,
3430                        pci_name(dev));
3431                 return -ENOSPC;
3432         }
3433         return index;
3434 }
3435
3436 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3437 {
3438         int ret;
3439         struct msi_msg msg;
3440
3441         ret = msi_compose_msg(dev, irq, &msg);
3442         if (ret < 0)
3443                 return ret;
3444
3445         set_irq_msi(irq, msidesc);
3446         write_msi_msg(irq, &msg);
3447
3448         if (irq_remapped(irq)) {
3449                 struct irq_desc *desc = irq_to_desc(irq);
3450                 /*
3451                  * irq migration in process context
3452                  */
3453                 desc->status |= IRQ_MOVE_PCNTXT;
3454                 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3455         } else
3456                 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3457
3458         dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3459
3460         return 0;
3461 }
3462
3463 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3464 {
3465         unsigned int irq;
3466         int ret, sub_handle;
3467         struct msi_desc *msidesc;
3468         unsigned int irq_want;
3469         struct intel_iommu *iommu = NULL;
3470         int index = 0;
3471
3472         irq_want = nr_irqs_gsi;
3473         sub_handle = 0;
3474         list_for_each_entry(msidesc, &dev->msi_list, list) {
3475                 irq = create_irq_nr(irq_want);
3476                 if (irq == 0)
3477                         return -1;
3478                 irq_want = irq + 1;
3479                 if (!intr_remapping_enabled)
3480                         goto no_ir;
3481
3482                 if (!sub_handle) {
3483                         /*
3484                          * allocate the consecutive block of IRTE's
3485                          * for 'nvec'
3486                          */
3487                         index = msi_alloc_irte(dev, irq, nvec);
3488                         if (index < 0) {
3489                                 ret = index;
3490                                 goto error;
3491                         }
3492                 } else {
3493                         iommu = map_dev_to_ir(dev);
3494                         if (!iommu) {
3495                                 ret = -ENOENT;
3496                                 goto error;
3497                         }
3498                         /*
3499                          * setup the mapping between the irq and the IRTE
3500                          * base index, the sub_handle pointing to the
3501                          * appropriate interrupt remap table entry.
3502                          */
3503                         set_irte_irq(irq, iommu, index, sub_handle);
3504                 }
3505 no_ir:
3506                 ret = setup_msi_irq(dev, msidesc, irq);
3507                 if (ret < 0)
3508                         goto error;
3509                 sub_handle++;
3510         }
3511         return 0;
3512
3513 error:
3514         destroy_irq(irq);
3515         return ret;
3516 }
3517
3518 void arch_teardown_msi_irq(unsigned int irq)
3519 {
3520         destroy_irq(irq);
3521 }
3522
3523 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3524 #ifdef CONFIG_SMP
3525 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3526 {
3527         struct irq_desc *desc = irq_to_desc(irq);
3528         struct irq_cfg *cfg;
3529         struct msi_msg msg;
3530         unsigned int dest;
3531
3532         dest = set_desc_affinity(desc, mask);
3533         if (dest == BAD_APICID)
3534                 return;
3535
3536         cfg = desc->chip_data;
3537
3538         dmar_msi_read(irq, &msg);
3539
3540         msg.data &= ~MSI_DATA_VECTOR_MASK;
3541         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3542         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3543         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3544
3545         dmar_msi_write(irq, &msg);
3546 }
3547
3548 #endif /* CONFIG_SMP */
3549
3550 struct irq_chip dmar_msi_type = {
3551         .name = "DMAR_MSI",
3552         .unmask = dmar_msi_unmask,
3553         .mask = dmar_msi_mask,
3554         .ack = ack_apic_edge,
3555 #ifdef CONFIG_SMP
3556         .set_affinity = dmar_msi_set_affinity,
3557 #endif
3558         .retrigger = ioapic_retrigger_irq,
3559 };
3560
3561 int arch_setup_dmar_msi(unsigned int irq)
3562 {
3563         int ret;
3564         struct msi_msg msg;
3565
3566         ret = msi_compose_msg(NULL, irq, &msg);
3567         if (ret < 0)
3568                 return ret;
3569         dmar_msi_write(irq, &msg);
3570         set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3571                 "edge");
3572         return 0;
3573 }
3574 #endif
3575
3576 #ifdef CONFIG_HPET_TIMER
3577
3578 #ifdef CONFIG_SMP
3579 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3580 {
3581         struct irq_desc *desc = irq_to_desc(irq);
3582         struct irq_cfg *cfg;
3583         struct msi_msg msg;
3584         unsigned int dest;
3585
3586         dest = set_desc_affinity(desc, mask);
3587         if (dest == BAD_APICID)
3588                 return;
3589
3590         cfg = desc->chip_data;
3591
3592         hpet_msi_read(irq, &msg);
3593
3594         msg.data &= ~MSI_DATA_VECTOR_MASK;
3595         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3596         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3597         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3598
3599         hpet_msi_write(irq, &msg);
3600 }
3601
3602 #endif /* CONFIG_SMP */
3603
3604 static struct irq_chip hpet_msi_type = {
3605         .name = "HPET_MSI",
3606         .unmask = hpet_msi_unmask,
3607         .mask = hpet_msi_mask,
3608         .ack = ack_apic_edge,
3609 #ifdef CONFIG_SMP
3610         .set_affinity = hpet_msi_set_affinity,
3611 #endif
3612         .retrigger = ioapic_retrigger_irq,
3613 };
3614
3615 int arch_setup_hpet_msi(unsigned int irq)
3616 {
3617         int ret;
3618         struct msi_msg msg;
3619
3620         ret = msi_compose_msg(NULL, irq, &msg);
3621         if (ret < 0)
3622                 return ret;
3623
3624         hpet_msi_write(irq, &msg);
3625         set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3626                 "edge");
3627
3628         return 0;
3629 }
3630 #endif
3631
3632 #endif /* CONFIG_PCI_MSI */
3633 /*
3634  * Hypertransport interrupt support
3635  */
3636 #ifdef CONFIG_HT_IRQ
3637
3638 #ifdef CONFIG_SMP
3639
3640 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3641 {
3642         struct ht_irq_msg msg;
3643         fetch_ht_irq_msg(irq, &msg);
3644
3645         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3646         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3647
3648         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3649         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3650
3651         write_ht_irq_msg(irq, &msg);
3652 }
3653
3654 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3655 {
3656         struct irq_desc *desc = irq_to_desc(irq);
3657         struct irq_cfg *cfg;
3658         unsigned int dest;
3659
3660         dest = set_desc_affinity(desc, mask);
3661         if (dest == BAD_APICID)
3662                 return;
3663
3664         cfg = desc->chip_data;
3665
3666         target_ht_irq(irq, dest, cfg->vector);
3667 }
3668
3669 #endif
3670
3671 static struct irq_chip ht_irq_chip = {
3672         .name           = "PCI-HT",
3673         .mask           = mask_ht_irq,
3674         .unmask         = unmask_ht_irq,
3675         .ack            = ack_apic_edge,
3676 #ifdef CONFIG_SMP
3677         .set_affinity   = set_ht_irq_affinity,
3678 #endif
3679         .retrigger      = ioapic_retrigger_irq,
3680 };
3681
3682 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3683 {
3684         struct irq_cfg *cfg;
3685         int err;
3686
3687         if (disable_apic)
3688                 return -ENXIO;
3689
3690         cfg = irq_cfg(irq);
3691         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3692         if (!err) {
3693                 struct ht_irq_msg msg;
3694                 unsigned dest;
3695
3696                 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3697                                                     apic->target_cpus());
3698
3699                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3700
3701                 msg.address_lo =
3702                         HT_IRQ_LOW_BASE |
3703                         HT_IRQ_LOW_DEST_ID(dest) |
3704                         HT_IRQ_LOW_VECTOR(cfg->vector) |
3705                         ((apic->irq_dest_mode == 0) ?
3706                                 HT_IRQ_LOW_DM_PHYSICAL :
3707                                 HT_IRQ_LOW_DM_LOGICAL) |
3708                         HT_IRQ_LOW_RQEOI_EDGE |
3709                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3710                                 HT_IRQ_LOW_MT_FIXED :
3711                                 HT_IRQ_LOW_MT_ARBITRATED) |
3712                         HT_IRQ_LOW_IRQ_MASKED;
3713
3714                 write_ht_irq_msg(irq, &msg);
3715
3716                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3717                                               handle_edge_irq, "edge");
3718
3719                 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3720         }
3721         return err;
3722 }
3723 #endif /* CONFIG_HT_IRQ */
3724
3725 #ifdef CONFIG_X86_UV
3726 /*
3727  * Re-target the irq to the specified CPU and enable the specified MMR located
3728  * on the specified blade to allow the sending of MSIs to the specified CPU.
3729  */
3730 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3731                        unsigned long mmr_offset)
3732 {
3733         const struct cpumask *eligible_cpu = cpumask_of(cpu);
3734         struct irq_cfg *cfg;
3735         int mmr_pnode;
3736         unsigned long mmr_value;
3737         struct uv_IO_APIC_route_entry *entry;
3738         unsigned long flags;
3739         int err;
3740
3741         cfg = irq_cfg(irq);
3742
3743         err = assign_irq_vector(irq, cfg, eligible_cpu);
3744         if (err != 0)
3745                 return err;
3746
3747         spin_lock_irqsave(&vector_lock, flags);
3748         set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3749                                       irq_name);
3750         spin_unlock_irqrestore(&vector_lock, flags);
3751
3752         mmr_value = 0;
3753         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3754         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3755
3756         entry->vector = cfg->vector;
3757         entry->delivery_mode = apic->irq_delivery_mode;
3758         entry->dest_mode = apic->irq_dest_mode;
3759         entry->polarity = 0;
3760         entry->trigger = 0;
3761         entry->mask = 0;
3762         entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3763
3764         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3765         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3766
3767         return irq;
3768 }
3769
3770 /*
3771  * Disable the specified MMR located on the specified blade so that MSIs are
3772  * longer allowed to be sent.
3773  */
3774 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3775 {
3776         unsigned long mmr_value;
3777         struct uv_IO_APIC_route_entry *entry;
3778         int mmr_pnode;
3779
3780         mmr_value = 0;
3781         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3782         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3783
3784         entry->mask = 1;
3785
3786         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3787         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3788 }
3789 #endif /* CONFIG_X86_64 */
3790
3791 int __init io_apic_get_redir_entries (int ioapic)
3792 {
3793         union IO_APIC_reg_01    reg_01;
3794         unsigned long flags;
3795
3796         spin_lock_irqsave(&ioapic_lock, flags);
3797         reg_01.raw = io_apic_read(ioapic, 1);
3798         spin_unlock_irqrestore(&ioapic_lock, flags);
3799
3800         return reg_01.bits.entries;
3801 }
3802
3803 void __init probe_nr_irqs_gsi(void)
3804 {
3805         int nr = 0;
3806
3807         nr = acpi_probe_gsi();
3808         if (nr > nr_irqs_gsi) {
3809                 nr_irqs_gsi = nr;
3810         } else {
3811                 /* for acpi=off or acpi is not compiled in */
3812                 int idx;
3813
3814                 nr = 0;
3815                 for (idx = 0; idx < nr_ioapics; idx++)
3816                         nr += io_apic_get_redir_entries(idx) + 1;
3817
3818                 if (nr > nr_irqs_gsi)
3819                         nr_irqs_gsi = nr;
3820         }
3821
3822         printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3823 }
3824
3825 #ifdef CONFIG_SPARSE_IRQ
3826 int __init arch_probe_nr_irqs(void)
3827 {
3828         int nr;
3829
3830         if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3831                 nr_irqs = NR_VECTORS * nr_cpu_ids;
3832
3833         nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3834 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3835         /*
3836          * for MSI and HT dyn irq
3837          */
3838         nr += nr_irqs_gsi * 16;
3839 #endif
3840         if (nr < nr_irqs)
3841                 nr_irqs = nr;
3842
3843         return 0;
3844 }
3845 #endif
3846
3847 /* --------------------------------------------------------------------------
3848                           ACPI-based IOAPIC Configuration
3849    -------------------------------------------------------------------------- */
3850
3851 #ifdef CONFIG_ACPI
3852
3853 #ifdef CONFIG_X86_32
3854 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3855 {
3856         union IO_APIC_reg_00 reg_00;
3857         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3858         physid_mask_t tmp;
3859         unsigned long flags;
3860         int i = 0;
3861
3862         /*
3863          * The P4 platform supports up to 256 APIC IDs on two separate APIC
3864          * buses (one for LAPICs, one for IOAPICs), where predecessors only
3865          * supports up to 16 on one shared APIC bus.
3866          *
3867          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3868          *      advantage of new APIC bus architecture.
3869          */
3870
3871         if (physids_empty(apic_id_map))
3872                 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3873
3874         spin_lock_irqsave(&ioapic_lock, flags);
3875         reg_00.raw = io_apic_read(ioapic, 0);
3876         spin_unlock_irqrestore(&ioapic_lock, flags);
3877
3878         if (apic_id >= get_physical_broadcast()) {
3879                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3880                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
3881                 apic_id = reg_00.bits.ID;
3882         }
3883
3884         /*
3885          * Every APIC in a system must have a unique ID or we get lots of nice
3886          * 'stuck on smp_invalidate_needed IPI wait' messages.
3887          */
3888         if (apic->check_apicid_used(apic_id_map, apic_id)) {
3889
3890                 for (i = 0; i < get_physical_broadcast(); i++) {
3891                         if (!apic->check_apicid_used(apic_id_map, i))
3892                                 break;
3893                 }
3894
3895                 if (i == get_physical_broadcast())
3896                         panic("Max apic_id exceeded!\n");
3897
3898                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3899                         "trying %d\n", ioapic, apic_id, i);
3900
3901                 apic_id = i;
3902         }
3903
3904         tmp = apic->apicid_to_cpu_present(apic_id);
3905         physids_or(apic_id_map, apic_id_map, tmp);
3906
3907         if (reg_00.bits.ID != apic_id) {
3908                 reg_00.bits.ID = apic_id;
3909
3910                 spin_lock_irqsave(&ioapic_lock, flags);
3911                 io_apic_write(ioapic, 0, reg_00.raw);
3912                 reg_00.raw = io_apic_read(ioapic, 0);
3913                 spin_unlock_irqrestore(&ioapic_lock, flags);
3914
3915                 /* Sanity check */
3916                 if (reg_00.bits.ID != apic_id) {
3917                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3918                         return -1;
3919                 }
3920         }
3921
3922         apic_printk(APIC_VERBOSE, KERN_INFO
3923                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3924
3925         return apic_id;
3926 }
3927
3928 int __init io_apic_get_version(int ioapic)
3929 {
3930         union IO_APIC_reg_01    reg_01;
3931         unsigned long flags;
3932
3933         spin_lock_irqsave(&ioapic_lock, flags);
3934         reg_01.raw = io_apic_read(ioapic, 1);
3935         spin_unlock_irqrestore(&ioapic_lock, flags);
3936
3937         return reg_01.bits.version;
3938 }
3939 #endif
3940
3941 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3942 {
3943         struct irq_desc *desc;
3944         struct irq_cfg *cfg;
3945         int cpu = boot_cpu_id;
3946
3947         if (!IO_APIC_IRQ(irq)) {
3948                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3949                         ioapic);
3950                 return -EINVAL;
3951         }
3952
3953         desc = irq_to_desc_alloc_cpu(irq, cpu);
3954         if (!desc) {
3955                 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3956                 return 0;
3957         }
3958
3959         /*
3960          * IRQs < 16 are already in the irq_2_pin[] map
3961          */
3962         if (irq >= NR_IRQS_LEGACY) {
3963                 cfg = desc->chip_data;
3964                 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3965         }
3966
3967         setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3968
3969         return 0;
3970 }
3971
3972
3973 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3974 {
3975         int i;
3976
3977         if (skip_ioapic_setup)
3978                 return -1;
3979
3980         for (i = 0; i < mp_irq_entries; i++)
3981                 if (mp_irqs[i].irqtype == mp_INT &&
3982                     mp_irqs[i].srcbusirq == bus_irq)
3983                         break;
3984         if (i >= mp_irq_entries)
3985                 return -1;
3986
3987         *trigger = irq_trigger(i);
3988         *polarity = irq_polarity(i);
3989         return 0;
3990 }
3991
3992 #endif /* CONFIG_ACPI */
3993
3994 /*
3995  * This function currently is only a helper for the i386 smp boot process where
3996  * we need to reprogram the ioredtbls to cater for the cpus which have come online
3997  * so mask in all cases should simply be apic->target_cpus()
3998  */
3999 #ifdef CONFIG_SMP
4000 void __init setup_ioapic_dest(void)
4001 {
4002         int pin, ioapic, irq, irq_entry;
4003         struct irq_desc *desc;
4004         struct irq_cfg *cfg;
4005         const struct cpumask *mask;
4006
4007         if (skip_ioapic_setup == 1)
4008                 return;
4009
4010         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4011                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4012                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4013                         if (irq_entry == -1)
4014                                 continue;
4015                         irq = pin_2_irq(irq_entry, ioapic, pin);
4016
4017                         /* setup_IO_APIC_irqs could fail to get vector for some device
4018                          * when you have too many devices, because at that time only boot
4019                          * cpu is online.
4020                          */
4021                         desc = irq_to_desc(irq);
4022                         cfg = desc->chip_data;
4023                         if (!cfg->vector) {
4024                                 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4025                                                   irq_trigger(irq_entry),
4026                                                   irq_polarity(irq_entry));
4027                                 continue;
4028
4029                         }
4030
4031                         /*
4032                          * Honour affinities which have been set in early boot
4033                          */
4034                         if (desc->status &
4035                             (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4036                                 mask = desc->affinity;
4037                         else
4038                                 mask = apic->target_cpus();
4039
4040                         if (intr_remapping_enabled)
4041                                 set_ir_ioapic_affinity_irq_desc(desc, mask);
4042                         else
4043                                 set_ioapic_affinity_irq_desc(desc, mask);
4044                 }
4045
4046         }
4047 }
4048 #endif
4049
4050 #define IOAPIC_RESOURCE_NAME_SIZE 11
4051
4052 static struct resource *ioapic_resources;
4053
4054 static struct resource * __init ioapic_setup_resources(void)
4055 {
4056         unsigned long n;
4057         struct resource *res;
4058         char *mem;
4059         int i;
4060
4061         if (nr_ioapics <= 0)
4062                 return NULL;
4063
4064         n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4065         n *= nr_ioapics;
4066
4067         mem = alloc_bootmem(n);
4068         res = (void *)mem;
4069
4070         if (mem != NULL) {
4071                 mem += sizeof(struct resource) * nr_ioapics;
4072
4073                 for (i = 0; i < nr_ioapics; i++) {
4074                         res[i].name = mem;
4075                         res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4076                         sprintf(mem,  "IOAPIC %u", i);
4077                         mem += IOAPIC_RESOURCE_NAME_SIZE;
4078                 }
4079         }
4080
4081         ioapic_resources = res;
4082
4083         return res;
4084 }
4085
4086 void __init ioapic_init_mappings(void)
4087 {
4088         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4089         struct resource *ioapic_res;
4090         int i;
4091
4092         ioapic_res = ioapic_setup_resources();
4093         for (i = 0; i < nr_ioapics; i++) {
4094                 if (smp_found_config) {
4095                         ioapic_phys = mp_ioapics[i].apicaddr;
4096 #ifdef CONFIG_X86_32
4097                         if (!ioapic_phys) {
4098                                 printk(KERN_ERR
4099                                        "WARNING: bogus zero IO-APIC "
4100                                        "address found in MPTABLE, "
4101                                        "disabling IO/APIC support!\n");
4102                                 smp_found_config = 0;
4103                                 skip_ioapic_setup = 1;
4104                                 goto fake_ioapic_page;
4105                         }
4106 #endif
4107                 } else {
4108 #ifdef CONFIG_X86_32
4109 fake_ioapic_page:
4110 #endif
4111                         ioapic_phys = (unsigned long)
4112                                 alloc_bootmem_pages(PAGE_SIZE);
4113                         ioapic_phys = __pa(ioapic_phys);
4114                 }
4115                 set_fixmap_nocache(idx, ioapic_phys);
4116                 apic_printk(APIC_VERBOSE,
4117                             "mapped IOAPIC to %08lx (%08lx)\n",
4118                             __fix_to_virt(idx), ioapic_phys);
4119                 idx++;
4120
4121                 if (ioapic_res != NULL) {
4122                         ioapic_res->start = ioapic_phys;
4123                         ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4124                         ioapic_res++;
4125                 }
4126         }
4127 }
4128
4129 static int __init ioapic_insert_resources(void)
4130 {
4131         int i;
4132         struct resource *r = ioapic_resources;
4133
4134         if (!r) {
4135                 if (nr_ioapics > 0) {
4136                         printk(KERN_ERR
4137                                 "IO APIC resources couldn't be allocated.\n");
4138                         return -1;
4139                 }
4140                 return 0;
4141         }
4142
4143         for (i = 0; i < nr_ioapics; i++) {
4144                 insert_resource(&iomem_resource, r);
4145                 r++;
4146         }
4147
4148         return 0;
4149 }
4150
4151 /* Insert the IO APIC resources after PCI initialization has occured to handle
4152  * IO APICS that are mapped in on a BAR in PCI space. */
4153 late_initcall(ioapic_insert_resources);