2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
51 #include <asm/proto.h>
54 #include <asm/timer.h>
55 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_SPINLOCK(ioapic_lock);
77 static DEFINE_SPINLOCK(vector_lock);
80 * # of IRQ routing registers
82 int nr_ioapic_registers[MAX_IO_APICS];
84 /* I/O APIC entries */
85 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
88 /* IO APIC gsi routing info */
89 struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
91 /* MP IRQ source entries */
92 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
94 /* # of MP IRQ source entries */
98 static int nr_irqs_gsi = NR_IRQS_LEGACY;
100 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
101 int mp_bus_id_to_type[MAX_MP_BUSSES];
104 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
106 int skip_ioapic_setup;
108 void arch_disable_smp_support(void)
112 noioapicreroute = -1;
114 skip_ioapic_setup = 1;
117 static int __init parse_noapic(char *str)
119 /* disable IO-APIC */
120 arch_disable_smp_support();
123 early_param("noapic", parse_noapic);
125 struct irq_pin_list {
127 struct irq_pin_list *next;
130 static struct irq_pin_list *get_one_free_irq_2_pin(int node)
132 struct irq_pin_list *pin;
134 pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
139 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
140 #ifdef CONFIG_SPARSE_IRQ
141 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
143 static struct irq_cfg irq_cfgx[NR_IRQS];
146 int __init arch_early_irq_init(void)
149 struct irq_desc *desc;
154 if (!legacy_pic->nr_legacy_irqs) {
160 count = ARRAY_SIZE(irq_cfgx);
161 node= cpu_to_node(boot_cpu_id);
163 for (i = 0; i < count; i++) {
164 if (i < legacy_pic->nr_legacy_irqs)
165 cfg[i].vector = IRQ0_VECTOR + i;
166 desc = irq_to_desc(i);
167 desc->chip_data = &cfg[i];
168 zalloc_cpumask_var_node(&cfg[i].domain, GFP_NOWAIT, node);
169 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_NOWAIT, node);
170 if (i < legacy_pic->nr_legacy_irqs)
171 cpumask_setall(cfg[i].domain);
177 #ifdef CONFIG_SPARSE_IRQ
178 struct irq_cfg *irq_cfg(unsigned int irq)
180 struct irq_cfg *cfg = NULL;
181 struct irq_desc *desc;
183 desc = irq_to_desc(irq);
185 cfg = desc->chip_data;
190 static struct irq_cfg *get_one_free_irq_cfg(int node)
194 cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
196 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
199 } else if (!zalloc_cpumask_var_node(&cfg->old_domain,
201 free_cpumask_var(cfg->domain);
210 int arch_init_chip_data(struct irq_desc *desc, int node)
214 cfg = desc->chip_data;
216 desc->chip_data = get_one_free_irq_cfg(node);
217 if (!desc->chip_data) {
218 printk(KERN_ERR "can not alloc irq_cfg\n");
226 /* for move_irq_desc */
228 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int node)
230 struct irq_pin_list *old_entry, *head, *tail, *entry;
232 cfg->irq_2_pin = NULL;
233 old_entry = old_cfg->irq_2_pin;
237 entry = get_one_free_irq_2_pin(node);
241 entry->apic = old_entry->apic;
242 entry->pin = old_entry->pin;
245 old_entry = old_entry->next;
247 entry = get_one_free_irq_2_pin(node);
255 /* still use the old one */
258 entry->apic = old_entry->apic;
259 entry->pin = old_entry->pin;
262 old_entry = old_entry->next;
266 cfg->irq_2_pin = head;
269 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
271 struct irq_pin_list *entry, *next;
273 if (old_cfg->irq_2_pin == cfg->irq_2_pin)
276 entry = old_cfg->irq_2_pin;
283 old_cfg->irq_2_pin = NULL;
286 void arch_init_copy_chip_data(struct irq_desc *old_desc,
287 struct irq_desc *desc, int node)
290 struct irq_cfg *old_cfg;
292 cfg = get_one_free_irq_cfg(node);
297 desc->chip_data = cfg;
299 old_cfg = old_desc->chip_data;
301 memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
303 init_copy_irq_2_pin(old_cfg, cfg, node);
306 static void free_irq_cfg(struct irq_cfg *old_cfg)
311 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
313 struct irq_cfg *old_cfg, *cfg;
315 old_cfg = old_desc->chip_data;
316 cfg = desc->chip_data;
322 free_irq_2_pin(old_cfg, cfg);
323 free_irq_cfg(old_cfg);
324 old_desc->chip_data = NULL;
327 /* end for move_irq_desc */
330 struct irq_cfg *irq_cfg(unsigned int irq)
332 return irq < nr_irqs ? irq_cfgx + irq : NULL;
339 unsigned int unused[3];
341 unsigned int unused2[11];
345 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
347 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
348 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
351 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
353 struct io_apic __iomem *io_apic = io_apic_base(apic);
354 writel(vector, &io_apic->eoi);
357 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
359 struct io_apic __iomem *io_apic = io_apic_base(apic);
360 writel(reg, &io_apic->index);
361 return readl(&io_apic->data);
364 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
366 struct io_apic __iomem *io_apic = io_apic_base(apic);
367 writel(reg, &io_apic->index);
368 writel(value, &io_apic->data);
372 * Re-write a value: to be used for read-modify-write
373 * cycles where the read already set up the index register.
375 * Older SiS APIC requires we rewrite the index register
377 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
379 struct io_apic __iomem *io_apic = io_apic_base(apic);
382 writel(reg, &io_apic->index);
383 writel(value, &io_apic->data);
386 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
388 struct irq_pin_list *entry;
391 spin_lock_irqsave(&ioapic_lock, flags);
392 for_each_irq_pin(entry, cfg->irq_2_pin) {
397 reg = io_apic_read(entry->apic, 0x10 + pin*2);
398 /* Is the remote IRR bit set? */
399 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
400 spin_unlock_irqrestore(&ioapic_lock, flags);
404 spin_unlock_irqrestore(&ioapic_lock, flags);
410 struct { u32 w1, w2; };
411 struct IO_APIC_route_entry entry;
414 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
416 union entry_union eu;
418 spin_lock_irqsave(&ioapic_lock, flags);
419 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
420 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
421 spin_unlock_irqrestore(&ioapic_lock, flags);
426 * When we write a new IO APIC routing entry, we need to write the high
427 * word first! If the mask bit in the low word is clear, we will enable
428 * the interrupt, and we need to make sure the entry is fully populated
429 * before that happens.
432 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
434 union entry_union eu = {{0, 0}};
437 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
438 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
441 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
444 spin_lock_irqsave(&ioapic_lock, flags);
445 __ioapic_write_entry(apic, pin, e);
446 spin_unlock_irqrestore(&ioapic_lock, flags);
450 * When we mask an IO APIC routing entry, we need to write the low
451 * word first, in order to set the mask bit before we change the
454 static void ioapic_mask_entry(int apic, int pin)
457 union entry_union eu = { .entry.mask = 1 };
459 spin_lock_irqsave(&ioapic_lock, flags);
460 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
461 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
462 spin_unlock_irqrestore(&ioapic_lock, flags);
466 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
467 * shared ISA-space IRQs, so we have to support them. We are super
468 * fast in the common case, and fast for shared ISA-space IRQs.
471 add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin)
473 struct irq_pin_list **last, *entry;
475 /* don't allow duplicates */
476 last = &cfg->irq_2_pin;
477 for_each_irq_pin(entry, cfg->irq_2_pin) {
478 if (entry->apic == apic && entry->pin == pin)
483 entry = get_one_free_irq_2_pin(node);
485 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
496 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
498 if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin))
499 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
503 * Reroute an IRQ to a different pin.
505 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
506 int oldapic, int oldpin,
507 int newapic, int newpin)
509 struct irq_pin_list *entry;
511 for_each_irq_pin(entry, cfg->irq_2_pin) {
512 if (entry->apic == oldapic && entry->pin == oldpin) {
513 entry->apic = newapic;
515 /* every one is different, right? */
520 /* old apic/pin didn't exist, so just add new ones */
521 add_pin_to_irq_node(cfg, node, newapic, newpin);
524 static void __io_apic_modify_irq(struct irq_pin_list *entry,
525 int mask_and, int mask_or,
526 void (*final)(struct irq_pin_list *entry))
528 unsigned int reg, pin;
531 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
534 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
539 static void io_apic_modify_irq(struct irq_cfg *cfg,
540 int mask_and, int mask_or,
541 void (*final)(struct irq_pin_list *entry))
543 struct irq_pin_list *entry;
545 for_each_irq_pin(entry, cfg->irq_2_pin)
546 __io_apic_modify_irq(entry, mask_and, mask_or, final);
549 static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry)
551 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER,
552 IO_APIC_REDIR_MASKED, NULL);
555 static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry)
557 __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED,
558 IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
561 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
563 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
566 static void io_apic_sync(struct irq_pin_list *entry)
569 * Synchronize the IO-APIC and the CPU by doing
570 * a dummy read from the IO-APIC
572 struct io_apic __iomem *io_apic;
573 io_apic = io_apic_base(entry->apic);
574 readl(&io_apic->data);
577 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
579 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
582 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
584 struct irq_cfg *cfg = desc->chip_data;
589 spin_lock_irqsave(&ioapic_lock, flags);
590 __mask_IO_APIC_irq(cfg);
591 spin_unlock_irqrestore(&ioapic_lock, flags);
594 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
596 struct irq_cfg *cfg = desc->chip_data;
599 spin_lock_irqsave(&ioapic_lock, flags);
600 __unmask_IO_APIC_irq(cfg);
601 spin_unlock_irqrestore(&ioapic_lock, flags);
604 static void mask_IO_APIC_irq(unsigned int irq)
606 struct irq_desc *desc = irq_to_desc(irq);
608 mask_IO_APIC_irq_desc(desc);
610 static void unmask_IO_APIC_irq(unsigned int irq)
612 struct irq_desc *desc = irq_to_desc(irq);
614 unmask_IO_APIC_irq_desc(desc);
617 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
619 struct IO_APIC_route_entry entry;
621 /* Check delivery_mode to be sure we're not clearing an SMI pin */
622 entry = ioapic_read_entry(apic, pin);
623 if (entry.delivery_mode == dest_SMI)
626 * Disable it in the IO-APIC irq-routing table:
628 ioapic_mask_entry(apic, pin);
631 static void clear_IO_APIC (void)
635 for (apic = 0; apic < nr_ioapics; apic++)
636 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
637 clear_IO_APIC_pin(apic, pin);
642 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
643 * specific CPU-side IRQs.
647 static int pirq_entries[MAX_PIRQS] = {
648 [0 ... MAX_PIRQS - 1] = -1
651 static int __init ioapic_pirq_setup(char *str)
654 int ints[MAX_PIRQS+1];
656 get_options(str, ARRAY_SIZE(ints), ints);
658 apic_printk(APIC_VERBOSE, KERN_INFO
659 "PIRQ redirection, working around broken MP-BIOS.\n");
661 if (ints[0] < MAX_PIRQS)
664 for (i = 0; i < max; i++) {
665 apic_printk(APIC_VERBOSE, KERN_DEBUG
666 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
668 * PIRQs are mapped upside down, usually.
670 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
675 __setup("pirq=", ioapic_pirq_setup);
676 #endif /* CONFIG_X86_32 */
678 struct IO_APIC_route_entry **alloc_ioapic_entries(void)
681 struct IO_APIC_route_entry **ioapic_entries;
683 ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
688 for (apic = 0; apic < nr_ioapics; apic++) {
689 ioapic_entries[apic] =
690 kzalloc(sizeof(struct IO_APIC_route_entry) *
691 nr_ioapic_registers[apic], GFP_ATOMIC);
692 if (!ioapic_entries[apic])
696 return ioapic_entries;
700 kfree(ioapic_entries[apic]);
701 kfree(ioapic_entries);
707 * Saves all the IO-APIC RTE's
709 int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
716 for (apic = 0; apic < nr_ioapics; apic++) {
717 if (!ioapic_entries[apic])
720 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
721 ioapic_entries[apic][pin] =
722 ioapic_read_entry(apic, pin);
729 * Mask all IO APIC entries.
731 void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
738 for (apic = 0; apic < nr_ioapics; apic++) {
739 if (!ioapic_entries[apic])
742 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
743 struct IO_APIC_route_entry entry;
745 entry = ioapic_entries[apic][pin];
748 ioapic_write_entry(apic, pin, entry);
755 * Restore IO APIC entries which was saved in ioapic_entries.
757 int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
764 for (apic = 0; apic < nr_ioapics; apic++) {
765 if (!ioapic_entries[apic])
768 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
769 ioapic_write_entry(apic, pin,
770 ioapic_entries[apic][pin]);
775 void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
779 for (apic = 0; apic < nr_ioapics; apic++)
780 kfree(ioapic_entries[apic]);
782 kfree(ioapic_entries);
786 * Find the IRQ entry number of a certain pin.
788 static int find_irq_entry(int apic, int pin, int type)
792 for (i = 0; i < mp_irq_entries; i++)
793 if (mp_irqs[i].irqtype == type &&
794 (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
795 mp_irqs[i].dstapic == MP_APIC_ALL) &&
796 mp_irqs[i].dstirq == pin)
803 * Find the pin to which IRQ[irq] (ISA) is connected
805 static int __init find_isa_irq_pin(int irq, int type)
809 for (i = 0; i < mp_irq_entries; i++) {
810 int lbus = mp_irqs[i].srcbus;
812 if (test_bit(lbus, mp_bus_not_pci) &&
813 (mp_irqs[i].irqtype == type) &&
814 (mp_irqs[i].srcbusirq == irq))
816 return mp_irqs[i].dstirq;
821 static int __init find_isa_irq_apic(int irq, int type)
825 for (i = 0; i < mp_irq_entries; i++) {
826 int lbus = mp_irqs[i].srcbus;
828 if (test_bit(lbus, mp_bus_not_pci) &&
829 (mp_irqs[i].irqtype == type) &&
830 (mp_irqs[i].srcbusirq == irq))
833 if (i < mp_irq_entries) {
835 for(apic = 0; apic < nr_ioapics; apic++) {
836 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
844 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
846 * EISA Edge/Level control register, ELCR
848 static int EISA_ELCR(unsigned int irq)
850 if (irq < legacy_pic->nr_legacy_irqs) {
851 unsigned int port = 0x4d0 + (irq >> 3);
852 return (inb(port) >> (irq & 7)) & 1;
854 apic_printk(APIC_VERBOSE, KERN_INFO
855 "Broken MPtable reports ISA irq %d\n", irq);
861 /* ISA interrupts are always polarity zero edge triggered,
862 * when listed as conforming in the MP table. */
864 #define default_ISA_trigger(idx) (0)
865 #define default_ISA_polarity(idx) (0)
867 /* EISA interrupts are always polarity zero and can be edge or level
868 * trigger depending on the ELCR value. If an interrupt is listed as
869 * EISA conforming in the MP table, that means its trigger type must
870 * be read in from the ELCR */
872 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
873 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
875 /* PCI interrupts are always polarity one level triggered,
876 * when listed as conforming in the MP table. */
878 #define default_PCI_trigger(idx) (1)
879 #define default_PCI_polarity(idx) (1)
881 /* MCA interrupts are always polarity zero level triggered,
882 * when listed as conforming in the MP table. */
884 #define default_MCA_trigger(idx) (1)
885 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
887 static int MPBIOS_polarity(int idx)
889 int bus = mp_irqs[idx].srcbus;
893 * Determine IRQ line polarity (high active or low active):
895 switch (mp_irqs[idx].irqflag & 3)
897 case 0: /* conforms, ie. bus-type dependent polarity */
898 if (test_bit(bus, mp_bus_not_pci))
899 polarity = default_ISA_polarity(idx);
901 polarity = default_PCI_polarity(idx);
903 case 1: /* high active */
908 case 2: /* reserved */
910 printk(KERN_WARNING "broken BIOS!!\n");
914 case 3: /* low active */
919 default: /* invalid */
921 printk(KERN_WARNING "broken BIOS!!\n");
929 static int MPBIOS_trigger(int idx)
931 int bus = mp_irqs[idx].srcbus;
935 * Determine IRQ trigger mode (edge or level sensitive):
937 switch ((mp_irqs[idx].irqflag>>2) & 3)
939 case 0: /* conforms, ie. bus-type dependent */
940 if (test_bit(bus, mp_bus_not_pci))
941 trigger = default_ISA_trigger(idx);
943 trigger = default_PCI_trigger(idx);
944 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
945 switch (mp_bus_id_to_type[bus]) {
946 case MP_BUS_ISA: /* ISA pin */
948 /* set before the switch */
951 case MP_BUS_EISA: /* EISA pin */
953 trigger = default_EISA_trigger(idx);
956 case MP_BUS_PCI: /* PCI pin */
958 /* set before the switch */
961 case MP_BUS_MCA: /* MCA pin */
963 trigger = default_MCA_trigger(idx);
968 printk(KERN_WARNING "broken BIOS!!\n");
980 case 2: /* reserved */
982 printk(KERN_WARNING "broken BIOS!!\n");
991 default: /* invalid */
993 printk(KERN_WARNING "broken BIOS!!\n");
1001 static inline int irq_polarity(int idx)
1003 return MPBIOS_polarity(idx);
1006 static inline int irq_trigger(int idx)
1008 return MPBIOS_trigger(idx);
1011 int (*ioapic_renumber_irq)(int ioapic, int irq);
1012 static int pin_2_irq(int idx, int apic, int pin)
1015 int bus = mp_irqs[idx].srcbus;
1018 * Debugging check, we are in big trouble if this message pops up!
1020 if (mp_irqs[idx].dstirq != pin)
1021 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1023 if (test_bit(bus, mp_bus_not_pci)) {
1024 irq = mp_irqs[idx].srcbusirq;
1027 * PCI IRQs are mapped in order
1031 irq += nr_ioapic_registers[i++];
1034 * For MPS mode, so far only needed by ES7000 platform
1036 if (ioapic_renumber_irq)
1037 irq = ioapic_renumber_irq(apic, irq);
1040 #ifdef CONFIG_X86_32
1042 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1044 if ((pin >= 16) && (pin <= 23)) {
1045 if (pirq_entries[pin-16] != -1) {
1046 if (!pirq_entries[pin-16]) {
1047 apic_printk(APIC_VERBOSE, KERN_DEBUG
1048 "disabling PIRQ%d\n", pin-16);
1050 irq = pirq_entries[pin-16];
1051 apic_printk(APIC_VERBOSE, KERN_DEBUG
1052 "using PIRQ%d -> IRQ %d\n",
1063 * Find a specific PCI IRQ entry.
1064 * Not an __init, possibly needed by modules
1066 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1067 struct io_apic_irq_attr *irq_attr)
1069 int apic, i, best_guess = -1;
1071 apic_printk(APIC_DEBUG,
1072 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1074 if (test_bit(bus, mp_bus_not_pci)) {
1075 apic_printk(APIC_VERBOSE,
1076 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1079 for (i = 0; i < mp_irq_entries; i++) {
1080 int lbus = mp_irqs[i].srcbus;
1082 for (apic = 0; apic < nr_ioapics; apic++)
1083 if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1084 mp_irqs[i].dstapic == MP_APIC_ALL)
1087 if (!test_bit(lbus, mp_bus_not_pci) &&
1088 !mp_irqs[i].irqtype &&
1090 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1091 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1093 if (!(apic || IO_APIC_IRQ(irq)))
1096 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1097 set_io_apic_irq_attr(irq_attr, apic,
1104 * Use the first all-but-pin matching entry as a
1105 * best-guess fuzzy result for broken mptables.
1107 if (best_guess < 0) {
1108 set_io_apic_irq_attr(irq_attr, apic,
1118 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1120 void lock_vector_lock(void)
1122 /* Used to the online set of cpus does not change
1123 * during assign_irq_vector.
1125 spin_lock(&vector_lock);
1128 void unlock_vector_lock(void)
1130 spin_unlock(&vector_lock);
1134 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1137 * NOTE! The local APIC isn't very good at handling
1138 * multiple interrupts at the same interrupt level.
1139 * As the interrupt level is determined by taking the
1140 * vector number and shifting that right by 4, we
1141 * want to spread these out a bit so that they don't
1142 * all fall in the same interrupt level.
1144 * Also, we've got to be careful not to trash gate
1145 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1147 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1148 unsigned int old_vector;
1150 cpumask_var_t tmp_mask;
1152 if (cfg->move_in_progress)
1155 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1158 old_vector = cfg->vector;
1160 cpumask_and(tmp_mask, mask, cpu_online_mask);
1161 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1162 if (!cpumask_empty(tmp_mask)) {
1163 free_cpumask_var(tmp_mask);
1168 /* Only try and allocate irqs on cpus that are present */
1170 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1174 apic->vector_allocation_domain(cpu, tmp_mask);
1176 vector = current_vector;
1177 offset = current_offset;
1180 if (vector >= first_system_vector) {
1181 /* If out of vectors on large boxen, must share them. */
1182 offset = (offset + 1) % 8;
1183 vector = FIRST_DEVICE_VECTOR + offset;
1185 if (unlikely(current_vector == vector))
1188 if (test_bit(vector, used_vectors))
1191 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1192 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1195 current_vector = vector;
1196 current_offset = offset;
1198 cfg->move_in_progress = 1;
1199 cpumask_copy(cfg->old_domain, cfg->domain);
1201 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1202 per_cpu(vector_irq, new_cpu)[vector] = irq;
1203 cfg->vector = vector;
1204 cpumask_copy(cfg->domain, tmp_mask);
1208 free_cpumask_var(tmp_mask);
1212 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1215 unsigned long flags;
1217 spin_lock_irqsave(&vector_lock, flags);
1218 err = __assign_irq_vector(irq, cfg, mask);
1219 spin_unlock_irqrestore(&vector_lock, flags);
1223 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1227 BUG_ON(!cfg->vector);
1229 vector = cfg->vector;
1230 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1231 per_cpu(vector_irq, cpu)[vector] = -1;
1234 cpumask_clear(cfg->domain);
1236 if (likely(!cfg->move_in_progress))
1238 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1239 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1241 if (per_cpu(vector_irq, cpu)[vector] != irq)
1243 per_cpu(vector_irq, cpu)[vector] = -1;
1247 cfg->move_in_progress = 0;
1250 void __setup_vector_irq(int cpu)
1252 /* Initialize vector_irq on a new cpu */
1253 /* This function must be called with vector_lock held */
1255 struct irq_cfg *cfg;
1256 struct irq_desc *desc;
1258 /* Mark the inuse vectors */
1259 for_each_irq_desc(irq, desc) {
1260 cfg = desc->chip_data;
1261 if (!cpumask_test_cpu(cpu, cfg->domain))
1263 vector = cfg->vector;
1264 per_cpu(vector_irq, cpu)[vector] = irq;
1266 /* Mark the free vectors */
1267 for (vector = 0; vector < NR_VECTORS; ++vector) {
1268 irq = per_cpu(vector_irq, cpu)[vector];
1273 if (!cpumask_test_cpu(cpu, cfg->domain))
1274 per_cpu(vector_irq, cpu)[vector] = -1;
1278 static struct irq_chip ioapic_chip;
1279 static struct irq_chip ir_ioapic_chip;
1281 #define IOAPIC_AUTO -1
1282 #define IOAPIC_EDGE 0
1283 #define IOAPIC_LEVEL 1
1285 #ifdef CONFIG_X86_32
1286 static inline int IO_APIC_irq_trigger(int irq)
1290 for (apic = 0; apic < nr_ioapics; apic++) {
1291 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1292 idx = find_irq_entry(apic, pin, mp_INT);
1293 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1294 return irq_trigger(idx);
1298 * nonexistent IRQs are edge default
1303 static inline int IO_APIC_irq_trigger(int irq)
1309 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1312 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1313 trigger == IOAPIC_LEVEL)
1314 desc->status |= IRQ_LEVEL;
1316 desc->status &= ~IRQ_LEVEL;
1318 if (irq_remapped(irq)) {
1319 desc->status |= IRQ_MOVE_PCNTXT;
1321 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1325 set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1326 handle_edge_irq, "edge");
1330 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1331 trigger == IOAPIC_LEVEL)
1332 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1336 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1337 handle_edge_irq, "edge");
1340 int setup_ioapic_entry(int apic_id, int irq,
1341 struct IO_APIC_route_entry *entry,
1342 unsigned int destination, int trigger,
1343 int polarity, int vector, int pin)
1346 * add it to the IO-APIC irq-routing table:
1348 memset(entry,0,sizeof(*entry));
1350 if (intr_remapping_enabled) {
1351 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1353 struct IR_IO_APIC_route_entry *ir_entry =
1354 (struct IR_IO_APIC_route_entry *) entry;
1358 panic("No mapping iommu for ioapic %d\n", apic_id);
1360 index = alloc_irte(iommu, irq, 1);
1362 panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1364 memset(&irte, 0, sizeof(irte));
1367 irte.dst_mode = apic->irq_dest_mode;
1369 * Trigger mode in the IRTE will always be edge, and the
1370 * actual level or edge trigger will be setup in the IO-APIC
1371 * RTE. This will help simplify level triggered irq migration.
1372 * For more details, see the comments above explainig IO-APIC
1373 * irq migration in the presence of interrupt-remapping.
1375 irte.trigger_mode = 0;
1376 irte.dlvry_mode = apic->irq_delivery_mode;
1377 irte.vector = vector;
1378 irte.dest_id = IRTE_DEST(destination);
1380 /* Set source-id of interrupt request */
1381 set_ioapic_sid(&irte, apic_id);
1383 modify_irte(irq, &irte);
1385 ir_entry->index2 = (index >> 15) & 0x1;
1387 ir_entry->format = 1;
1388 ir_entry->index = (index & 0x7fff);
1390 * IO-APIC RTE will be configured with virtual vector.
1391 * irq handler will do the explicit EOI to the io-apic.
1393 ir_entry->vector = pin;
1395 entry->delivery_mode = apic->irq_delivery_mode;
1396 entry->dest_mode = apic->irq_dest_mode;
1397 entry->dest = destination;
1398 entry->vector = vector;
1401 entry->mask = 0; /* enable IRQ */
1402 entry->trigger = trigger;
1403 entry->polarity = polarity;
1405 /* Mask level triggered irqs.
1406 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1413 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1414 int trigger, int polarity)
1416 struct irq_cfg *cfg;
1417 struct IO_APIC_route_entry entry;
1420 if (!IO_APIC_IRQ(irq))
1423 cfg = desc->chip_data;
1425 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1428 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1430 apic_printk(APIC_VERBOSE,KERN_DEBUG
1431 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1432 "IRQ %d Mode:%i Active:%i)\n",
1433 apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1434 irq, trigger, polarity);
1437 if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1438 dest, trigger, polarity, cfg->vector, pin)) {
1439 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1440 mp_ioapics[apic_id].apicid, pin);
1441 __clear_irq_vector(irq, cfg);
1445 ioapic_register_intr(irq, desc, trigger);
1446 if (irq < legacy_pic->nr_legacy_irqs)
1447 legacy_pic->chip->mask(irq);
1449 ioapic_write_entry(apic_id, pin, entry);
1453 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
1454 } mp_ioapic_routing[MAX_IO_APICS];
1456 static void __init setup_IO_APIC_irqs(void)
1458 int apic_id = 0, pin, idx, irq;
1460 struct irq_desc *desc;
1461 struct irq_cfg *cfg;
1462 int node = cpu_to_node(boot_cpu_id);
1464 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1467 if (!acpi_disabled && acpi_ioapic) {
1468 apic_id = mp_find_ioapic(0);
1474 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1475 idx = find_irq_entry(apic_id, pin, mp_INT);
1479 apic_printk(APIC_VERBOSE,
1480 KERN_DEBUG " %d-%d",
1481 mp_ioapics[apic_id].apicid, pin);
1483 apic_printk(APIC_VERBOSE, " %d-%d",
1484 mp_ioapics[apic_id].apicid, pin);
1488 apic_printk(APIC_VERBOSE,
1489 " (apicid-pin) not connected\n");
1493 irq = pin_2_irq(idx, apic_id, pin);
1496 * Skip the timer IRQ if there's a quirk handler
1497 * installed and if it returns 1:
1499 if (apic->multi_timer_check &&
1500 apic->multi_timer_check(apic_id, irq))
1503 desc = irq_to_desc_alloc_node(irq, node);
1505 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1508 cfg = desc->chip_data;
1509 add_pin_to_irq_node(cfg, node, apic_id, pin);
1511 * don't mark it in pin_programmed, so later acpi could
1512 * set it correctly when irq < 16
1514 setup_IO_APIC_irq(apic_id, pin, irq, desc,
1515 irq_trigger(idx), irq_polarity(idx));
1519 apic_printk(APIC_VERBOSE,
1520 " (apicid-pin) not connected\n");
1524 * Set up the timer pin, possibly with the 8259A-master behind.
1526 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1529 struct IO_APIC_route_entry entry;
1531 if (intr_remapping_enabled)
1534 memset(&entry, 0, sizeof(entry));
1537 * We use logical delivery to get the timer IRQ
1540 entry.dest_mode = apic->irq_dest_mode;
1541 entry.mask = 0; /* don't mask IRQ for edge */
1542 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1543 entry.delivery_mode = apic->irq_delivery_mode;
1546 entry.vector = vector;
1549 * The timer IRQ doesn't have to know that behind the
1550 * scene we may have a 8259A-master in AEOI mode ...
1552 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1555 * Add it to the IO-APIC irq-routing table:
1557 ioapic_write_entry(apic_id, pin, entry);
1561 __apicdebuginit(void) print_IO_APIC(void)
1564 union IO_APIC_reg_00 reg_00;
1565 union IO_APIC_reg_01 reg_01;
1566 union IO_APIC_reg_02 reg_02;
1567 union IO_APIC_reg_03 reg_03;
1568 unsigned long flags;
1569 struct irq_cfg *cfg;
1570 struct irq_desc *desc;
1573 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1574 for (i = 0; i < nr_ioapics; i++)
1575 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1576 mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1579 * We are a bit conservative about what we expect. We have to
1580 * know about every hardware change ASAP.
1582 printk(KERN_INFO "testing the IO APIC.......................\n");
1584 for (apic = 0; apic < nr_ioapics; apic++) {
1586 spin_lock_irqsave(&ioapic_lock, flags);
1587 reg_00.raw = io_apic_read(apic, 0);
1588 reg_01.raw = io_apic_read(apic, 1);
1589 if (reg_01.bits.version >= 0x10)
1590 reg_02.raw = io_apic_read(apic, 2);
1591 if (reg_01.bits.version >= 0x20)
1592 reg_03.raw = io_apic_read(apic, 3);
1593 spin_unlock_irqrestore(&ioapic_lock, flags);
1596 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1597 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1598 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1599 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1600 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1602 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1603 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
1605 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1606 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1609 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1610 * but the value of reg_02 is read as the previous read register
1611 * value, so ignore it if reg_02 == reg_01.
1613 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1614 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1615 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1619 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1620 * or reg_03, but the value of reg_0[23] is read as the previous read
1621 * register value, so ignore it if reg_03 == reg_0[12].
1623 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1624 reg_03.raw != reg_01.raw) {
1625 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1626 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1629 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1631 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1632 " Stat Dmod Deli Vect: \n");
1634 for (i = 0; i <= reg_01.bits.entries; i++) {
1635 struct IO_APIC_route_entry entry;
1637 entry = ioapic_read_entry(apic, i);
1639 printk(KERN_DEBUG " %02x %03X ",
1644 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1649 entry.delivery_status,
1651 entry.delivery_mode,
1656 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1657 for_each_irq_desc(irq, desc) {
1658 struct irq_pin_list *entry;
1660 cfg = desc->chip_data;
1661 entry = cfg->irq_2_pin;
1664 printk(KERN_DEBUG "IRQ%d ", irq);
1665 for_each_irq_pin(entry, cfg->irq_2_pin)
1666 printk("-> %d:%d", entry->apic, entry->pin);
1670 printk(KERN_INFO ".................................... done.\n");
1675 __apicdebuginit(void) print_APIC_field(int base)
1681 for (i = 0; i < 8; i++)
1682 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1684 printk(KERN_CONT "\n");
1687 __apicdebuginit(void) print_local_APIC(void *dummy)
1689 unsigned int i, v, ver, maxlvt;
1692 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1693 smp_processor_id(), hard_smp_processor_id());
1694 v = apic_read(APIC_ID);
1695 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1696 v = apic_read(APIC_LVR);
1697 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1698 ver = GET_APIC_VERSION(v);
1699 maxlvt = lapic_get_maxlvt();
1701 v = apic_read(APIC_TASKPRI);
1702 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1704 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1705 if (!APIC_XAPIC(ver)) {
1706 v = apic_read(APIC_ARBPRI);
1707 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1708 v & APIC_ARBPRI_MASK);
1710 v = apic_read(APIC_PROCPRI);
1711 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1715 * Remote read supported only in the 82489DX and local APIC for
1716 * Pentium processors.
1718 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1719 v = apic_read(APIC_RRR);
1720 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1723 v = apic_read(APIC_LDR);
1724 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1725 if (!x2apic_enabled()) {
1726 v = apic_read(APIC_DFR);
1727 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1729 v = apic_read(APIC_SPIV);
1730 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1732 printk(KERN_DEBUG "... APIC ISR field:\n");
1733 print_APIC_field(APIC_ISR);
1734 printk(KERN_DEBUG "... APIC TMR field:\n");
1735 print_APIC_field(APIC_TMR);
1736 printk(KERN_DEBUG "... APIC IRR field:\n");
1737 print_APIC_field(APIC_IRR);
1739 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1740 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1741 apic_write(APIC_ESR, 0);
1743 v = apic_read(APIC_ESR);
1744 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1747 icr = apic_icr_read();
1748 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1749 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1751 v = apic_read(APIC_LVTT);
1752 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1754 if (maxlvt > 3) { /* PC is LVT#4. */
1755 v = apic_read(APIC_LVTPC);
1756 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1758 v = apic_read(APIC_LVT0);
1759 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1760 v = apic_read(APIC_LVT1);
1761 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1763 if (maxlvt > 2) { /* ERR is LVT#3. */
1764 v = apic_read(APIC_LVTERR);
1765 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1768 v = apic_read(APIC_TMICT);
1769 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1770 v = apic_read(APIC_TMCCT);
1771 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1772 v = apic_read(APIC_TDCR);
1773 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1775 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1776 v = apic_read(APIC_EFEAT);
1777 maxlvt = (v >> 16) & 0xff;
1778 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1779 v = apic_read(APIC_ECTRL);
1780 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1781 for (i = 0; i < maxlvt; i++) {
1782 v = apic_read(APIC_EILVTn(i));
1783 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1789 __apicdebuginit(void) print_local_APICs(int maxcpu)
1797 for_each_online_cpu(cpu) {
1800 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1805 __apicdebuginit(void) print_PIC(void)
1808 unsigned long flags;
1810 if (!legacy_pic->nr_legacy_irqs)
1813 printk(KERN_DEBUG "\nprinting PIC contents\n");
1815 spin_lock_irqsave(&i8259A_lock, flags);
1817 v = inb(0xa1) << 8 | inb(0x21);
1818 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1820 v = inb(0xa0) << 8 | inb(0x20);
1821 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1825 v = inb(0xa0) << 8 | inb(0x20);
1829 spin_unlock_irqrestore(&i8259A_lock, flags);
1831 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1833 v = inb(0x4d1) << 8 | inb(0x4d0);
1834 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1837 static int __initdata show_lapic = 1;
1838 static __init int setup_show_lapic(char *arg)
1842 if (strcmp(arg, "all") == 0) {
1843 show_lapic = CONFIG_NR_CPUS;
1845 get_option(&arg, &num);
1852 __setup("show_lapic=", setup_show_lapic);
1854 __apicdebuginit(int) print_ICs(void)
1856 if (apic_verbosity == APIC_QUIET)
1861 /* don't print out if apic is not there */
1862 if (!cpu_has_apic && !apic_from_smp_config())
1865 print_local_APICs(show_lapic);
1871 fs_initcall(print_ICs);
1874 /* Where if anywhere is the i8259 connect in external int mode */
1875 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1877 void __init enable_IO_APIC(void)
1879 union IO_APIC_reg_01 reg_01;
1880 int i8259_apic, i8259_pin;
1882 unsigned long flags;
1885 * The number of IO-APIC IRQ registers (== #pins):
1887 for (apic = 0; apic < nr_ioapics; apic++) {
1888 spin_lock_irqsave(&ioapic_lock, flags);
1889 reg_01.raw = io_apic_read(apic, 1);
1890 spin_unlock_irqrestore(&ioapic_lock, flags);
1891 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1894 if (!legacy_pic->nr_legacy_irqs)
1897 for(apic = 0; apic < nr_ioapics; apic++) {
1899 /* See if any of the pins is in ExtINT mode */
1900 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1901 struct IO_APIC_route_entry entry;
1902 entry = ioapic_read_entry(apic, pin);
1904 /* If the interrupt line is enabled and in ExtInt mode
1905 * I have found the pin where the i8259 is connected.
1907 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1908 ioapic_i8259.apic = apic;
1909 ioapic_i8259.pin = pin;
1915 /* Look to see what if the MP table has reported the ExtINT */
1916 /* If we could not find the appropriate pin by looking at the ioapic
1917 * the i8259 probably is not connected the ioapic but give the
1918 * mptable a chance anyway.
1920 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1921 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1922 /* Trust the MP table if nothing is setup in the hardware */
1923 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1924 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1925 ioapic_i8259.pin = i8259_pin;
1926 ioapic_i8259.apic = i8259_apic;
1928 /* Complain if the MP table and the hardware disagree */
1929 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1930 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1932 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1936 * Do not trust the IO-APIC being empty at bootup
1942 * Not an __init, needed by the reboot code
1944 void disable_IO_APIC(void)
1947 * Clear the IO-APIC before rebooting:
1951 if (!legacy_pic->nr_legacy_irqs)
1955 * If the i8259 is routed through an IOAPIC
1956 * Put that IOAPIC in virtual wire mode
1957 * so legacy interrupts can be delivered.
1959 * With interrupt-remapping, for now we will use virtual wire A mode,
1960 * as virtual wire B is little complex (need to configure both
1961 * IOAPIC RTE aswell as interrupt-remapping table entry).
1962 * As this gets called during crash dump, keep this simple for now.
1964 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
1965 struct IO_APIC_route_entry entry;
1967 memset(&entry, 0, sizeof(entry));
1968 entry.mask = 0; /* Enabled */
1969 entry.trigger = 0; /* Edge */
1971 entry.polarity = 0; /* High */
1972 entry.delivery_status = 0;
1973 entry.dest_mode = 0; /* Physical */
1974 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1976 entry.dest = read_apic_id();
1979 * Add it to the IO-APIC irq-routing table:
1981 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1985 * Use virtual wire A mode when interrupt remapping is enabled.
1987 if (cpu_has_apic || apic_from_smp_config())
1988 disconnect_bsp_APIC(!intr_remapping_enabled &&
1989 ioapic_i8259.pin != -1);
1992 #ifdef CONFIG_X86_32
1994 * function to set the IO-APIC physical IDs based on the
1995 * values stored in the MPC table.
1997 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2000 void __init setup_ioapic_ids_from_mpc(void)
2002 union IO_APIC_reg_00 reg_00;
2003 physid_mask_t phys_id_present_map;
2006 unsigned char old_id;
2007 unsigned long flags;
2012 * Don't check I/O APIC IDs for xAPIC systems. They have
2013 * no meaning without the serial APIC bus.
2015 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2016 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2019 * This is broken; anything with a real cpu count has to
2020 * circumvent this idiocy regardless.
2022 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2025 * Set the IOAPIC ID to the value stored in the MPC table.
2027 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2029 /* Read the register 0 value */
2030 spin_lock_irqsave(&ioapic_lock, flags);
2031 reg_00.raw = io_apic_read(apic_id, 0);
2032 spin_unlock_irqrestore(&ioapic_lock, flags);
2034 old_id = mp_ioapics[apic_id].apicid;
2036 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2037 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2038 apic_id, mp_ioapics[apic_id].apicid);
2039 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2041 mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2045 * Sanity check, is the ID really free? Every APIC in a
2046 * system must have a unique ID or we get lots of nice
2047 * 'stuck on smp_invalidate_needed IPI wait' messages.
2049 if (apic->check_apicid_used(&phys_id_present_map,
2050 mp_ioapics[apic_id].apicid)) {
2051 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2052 apic_id, mp_ioapics[apic_id].apicid);
2053 for (i = 0; i < get_physical_broadcast(); i++)
2054 if (!physid_isset(i, phys_id_present_map))
2056 if (i >= get_physical_broadcast())
2057 panic("Max APIC ID exceeded!\n");
2058 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2060 physid_set(i, phys_id_present_map);
2061 mp_ioapics[apic_id].apicid = i;
2064 apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
2065 apic_printk(APIC_VERBOSE, "Setting %d in the "
2066 "phys_id_present_map\n",
2067 mp_ioapics[apic_id].apicid);
2068 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2073 * We need to adjust the IRQ routing table
2074 * if the ID changed.
2076 if (old_id != mp_ioapics[apic_id].apicid)
2077 for (i = 0; i < mp_irq_entries; i++)
2078 if (mp_irqs[i].dstapic == old_id)
2080 = mp_ioapics[apic_id].apicid;
2083 * Read the right value from the MPC table and
2084 * write it into the ID register.
2086 apic_printk(APIC_VERBOSE, KERN_INFO
2087 "...changing IO-APIC physical APIC ID to %d ...",
2088 mp_ioapics[apic_id].apicid);
2090 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2091 spin_lock_irqsave(&ioapic_lock, flags);
2092 io_apic_write(apic_id, 0, reg_00.raw);
2093 spin_unlock_irqrestore(&ioapic_lock, flags);
2098 spin_lock_irqsave(&ioapic_lock, flags);
2099 reg_00.raw = io_apic_read(apic_id, 0);
2100 spin_unlock_irqrestore(&ioapic_lock, flags);
2101 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2102 printk("could not set ID!\n");
2104 apic_printk(APIC_VERBOSE, " ok.\n");
2109 int no_timer_check __initdata;
2111 static int __init notimercheck(char *s)
2116 __setup("no_timer_check", notimercheck);
2119 * There is a nasty bug in some older SMP boards, their mptable lies
2120 * about the timer IRQ. We do the following to work around the situation:
2122 * - timer IRQ defaults to IO-APIC IRQ
2123 * - if this function detects that timer IRQs are defunct, then we fall
2124 * back to ISA timer IRQs
2126 static int __init timer_irq_works(void)
2128 unsigned long t1 = jiffies;
2129 unsigned long flags;
2134 local_save_flags(flags);
2136 /* Let ten ticks pass... */
2137 mdelay((10 * 1000) / HZ);
2138 local_irq_restore(flags);
2141 * Expect a few ticks at least, to be sure some possible
2142 * glue logic does not lock up after one or two first
2143 * ticks in a non-ExtINT mode. Also the local APIC
2144 * might have cached one ExtINT interrupt. Finally, at
2145 * least one tick may be lost due to delays.
2149 if (time_after(jiffies, t1 + 4))
2155 * In the SMP+IOAPIC case it might happen that there are an unspecified
2156 * number of pending IRQ events unhandled. These cases are very rare,
2157 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2158 * better to do it this way as thus we do not have to be aware of
2159 * 'pending' interrupts in the IRQ path, except at this point.
2162 * Edge triggered needs to resend any interrupt
2163 * that was delayed but this is now handled in the device
2168 * Starting up a edge-triggered IO-APIC interrupt is
2169 * nasty - we need to make sure that we get the edge.
2170 * If it is already asserted for some reason, we need
2171 * return 1 to indicate that is was pending.
2173 * This is not complete - we should be able to fake
2174 * an edge even if it isn't on the 8259A...
2177 static unsigned int startup_ioapic_irq(unsigned int irq)
2179 int was_pending = 0;
2180 unsigned long flags;
2181 struct irq_cfg *cfg;
2183 spin_lock_irqsave(&ioapic_lock, flags);
2184 if (irq < legacy_pic->nr_legacy_irqs) {
2185 legacy_pic->chip->mask(irq);
2186 if (legacy_pic->irq_pending(irq))
2190 __unmask_IO_APIC_irq(cfg);
2191 spin_unlock_irqrestore(&ioapic_lock, flags);
2196 static int ioapic_retrigger_irq(unsigned int irq)
2199 struct irq_cfg *cfg = irq_cfg(irq);
2200 unsigned long flags;
2202 spin_lock_irqsave(&vector_lock, flags);
2203 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2204 spin_unlock_irqrestore(&vector_lock, flags);
2210 * Level and edge triggered IO-APIC interrupts need different handling,
2211 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2212 * handled with the level-triggered descriptor, but that one has slightly
2213 * more overhead. Level-triggered interrupts cannot be handled with the
2214 * edge-triggered handler, without risking IRQ storms and other ugly
2219 void send_cleanup_vector(struct irq_cfg *cfg)
2221 cpumask_var_t cleanup_mask;
2223 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2225 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2226 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2228 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2229 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2230 free_cpumask_var(cleanup_mask);
2232 cfg->move_in_progress = 0;
2235 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2238 struct irq_pin_list *entry;
2239 u8 vector = cfg->vector;
2241 for_each_irq_pin(entry, cfg->irq_2_pin) {
2247 * With interrupt-remapping, destination information comes
2248 * from interrupt-remapping table entry.
2250 if (!irq_remapped(irq))
2251 io_apic_write(apic, 0x11 + pin*2, dest);
2252 reg = io_apic_read(apic, 0x10 + pin*2);
2253 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2255 io_apic_modify(apic, 0x10 + pin*2, reg);
2260 * Either sets desc->affinity to a valid value, and returns
2261 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2262 * leaves desc->affinity untouched.
2265 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask,
2266 unsigned int *dest_id)
2268 struct irq_cfg *cfg;
2271 if (!cpumask_intersects(mask, cpu_online_mask))
2275 cfg = desc->chip_data;
2276 if (assign_irq_vector(irq, cfg, mask))
2279 cpumask_copy(desc->affinity, mask);
2281 *dest_id = apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
2286 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2288 struct irq_cfg *cfg;
2289 unsigned long flags;
2295 cfg = desc->chip_data;
2297 spin_lock_irqsave(&ioapic_lock, flags);
2298 ret = set_desc_affinity(desc, mask, &dest);
2300 /* Only the high 8 bits are valid. */
2301 dest = SET_APIC_LOGICAL_ID(dest);
2302 __target_IO_APIC_irq(irq, dest, cfg);
2304 spin_unlock_irqrestore(&ioapic_lock, flags);
2310 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
2312 struct irq_desc *desc;
2314 desc = irq_to_desc(irq);
2316 return set_ioapic_affinity_irq_desc(desc, mask);
2319 #ifdef CONFIG_INTR_REMAP
2322 * Migrate the IO-APIC irq in the presence of intr-remapping.
2324 * For both level and edge triggered, irq migration is a simple atomic
2325 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2327 * For level triggered, we eliminate the io-apic RTE modification (with the
2328 * updated vector information), by using a virtual vector (io-apic pin number).
2329 * Real vector that is used for interrupting cpu will be coming from
2330 * the interrupt-remapping table entry.
2333 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2335 struct irq_cfg *cfg;
2341 if (!cpumask_intersects(mask, cpu_online_mask))
2345 if (get_irte(irq, &irte))
2348 cfg = desc->chip_data;
2349 if (assign_irq_vector(irq, cfg, mask))
2352 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2354 irte.vector = cfg->vector;
2355 irte.dest_id = IRTE_DEST(dest);
2358 * Modified the IRTE and flushes the Interrupt entry cache.
2360 modify_irte(irq, &irte);
2362 if (cfg->move_in_progress)
2363 send_cleanup_vector(cfg);
2365 cpumask_copy(desc->affinity, mask);
2371 * Migrates the IRQ destination in the process context.
2373 static int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2374 const struct cpumask *mask)
2376 return migrate_ioapic_irq_desc(desc, mask);
2378 static int set_ir_ioapic_affinity_irq(unsigned int irq,
2379 const struct cpumask *mask)
2381 struct irq_desc *desc = irq_to_desc(irq);
2383 return set_ir_ioapic_affinity_irq_desc(desc, mask);
2386 static inline int set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2387 const struct cpumask *mask)
2393 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2395 unsigned vector, me;
2401 me = smp_processor_id();
2402 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2405 struct irq_desc *desc;
2406 struct irq_cfg *cfg;
2407 irq = __get_cpu_var(vector_irq)[vector];
2412 desc = irq_to_desc(irq);
2417 raw_spin_lock(&desc->lock);
2420 * Check if the irq migration is in progress. If so, we
2421 * haven't received the cleanup request yet for this irq.
2423 if (cfg->move_in_progress)
2426 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2429 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2431 * Check if the vector that needs to be cleanedup is
2432 * registered at the cpu's IRR. If so, then this is not
2433 * the best time to clean it up. Lets clean it up in the
2434 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2437 if (irr & (1 << (vector % 32))) {
2438 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2441 __get_cpu_var(vector_irq)[vector] = -1;
2443 raw_spin_unlock(&desc->lock);
2449 static void __irq_complete_move(struct irq_desc **descp, unsigned vector)
2451 struct irq_desc *desc = *descp;
2452 struct irq_cfg *cfg = desc->chip_data;
2455 if (likely(!cfg->move_in_progress))
2458 me = smp_processor_id();
2460 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2461 send_cleanup_vector(cfg);
2464 static void irq_complete_move(struct irq_desc **descp)
2466 __irq_complete_move(descp, ~get_irq_regs()->orig_ax);
2469 void irq_force_complete_move(int irq)
2471 struct irq_desc *desc = irq_to_desc(irq);
2472 struct irq_cfg *cfg = desc->chip_data;
2474 __irq_complete_move(&desc, cfg->vector);
2477 static inline void irq_complete_move(struct irq_desc **descp) {}
2480 static void ack_apic_edge(unsigned int irq)
2482 struct irq_desc *desc = irq_to_desc(irq);
2484 irq_complete_move(&desc);
2485 move_native_irq(irq);
2489 atomic_t irq_mis_count;
2492 * IO-APIC versions below 0x20 don't support EOI register.
2493 * For the record, here is the information about various versions:
2495 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
2496 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
2499 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
2500 * version as 0x2. This is an error with documentation and these ICH chips
2501 * use io-apic's of version 0x20.
2503 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
2504 * Otherwise, we simulate the EOI message manually by changing the trigger
2505 * mode to edge and then back to level, with RTE being masked during this.
2507 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2509 struct irq_pin_list *entry;
2511 for_each_irq_pin(entry, cfg->irq_2_pin) {
2512 if (mp_ioapics[entry->apic].apicver >= 0x20) {
2514 * Intr-remapping uses pin number as the virtual vector
2515 * in the RTE. Actual vector is programmed in
2516 * intr-remapping table entry. Hence for the io-apic
2517 * EOI we use the pin number.
2519 if (irq_remapped(irq))
2520 io_apic_eoi(entry->apic, entry->pin);
2522 io_apic_eoi(entry->apic, cfg->vector);
2524 __mask_and_edge_IO_APIC_irq(entry);
2525 __unmask_and_level_IO_APIC_irq(entry);
2530 static void eoi_ioapic_irq(struct irq_desc *desc)
2532 struct irq_cfg *cfg;
2533 unsigned long flags;
2537 cfg = desc->chip_data;
2539 spin_lock_irqsave(&ioapic_lock, flags);
2540 __eoi_ioapic_irq(irq, cfg);
2541 spin_unlock_irqrestore(&ioapic_lock, flags);
2544 static void ack_apic_level(unsigned int irq)
2546 struct irq_desc *desc = irq_to_desc(irq);
2549 struct irq_cfg *cfg;
2550 int do_unmask_irq = 0;
2552 irq_complete_move(&desc);
2553 #ifdef CONFIG_GENERIC_PENDING_IRQ
2554 /* If we are moving the irq we need to mask it */
2555 if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2557 mask_IO_APIC_irq_desc(desc);
2562 * It appears there is an erratum which affects at least version 0x11
2563 * of I/O APIC (that's the 82093AA and cores integrated into various
2564 * chipsets). Under certain conditions a level-triggered interrupt is
2565 * erroneously delivered as edge-triggered one but the respective IRR
2566 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2567 * message but it will never arrive and further interrupts are blocked
2568 * from the source. The exact reason is so far unknown, but the
2569 * phenomenon was observed when two consecutive interrupt requests
2570 * from a given source get delivered to the same CPU and the source is
2571 * temporarily disabled in between.
2573 * A workaround is to simulate an EOI message manually. We achieve it
2574 * by setting the trigger mode to edge and then to level when the edge
2575 * trigger mode gets detected in the TMR of a local APIC for a
2576 * level-triggered interrupt. We mask the source for the time of the
2577 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2578 * The idea is from Manfred Spraul. --macro
2580 * Also in the case when cpu goes offline, fixup_irqs() will forward
2581 * any unhandled interrupt on the offlined cpu to the new cpu
2582 * destination that is handling the corresponding interrupt. This
2583 * interrupt forwarding is done via IPI's. Hence, in this case also
2584 * level-triggered io-apic interrupt will be seen as an edge
2585 * interrupt in the IRR. And we can't rely on the cpu's EOI
2586 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2587 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2588 * supporting EOI register, we do an explicit EOI to clear the
2589 * remote IRR and on IO-APIC's which don't have an EOI register,
2590 * we use the above logic (mask+edge followed by unmask+level) from
2591 * Manfred Spraul to clear the remote IRR.
2593 cfg = desc->chip_data;
2595 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2598 * We must acknowledge the irq before we move it or the acknowledge will
2599 * not propagate properly.
2604 * Tail end of clearing remote IRR bit (either by delivering the EOI
2605 * message via io-apic EOI register write or simulating it using
2606 * mask+edge followed by unnask+level logic) manually when the
2607 * level triggered interrupt is seen as the edge triggered interrupt
2610 if (!(v & (1 << (i & 0x1f)))) {
2611 atomic_inc(&irq_mis_count);
2613 eoi_ioapic_irq(desc);
2616 /* Now we can move and renable the irq */
2617 if (unlikely(do_unmask_irq)) {
2618 /* Only migrate the irq if the ack has been received.
2620 * On rare occasions the broadcast level triggered ack gets
2621 * delayed going to ioapics, and if we reprogram the
2622 * vector while Remote IRR is still set the irq will never
2625 * To prevent this scenario we read the Remote IRR bit
2626 * of the ioapic. This has two effects.
2627 * - On any sane system the read of the ioapic will
2628 * flush writes (and acks) going to the ioapic from
2630 * - We get to see if the ACK has actually been delivered.
2632 * Based on failed experiments of reprogramming the
2633 * ioapic entry from outside of irq context starting
2634 * with masking the ioapic entry and then polling until
2635 * Remote IRR was clear before reprogramming the
2636 * ioapic I don't trust the Remote IRR bit to be
2637 * completey accurate.
2639 * However there appears to be no other way to plug
2640 * this race, so if the Remote IRR bit is not
2641 * accurate and is causing problems then it is a hardware bug
2642 * and you can go talk to the chipset vendor about it.
2644 cfg = desc->chip_data;
2645 if (!io_apic_level_ack_pending(cfg))
2646 move_masked_irq(irq);
2647 unmask_IO_APIC_irq_desc(desc);
2651 #ifdef CONFIG_INTR_REMAP
2652 static void ir_ack_apic_edge(unsigned int irq)
2657 static void ir_ack_apic_level(unsigned int irq)
2659 struct irq_desc *desc = irq_to_desc(irq);
2662 eoi_ioapic_irq(desc);
2664 #endif /* CONFIG_INTR_REMAP */
2666 static struct irq_chip ioapic_chip __read_mostly = {
2668 .startup = startup_ioapic_irq,
2669 .mask = mask_IO_APIC_irq,
2670 .unmask = unmask_IO_APIC_irq,
2671 .ack = ack_apic_edge,
2672 .eoi = ack_apic_level,
2674 .set_affinity = set_ioapic_affinity_irq,
2676 .retrigger = ioapic_retrigger_irq,
2679 static struct irq_chip ir_ioapic_chip __read_mostly = {
2680 .name = "IR-IO-APIC",
2681 .startup = startup_ioapic_irq,
2682 .mask = mask_IO_APIC_irq,
2683 .unmask = unmask_IO_APIC_irq,
2684 #ifdef CONFIG_INTR_REMAP
2685 .ack = ir_ack_apic_edge,
2686 .eoi = ir_ack_apic_level,
2688 .set_affinity = set_ir_ioapic_affinity_irq,
2691 .retrigger = ioapic_retrigger_irq,
2694 static inline void init_IO_APIC_traps(void)
2697 struct irq_desc *desc;
2698 struct irq_cfg *cfg;
2701 * NOTE! The local APIC isn't very good at handling
2702 * multiple interrupts at the same interrupt level.
2703 * As the interrupt level is determined by taking the
2704 * vector number and shifting that right by 4, we
2705 * want to spread these out a bit so that they don't
2706 * all fall in the same interrupt level.
2708 * Also, we've got to be careful not to trash gate
2709 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2711 for_each_irq_desc(irq, desc) {
2712 cfg = desc->chip_data;
2713 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2715 * Hmm.. We don't have an entry for this,
2716 * so default to an old-fashioned 8259
2717 * interrupt if we can..
2719 if (irq < legacy_pic->nr_legacy_irqs)
2720 legacy_pic->make_irq(irq);
2722 /* Strange. Oh, well.. */
2723 desc->chip = &no_irq_chip;
2729 * The local APIC irq-chip implementation:
2732 static void mask_lapic_irq(unsigned int irq)
2736 v = apic_read(APIC_LVT0);
2737 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2740 static void unmask_lapic_irq(unsigned int irq)
2744 v = apic_read(APIC_LVT0);
2745 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2748 static void ack_lapic_irq(unsigned int irq)
2753 static struct irq_chip lapic_chip __read_mostly = {
2754 .name = "local-APIC",
2755 .mask = mask_lapic_irq,
2756 .unmask = unmask_lapic_irq,
2757 .ack = ack_lapic_irq,
2760 static void lapic_register_intr(int irq, struct irq_desc *desc)
2762 desc->status &= ~IRQ_LEVEL;
2763 set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2767 static void __init setup_nmi(void)
2770 * Dirty trick to enable the NMI watchdog ...
2771 * We put the 8259A master into AEOI mode and
2772 * unmask on all local APICs LVT0 as NMI.
2774 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2775 * is from Maciej W. Rozycki - so we do not have to EOI from
2776 * the NMI handler or the timer interrupt.
2778 apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2780 enable_NMI_through_LVT0();
2782 apic_printk(APIC_VERBOSE, " done.\n");
2786 * This looks a bit hackish but it's about the only one way of sending
2787 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2788 * not support the ExtINT mode, unfortunately. We need to send these
2789 * cycles as some i82489DX-based boards have glue logic that keeps the
2790 * 8259A interrupt line asserted until INTA. --macro
2792 static inline void __init unlock_ExtINT_logic(void)
2795 struct IO_APIC_route_entry entry0, entry1;
2796 unsigned char save_control, save_freq_select;
2798 pin = find_isa_irq_pin(8, mp_INT);
2803 apic = find_isa_irq_apic(8, mp_INT);
2809 entry0 = ioapic_read_entry(apic, pin);
2810 clear_IO_APIC_pin(apic, pin);
2812 memset(&entry1, 0, sizeof(entry1));
2814 entry1.dest_mode = 0; /* physical delivery */
2815 entry1.mask = 0; /* unmask IRQ now */
2816 entry1.dest = hard_smp_processor_id();
2817 entry1.delivery_mode = dest_ExtINT;
2818 entry1.polarity = entry0.polarity;
2822 ioapic_write_entry(apic, pin, entry1);
2824 save_control = CMOS_READ(RTC_CONTROL);
2825 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2826 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2828 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2833 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2837 CMOS_WRITE(save_control, RTC_CONTROL);
2838 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2839 clear_IO_APIC_pin(apic, pin);
2841 ioapic_write_entry(apic, pin, entry0);
2844 static int disable_timer_pin_1 __initdata;
2845 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2846 static int __init disable_timer_pin_setup(char *arg)
2848 disable_timer_pin_1 = 1;
2851 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2853 int timer_through_8259 __initdata;
2856 * This code may look a bit paranoid, but it's supposed to cooperate with
2857 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2858 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2859 * fanatically on his truly buggy board.
2861 * FIXME: really need to revamp this for all platforms.
2863 static inline void __init check_timer(void)
2865 struct irq_desc *desc = irq_to_desc(0);
2866 struct irq_cfg *cfg = desc->chip_data;
2867 int node = cpu_to_node(boot_cpu_id);
2868 int apic1, pin1, apic2, pin2;
2869 unsigned long flags;
2872 local_irq_save(flags);
2875 * get/set the timer IRQ vector:
2877 legacy_pic->chip->mask(0);
2878 assign_irq_vector(0, cfg, apic->target_cpus());
2881 * As IRQ0 is to be enabled in the 8259A, the virtual
2882 * wire has to be disabled in the local APIC. Also
2883 * timer interrupts need to be acknowledged manually in
2884 * the 8259A for the i82489DX when using the NMI
2885 * watchdog as that APIC treats NMIs as level-triggered.
2886 * The AEOI mode will finish them in the 8259A
2889 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2890 legacy_pic->init(1);
2891 #ifdef CONFIG_X86_32
2895 ver = apic_read(APIC_LVR);
2896 ver = GET_APIC_VERSION(ver);
2897 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2901 pin1 = find_isa_irq_pin(0, mp_INT);
2902 apic1 = find_isa_irq_apic(0, mp_INT);
2903 pin2 = ioapic_i8259.pin;
2904 apic2 = ioapic_i8259.apic;
2906 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2907 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2908 cfg->vector, apic1, pin1, apic2, pin2);
2911 * Some BIOS writers are clueless and report the ExtINTA
2912 * I/O APIC input from the cascaded 8259A as the timer
2913 * interrupt input. So just in case, if only one pin
2914 * was found above, try it both directly and through the
2918 if (intr_remapping_enabled)
2919 panic("BIOS bug: timer not connected to IO-APIC");
2923 } else if (pin2 == -1) {
2930 * Ok, does IRQ0 through the IOAPIC work?
2933 add_pin_to_irq_node(cfg, node, apic1, pin1);
2934 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2936 /* for edge trigger, setup_IO_APIC_irq already
2937 * leave it unmasked.
2938 * so only need to unmask if it is level-trigger
2939 * do we really have level trigger timer?
2942 idx = find_irq_entry(apic1, pin1, mp_INT);
2943 if (idx != -1 && irq_trigger(idx))
2944 unmask_IO_APIC_irq_desc(desc);
2946 if (timer_irq_works()) {
2947 if (nmi_watchdog == NMI_IO_APIC) {
2949 legacy_pic->chip->unmask(0);
2951 if (disable_timer_pin_1 > 0)
2952 clear_IO_APIC_pin(0, pin1);
2955 if (intr_remapping_enabled)
2956 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2957 local_irq_disable();
2958 clear_IO_APIC_pin(apic1, pin1);
2960 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2961 "8254 timer not connected to IO-APIC\n");
2963 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2964 "(IRQ0) through the 8259A ...\n");
2965 apic_printk(APIC_QUIET, KERN_INFO
2966 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2968 * legacy devices should be connected to IO APIC #0
2970 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2971 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2972 legacy_pic->chip->unmask(0);
2973 if (timer_irq_works()) {
2974 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2975 timer_through_8259 = 1;
2976 if (nmi_watchdog == NMI_IO_APIC) {
2977 legacy_pic->chip->mask(0);
2979 legacy_pic->chip->unmask(0);
2984 * Cleanup, just in case ...
2986 local_irq_disable();
2987 legacy_pic->chip->mask(0);
2988 clear_IO_APIC_pin(apic2, pin2);
2989 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2992 if (nmi_watchdog == NMI_IO_APIC) {
2993 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2994 "through the IO-APIC - disabling NMI Watchdog!\n");
2995 nmi_watchdog = NMI_NONE;
2997 #ifdef CONFIG_X86_32
3001 apic_printk(APIC_QUIET, KERN_INFO
3002 "...trying to set up timer as Virtual Wire IRQ...\n");
3004 lapic_register_intr(0, desc);
3005 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
3006 legacy_pic->chip->unmask(0);
3008 if (timer_irq_works()) {
3009 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3012 local_irq_disable();
3013 legacy_pic->chip->mask(0);
3014 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3015 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3017 apic_printk(APIC_QUIET, KERN_INFO
3018 "...trying to set up timer as ExtINT IRQ...\n");
3020 legacy_pic->init(0);
3021 legacy_pic->make_irq(0);
3022 apic_write(APIC_LVT0, APIC_DM_EXTINT);
3024 unlock_ExtINT_logic();
3026 if (timer_irq_works()) {
3027 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3030 local_irq_disable();
3031 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3032 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3033 "report. Then try booting with the 'noapic' option.\n");
3035 local_irq_restore(flags);
3039 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3040 * to devices. However there may be an I/O APIC pin available for
3041 * this interrupt regardless. The pin may be left unconnected, but
3042 * typically it will be reused as an ExtINT cascade interrupt for
3043 * the master 8259A. In the MPS case such a pin will normally be
3044 * reported as an ExtINT interrupt in the MP table. With ACPI
3045 * there is no provision for ExtINT interrupts, and in the absence
3046 * of an override it would be treated as an ordinary ISA I/O APIC
3047 * interrupt, that is edge-triggered and unmasked by default. We
3048 * used to do this, but it caused problems on some systems because
3049 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3050 * the same ExtINT cascade interrupt to drive the local APIC of the
3051 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3052 * the I/O APIC in all cases now. No actual device should request
3053 * it anyway. --macro
3055 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
3057 void __init setup_IO_APIC(void)
3061 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3063 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
3065 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3067 * Set up IO-APIC IRQ routing.
3069 x86_init.mpparse.setup_ioapic_ids();
3072 setup_IO_APIC_irqs();
3073 init_IO_APIC_traps();
3074 if (legacy_pic->nr_legacy_irqs)
3079 * Called after all the initialization is done. If we didnt find any
3080 * APIC bugs then we can allow the modify fast path
3083 static int __init io_apic_bug_finalize(void)
3085 if (sis_apic_bug == -1)
3090 late_initcall(io_apic_bug_finalize);
3092 struct sysfs_ioapic_data {
3093 struct sys_device dev;
3094 struct IO_APIC_route_entry entry[0];
3096 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3098 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3100 struct IO_APIC_route_entry *entry;
3101 struct sysfs_ioapic_data *data;
3104 data = container_of(dev, struct sysfs_ioapic_data, dev);
3105 entry = data->entry;
3106 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3107 *entry = ioapic_read_entry(dev->id, i);
3112 static int ioapic_resume(struct sys_device *dev)
3114 struct IO_APIC_route_entry *entry;
3115 struct sysfs_ioapic_data *data;
3116 unsigned long flags;
3117 union IO_APIC_reg_00 reg_00;
3120 data = container_of(dev, struct sysfs_ioapic_data, dev);
3121 entry = data->entry;
3123 spin_lock_irqsave(&ioapic_lock, flags);
3124 reg_00.raw = io_apic_read(dev->id, 0);
3125 if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3126 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3127 io_apic_write(dev->id, 0, reg_00.raw);
3129 spin_unlock_irqrestore(&ioapic_lock, flags);
3130 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3131 ioapic_write_entry(dev->id, i, entry[i]);
3136 static struct sysdev_class ioapic_sysdev_class = {
3138 .suspend = ioapic_suspend,
3139 .resume = ioapic_resume,
3142 static int __init ioapic_init_sysfs(void)
3144 struct sys_device * dev;
3147 error = sysdev_class_register(&ioapic_sysdev_class);
3151 for (i = 0; i < nr_ioapics; i++ ) {
3152 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3153 * sizeof(struct IO_APIC_route_entry);
3154 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3155 if (!mp_ioapic_data[i]) {
3156 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3159 dev = &mp_ioapic_data[i]->dev;
3161 dev->cls = &ioapic_sysdev_class;
3162 error = sysdev_register(dev);
3164 kfree(mp_ioapic_data[i]);
3165 mp_ioapic_data[i] = NULL;
3166 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3174 device_initcall(ioapic_init_sysfs);
3177 * Dynamic irq allocate and deallocation
3179 unsigned int create_irq_nr(unsigned int irq_want, int node)
3181 /* Allocate an unused irq */
3184 unsigned long flags;
3185 struct irq_cfg *cfg_new = NULL;
3186 struct irq_desc *desc_new = NULL;
3189 if (irq_want < nr_irqs_gsi)
3190 irq_want = nr_irqs_gsi;
3192 spin_lock_irqsave(&vector_lock, flags);
3193 for (new = irq_want; new < nr_irqs; new++) {
3194 desc_new = irq_to_desc_alloc_node(new, node);
3196 printk(KERN_INFO "can not get irq_desc for %d\n", new);
3199 cfg_new = desc_new->chip_data;
3201 if (cfg_new->vector != 0)
3204 desc_new = move_irq_desc(desc_new, node);
3205 cfg_new = desc_new->chip_data;
3207 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3211 spin_unlock_irqrestore(&vector_lock, flags);
3214 dynamic_irq_init(irq);
3215 /* restore it, in case dynamic_irq_init clear it */
3217 desc_new->chip_data = cfg_new;
3222 int create_irq(void)
3224 int node = cpu_to_node(boot_cpu_id);
3225 unsigned int irq_want;
3228 irq_want = nr_irqs_gsi;
3229 irq = create_irq_nr(irq_want, node);
3237 void destroy_irq(unsigned int irq)
3239 unsigned long flags;
3240 struct irq_cfg *cfg;
3241 struct irq_desc *desc;
3243 /* store it, in case dynamic_irq_cleanup clear it */
3244 desc = irq_to_desc(irq);
3245 cfg = desc->chip_data;
3246 dynamic_irq_cleanup(irq);
3247 /* connect back irq_cfg */
3248 desc->chip_data = cfg;
3251 spin_lock_irqsave(&vector_lock, flags);
3252 __clear_irq_vector(irq, cfg);
3253 spin_unlock_irqrestore(&vector_lock, flags);
3257 * MSI message composition
3259 #ifdef CONFIG_PCI_MSI
3260 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3261 struct msi_msg *msg, u8 hpet_id)
3263 struct irq_cfg *cfg;
3271 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3275 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3277 if (irq_remapped(irq)) {
3282 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3283 BUG_ON(ir_index == -1);
3285 memset (&irte, 0, sizeof(irte));
3288 irte.dst_mode = apic->irq_dest_mode;
3289 irte.trigger_mode = 0; /* edge */
3290 irte.dlvry_mode = apic->irq_delivery_mode;
3291 irte.vector = cfg->vector;
3292 irte.dest_id = IRTE_DEST(dest);
3294 /* Set source-id of interrupt request */
3296 set_msi_sid(&irte, pdev);
3298 set_hpet_sid(&irte, hpet_id);
3300 modify_irte(irq, &irte);
3302 msg->address_hi = MSI_ADDR_BASE_HI;
3303 msg->data = sub_handle;
3304 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3306 MSI_ADDR_IR_INDEX1(ir_index) |
3307 MSI_ADDR_IR_INDEX2(ir_index);
3309 if (x2apic_enabled())
3310 msg->address_hi = MSI_ADDR_BASE_HI |
3311 MSI_ADDR_EXT_DEST_ID(dest);
3313 msg->address_hi = MSI_ADDR_BASE_HI;
3317 ((apic->irq_dest_mode == 0) ?
3318 MSI_ADDR_DEST_MODE_PHYSICAL:
3319 MSI_ADDR_DEST_MODE_LOGICAL) |
3320 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3321 MSI_ADDR_REDIRECTION_CPU:
3322 MSI_ADDR_REDIRECTION_LOWPRI) |
3323 MSI_ADDR_DEST_ID(dest);
3326 MSI_DATA_TRIGGER_EDGE |
3327 MSI_DATA_LEVEL_ASSERT |
3328 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3329 MSI_DATA_DELIVERY_FIXED:
3330 MSI_DATA_DELIVERY_LOWPRI) |
3331 MSI_DATA_VECTOR(cfg->vector);
3337 static int set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3339 struct irq_desc *desc = irq_to_desc(irq);
3340 struct irq_cfg *cfg;
3344 if (set_desc_affinity(desc, mask, &dest))
3347 cfg = desc->chip_data;
3349 read_msi_msg_desc(desc, &msg);
3351 msg.data &= ~MSI_DATA_VECTOR_MASK;
3352 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3353 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3354 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3356 write_msi_msg_desc(desc, &msg);
3360 #ifdef CONFIG_INTR_REMAP
3362 * Migrate the MSI irq to another cpumask. This migration is
3363 * done in the process context using interrupt-remapping hardware.
3366 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3368 struct irq_desc *desc = irq_to_desc(irq);
3369 struct irq_cfg *cfg = desc->chip_data;
3373 if (get_irte(irq, &irte))
3376 if (set_desc_affinity(desc, mask, &dest))
3379 irte.vector = cfg->vector;
3380 irte.dest_id = IRTE_DEST(dest);
3383 * atomically update the IRTE with the new destination and vector.
3385 modify_irte(irq, &irte);
3388 * After this point, all the interrupts will start arriving
3389 * at the new destination. So, time to cleanup the previous
3390 * vector allocation.
3392 if (cfg->move_in_progress)
3393 send_cleanup_vector(cfg);
3399 #endif /* CONFIG_SMP */
3402 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3403 * which implement the MSI or MSI-X Capability Structure.
3405 static struct irq_chip msi_chip = {
3407 .unmask = unmask_msi_irq,
3408 .mask = mask_msi_irq,
3409 .ack = ack_apic_edge,
3411 .set_affinity = set_msi_irq_affinity,
3413 .retrigger = ioapic_retrigger_irq,
3416 static struct irq_chip msi_ir_chip = {
3417 .name = "IR-PCI-MSI",
3418 .unmask = unmask_msi_irq,
3419 .mask = mask_msi_irq,
3420 #ifdef CONFIG_INTR_REMAP
3421 .ack = ir_ack_apic_edge,
3423 .set_affinity = ir_set_msi_irq_affinity,
3426 .retrigger = ioapic_retrigger_irq,
3430 * Map the PCI dev to the corresponding remapping hardware unit
3431 * and allocate 'nvec' consecutive interrupt-remapping table entries
3434 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3436 struct intel_iommu *iommu;
3439 iommu = map_dev_to_ir(dev);
3442 "Unable to map PCI %s to iommu\n", pci_name(dev));
3446 index = alloc_irte(iommu, irq, nvec);
3449 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3456 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3461 ret = msi_compose_msg(dev, irq, &msg, -1);
3465 set_irq_msi(irq, msidesc);
3466 write_msi_msg(irq, &msg);
3468 if (irq_remapped(irq)) {
3469 struct irq_desc *desc = irq_to_desc(irq);
3471 * irq migration in process context
3473 desc->status |= IRQ_MOVE_PCNTXT;
3474 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3476 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3478 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3483 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3486 int ret, sub_handle;
3487 struct msi_desc *msidesc;
3488 unsigned int irq_want;
3489 struct intel_iommu *iommu = NULL;
3493 /* x86 doesn't support multiple MSI yet */
3494 if (type == PCI_CAP_ID_MSI && nvec > 1)
3497 node = dev_to_node(&dev->dev);
3498 irq_want = nr_irqs_gsi;
3500 list_for_each_entry(msidesc, &dev->msi_list, list) {
3501 irq = create_irq_nr(irq_want, node);
3505 if (!intr_remapping_enabled)
3510 * allocate the consecutive block of IRTE's
3513 index = msi_alloc_irte(dev, irq, nvec);
3519 iommu = map_dev_to_ir(dev);
3525 * setup the mapping between the irq and the IRTE
3526 * base index, the sub_handle pointing to the
3527 * appropriate interrupt remap table entry.
3529 set_irte_irq(irq, iommu, index, sub_handle);
3532 ret = setup_msi_irq(dev, msidesc, irq);
3544 void arch_teardown_msi_irq(unsigned int irq)
3549 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3551 static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3553 struct irq_desc *desc = irq_to_desc(irq);
3554 struct irq_cfg *cfg;
3558 if (set_desc_affinity(desc, mask, &dest))
3561 cfg = desc->chip_data;
3563 dmar_msi_read(irq, &msg);
3565 msg.data &= ~MSI_DATA_VECTOR_MASK;
3566 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3567 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3568 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3570 dmar_msi_write(irq, &msg);
3575 #endif /* CONFIG_SMP */
3577 static struct irq_chip dmar_msi_type = {
3579 .unmask = dmar_msi_unmask,
3580 .mask = dmar_msi_mask,
3581 .ack = ack_apic_edge,
3583 .set_affinity = dmar_msi_set_affinity,
3585 .retrigger = ioapic_retrigger_irq,
3588 int arch_setup_dmar_msi(unsigned int irq)
3593 ret = msi_compose_msg(NULL, irq, &msg, -1);
3596 dmar_msi_write(irq, &msg);
3597 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3603 #ifdef CONFIG_HPET_TIMER
3606 static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3608 struct irq_desc *desc = irq_to_desc(irq);
3609 struct irq_cfg *cfg;
3613 if (set_desc_affinity(desc, mask, &dest))
3616 cfg = desc->chip_data;
3618 hpet_msi_read(irq, &msg);
3620 msg.data &= ~MSI_DATA_VECTOR_MASK;
3621 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3622 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3623 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3625 hpet_msi_write(irq, &msg);
3630 #endif /* CONFIG_SMP */
3632 static struct irq_chip ir_hpet_msi_type = {
3633 .name = "IR-HPET_MSI",
3634 .unmask = hpet_msi_unmask,
3635 .mask = hpet_msi_mask,
3636 #ifdef CONFIG_INTR_REMAP
3637 .ack = ir_ack_apic_edge,
3639 .set_affinity = ir_set_msi_irq_affinity,
3642 .retrigger = ioapic_retrigger_irq,
3645 static struct irq_chip hpet_msi_type = {
3647 .unmask = hpet_msi_unmask,
3648 .mask = hpet_msi_mask,
3649 .ack = ack_apic_edge,
3651 .set_affinity = hpet_msi_set_affinity,
3653 .retrigger = ioapic_retrigger_irq,
3656 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3660 struct irq_desc *desc = irq_to_desc(irq);
3662 if (intr_remapping_enabled) {
3663 struct intel_iommu *iommu = map_hpet_to_ir(id);
3669 index = alloc_irte(iommu, irq, 1);
3674 ret = msi_compose_msg(NULL, irq, &msg, id);
3678 hpet_msi_write(irq, &msg);
3679 desc->status |= IRQ_MOVE_PCNTXT;
3680 if (irq_remapped(irq))
3681 set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
3682 handle_edge_irq, "edge");
3684 set_irq_chip_and_handler_name(irq, &hpet_msi_type,
3685 handle_edge_irq, "edge");
3691 #endif /* CONFIG_PCI_MSI */
3693 * Hypertransport interrupt support
3695 #ifdef CONFIG_HT_IRQ
3699 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3701 struct ht_irq_msg msg;
3702 fetch_ht_irq_msg(irq, &msg);
3704 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3705 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3707 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3708 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3710 write_ht_irq_msg(irq, &msg);
3713 static int set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3715 struct irq_desc *desc = irq_to_desc(irq);
3716 struct irq_cfg *cfg;
3719 if (set_desc_affinity(desc, mask, &dest))
3722 cfg = desc->chip_data;
3724 target_ht_irq(irq, dest, cfg->vector);
3731 static struct irq_chip ht_irq_chip = {
3733 .mask = mask_ht_irq,
3734 .unmask = unmask_ht_irq,
3735 .ack = ack_apic_edge,
3737 .set_affinity = set_ht_irq_affinity,
3739 .retrigger = ioapic_retrigger_irq,
3742 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3744 struct irq_cfg *cfg;
3751 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3753 struct ht_irq_msg msg;
3756 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3757 apic->target_cpus());
3759 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3763 HT_IRQ_LOW_DEST_ID(dest) |
3764 HT_IRQ_LOW_VECTOR(cfg->vector) |
3765 ((apic->irq_dest_mode == 0) ?
3766 HT_IRQ_LOW_DM_PHYSICAL :
3767 HT_IRQ_LOW_DM_LOGICAL) |
3768 HT_IRQ_LOW_RQEOI_EDGE |
3769 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3770 HT_IRQ_LOW_MT_FIXED :
3771 HT_IRQ_LOW_MT_ARBITRATED) |
3772 HT_IRQ_LOW_IRQ_MASKED;
3774 write_ht_irq_msg(irq, &msg);
3776 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3777 handle_edge_irq, "edge");
3779 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3783 #endif /* CONFIG_HT_IRQ */
3785 int __init io_apic_get_redir_entries (int ioapic)
3787 union IO_APIC_reg_01 reg_01;
3788 unsigned long flags;
3790 spin_lock_irqsave(&ioapic_lock, flags);
3791 reg_01.raw = io_apic_read(ioapic, 1);
3792 spin_unlock_irqrestore(&ioapic_lock, flags);
3794 return reg_01.bits.entries;
3797 void __init probe_nr_irqs_gsi(void)
3801 nr = acpi_probe_gsi();
3802 if (nr > nr_irqs_gsi) {
3805 /* for acpi=off or acpi is not compiled in */
3809 for (idx = 0; idx < nr_ioapics; idx++)
3810 nr += io_apic_get_redir_entries(idx) + 1;
3812 if (nr > nr_irqs_gsi)
3816 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3819 #ifdef CONFIG_SPARSE_IRQ
3820 int __init arch_probe_nr_irqs(void)
3824 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3825 nr_irqs = NR_VECTORS * nr_cpu_ids;
3827 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3828 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3830 * for MSI and HT dyn irq
3832 nr += nr_irqs_gsi * 16;
3841 static int __io_apic_set_pci_routing(struct device *dev, int irq,
3842 struct io_apic_irq_attr *irq_attr)
3844 struct irq_desc *desc;
3845 struct irq_cfg *cfg;
3848 int trigger, polarity;
3850 ioapic = irq_attr->ioapic;
3851 if (!IO_APIC_IRQ(irq)) {
3852 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3858 node = dev_to_node(dev);
3860 node = cpu_to_node(boot_cpu_id);
3862 desc = irq_to_desc_alloc_node(irq, node);
3864 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3868 pin = irq_attr->ioapic_pin;
3869 trigger = irq_attr->trigger;
3870 polarity = irq_attr->polarity;
3873 * IRQs < 16 are already in the irq_2_pin[] map
3875 if (irq >= legacy_pic->nr_legacy_irqs) {
3876 cfg = desc->chip_data;
3877 if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
3878 printk(KERN_INFO "can not add pin %d for irq %d\n",
3884 setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
3889 int io_apic_set_pci_routing(struct device *dev, int irq,
3890 struct io_apic_irq_attr *irq_attr)
3894 * Avoid pin reprogramming. PRTs typically include entries
3895 * with redundant pin->gsi mappings (but unique PCI devices);
3896 * we only program the IOAPIC on the first.
3898 ioapic = irq_attr->ioapic;
3899 pin = irq_attr->ioapic_pin;
3900 if (test_bit(pin, mp_ioapic_routing[ioapic].pin_programmed)) {
3901 pr_debug("Pin %d-%d already programmed\n",
3902 mp_ioapics[ioapic].apicid, pin);
3905 set_bit(pin, mp_ioapic_routing[ioapic].pin_programmed);
3907 return __io_apic_set_pci_routing(dev, irq, irq_attr);
3910 u8 __init io_apic_unique_id(u8 id)
3912 #ifdef CONFIG_X86_32
3913 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3914 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3915 return io_apic_get_unique_id(nr_ioapics, id);
3920 DECLARE_BITMAP(used, 256);
3922 bitmap_zero(used, 256);
3923 for (i = 0; i < nr_ioapics; i++) {
3924 struct mpc_ioapic *ia = &mp_ioapics[i];
3925 __set_bit(ia->apicid, used);
3927 if (!test_bit(id, used))
3929 return find_first_zero_bit(used, 256);
3933 #ifdef CONFIG_X86_32
3934 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3936 union IO_APIC_reg_00 reg_00;
3937 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3939 unsigned long flags;
3943 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3944 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3945 * supports up to 16 on one shared APIC bus.
3947 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3948 * advantage of new APIC bus architecture.
3951 if (physids_empty(apic_id_map))
3952 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3954 spin_lock_irqsave(&ioapic_lock, flags);
3955 reg_00.raw = io_apic_read(ioapic, 0);
3956 spin_unlock_irqrestore(&ioapic_lock, flags);
3958 if (apic_id >= get_physical_broadcast()) {
3959 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3960 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3961 apic_id = reg_00.bits.ID;
3965 * Every APIC in a system must have a unique ID or we get lots of nice
3966 * 'stuck on smp_invalidate_needed IPI wait' messages.
3968 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3970 for (i = 0; i < get_physical_broadcast(); i++) {
3971 if (!apic->check_apicid_used(&apic_id_map, i))
3975 if (i == get_physical_broadcast())
3976 panic("Max apic_id exceeded!\n");
3978 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3979 "trying %d\n", ioapic, apic_id, i);
3984 apic->apicid_to_cpu_present(apic_id, &tmp);
3985 physids_or(apic_id_map, apic_id_map, tmp);
3987 if (reg_00.bits.ID != apic_id) {
3988 reg_00.bits.ID = apic_id;
3990 spin_lock_irqsave(&ioapic_lock, flags);
3991 io_apic_write(ioapic, 0, reg_00.raw);
3992 reg_00.raw = io_apic_read(ioapic, 0);
3993 spin_unlock_irqrestore(&ioapic_lock, flags);
3996 if (reg_00.bits.ID != apic_id) {
3997 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
4002 apic_printk(APIC_VERBOSE, KERN_INFO
4003 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
4009 int __init io_apic_get_version(int ioapic)
4011 union IO_APIC_reg_01 reg_01;
4012 unsigned long flags;
4014 spin_lock_irqsave(&ioapic_lock, flags);
4015 reg_01.raw = io_apic_read(ioapic, 1);
4016 spin_unlock_irqrestore(&ioapic_lock, flags);
4018 return reg_01.bits.version;
4021 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
4025 if (skip_ioapic_setup)
4028 for (i = 0; i < mp_irq_entries; i++)
4029 if (mp_irqs[i].irqtype == mp_INT &&
4030 mp_irqs[i].srcbusirq == bus_irq)
4032 if (i >= mp_irq_entries)
4035 *trigger = irq_trigger(i);
4036 *polarity = irq_polarity(i);
4041 * This function currently is only a helper for the i386 smp boot process where
4042 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4043 * so mask in all cases should simply be apic->target_cpus()
4046 void __init setup_ioapic_dest(void)
4048 int pin, ioapic = 0, irq, irq_entry;
4049 struct irq_desc *desc;
4050 const struct cpumask *mask;
4052 if (skip_ioapic_setup == 1)
4056 if (!acpi_disabled && acpi_ioapic) {
4057 ioapic = mp_find_ioapic(0);
4063 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4064 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4065 if (irq_entry == -1)
4067 irq = pin_2_irq(irq_entry, ioapic, pin);
4069 desc = irq_to_desc(irq);
4072 * Honour affinities which have been set in early boot
4075 (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4076 mask = desc->affinity;
4078 mask = apic->target_cpus();
4080 if (intr_remapping_enabled)
4081 set_ir_ioapic_affinity_irq_desc(desc, mask);
4083 set_ioapic_affinity_irq_desc(desc, mask);
4089 #define IOAPIC_RESOURCE_NAME_SIZE 11
4091 static struct resource *ioapic_resources;
4093 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
4096 struct resource *res;
4100 if (nr_ioapics <= 0)
4103 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4106 mem = alloc_bootmem(n);
4109 mem += sizeof(struct resource) * nr_ioapics;
4111 for (i = 0; i < nr_ioapics; i++) {
4113 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4114 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
4115 mem += IOAPIC_RESOURCE_NAME_SIZE;
4118 ioapic_resources = res;
4123 void __init ioapic_init_mappings(void)
4125 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4126 struct resource *ioapic_res;
4129 ioapic_res = ioapic_setup_resources(nr_ioapics);
4130 for (i = 0; i < nr_ioapics; i++) {
4131 if (smp_found_config) {
4132 ioapic_phys = mp_ioapics[i].apicaddr;
4133 #ifdef CONFIG_X86_32
4136 "WARNING: bogus zero IO-APIC "
4137 "address found in MPTABLE, "
4138 "disabling IO/APIC support!\n");
4139 smp_found_config = 0;
4140 skip_ioapic_setup = 1;
4141 goto fake_ioapic_page;
4145 #ifdef CONFIG_X86_32
4148 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
4149 ioapic_phys = __pa(ioapic_phys);
4151 set_fixmap_nocache(idx, ioapic_phys);
4152 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
4153 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
4157 ioapic_res->start = ioapic_phys;
4158 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
4163 void __init ioapic_insert_resources(void)
4166 struct resource *r = ioapic_resources;
4171 "IO APIC resources couldn't be allocated.\n");
4175 for (i = 0; i < nr_ioapics; i++) {
4176 insert_resource(&iomem_resource, r);
4181 int mp_find_ioapic(int gsi)
4185 /* Find the IOAPIC that manages this GSI. */
4186 for (i = 0; i < nr_ioapics; i++) {
4187 if ((gsi >= mp_gsi_routing[i].gsi_base)
4188 && (gsi <= mp_gsi_routing[i].gsi_end))
4192 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
4196 int mp_find_ioapic_pin(int ioapic, int gsi)
4198 if (WARN_ON(ioapic == -1))
4200 if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
4203 return gsi - mp_gsi_routing[ioapic].gsi_base;
4206 static int bad_ioapic(unsigned long address)
4208 if (nr_ioapics >= MAX_IO_APICS) {
4209 printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
4210 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
4214 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
4215 " found in table, skipping!\n");
4221 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
4225 if (bad_ioapic(address))
4230 mp_ioapics[idx].type = MP_IOAPIC;
4231 mp_ioapics[idx].flags = MPC_APIC_USABLE;
4232 mp_ioapics[idx].apicaddr = address;
4234 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
4235 mp_ioapics[idx].apicid = io_apic_unique_id(id);
4236 mp_ioapics[idx].apicver = io_apic_get_version(idx);
4239 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
4240 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
4242 mp_gsi_routing[idx].gsi_base = gsi_base;
4243 mp_gsi_routing[idx].gsi_end = gsi_base +
4244 io_apic_get_redir_entries(idx);
4246 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4247 "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
4248 mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
4249 mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);