2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
68 #define for_each_irq_pin(entry, head) \
69 for (entry = head; entry; entry = entry->next)
71 #ifdef CONFIG_IRQ_REMAP
72 static void irq_remap_modify_chip_defaults(struct irq_chip *chip);
73 static inline bool irq_remapped(struct irq_cfg *cfg)
75 return cfg->irq_2_iommu.iommu != NULL;
78 static inline bool irq_remapped(struct irq_cfg *cfg)
82 static inline void irq_remap_modify_chip_defaults(struct irq_chip *chip)
88 * Is the SiS APIC rmw bug present ?
89 * -1 = don't know, 0 = no, 1 = yes
91 int sis_apic_bug = -1;
93 static DEFINE_RAW_SPINLOCK(ioapic_lock);
94 static DEFINE_RAW_SPINLOCK(vector_lock);
96 static struct ioapic {
98 * # of IRQ routing registers
102 * Saved state during suspend/resume, or while enabling intr-remap.
104 struct IO_APIC_route_entry *saved_registers;
105 /* I/O APIC config */
106 struct mpc_ioapic mp_config;
107 /* IO APIC gsi routing info */
108 struct mp_ioapic_gsi gsi_config;
109 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
110 } ioapics[MAX_IO_APICS];
112 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
114 int mpc_ioapic_id(int ioapic_idx)
116 return ioapics[ioapic_idx].mp_config.apicid;
119 unsigned int mpc_ioapic_addr(int ioapic_idx)
121 return ioapics[ioapic_idx].mp_config.apicaddr;
124 struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
126 return &ioapics[ioapic_idx].gsi_config;
131 /* The one past the highest gsi number used */
134 /* MP IRQ source entries */
135 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
137 /* # of MP IRQ source entries */
141 static int nr_irqs_gsi = NR_IRQS_LEGACY;
144 int mp_bus_id_to_type[MAX_MP_BUSSES];
147 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
149 int skip_ioapic_setup;
152 * disable_ioapic_support() - disables ioapic support at runtime
154 void disable_ioapic_support(void)
158 noioapicreroute = -1;
160 skip_ioapic_setup = 1;
163 static int __init parse_noapic(char *str)
165 /* disable IO-APIC */
166 disable_ioapic_support();
169 early_param("noapic", parse_noapic);
171 static int io_apic_setup_irq_pin(unsigned int irq, int node,
172 struct io_apic_irq_attr *attr);
174 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
175 void mp_save_irq(struct mpc_intsrc *m)
179 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
180 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
181 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
182 m->srcbusirq, m->dstapic, m->dstirq);
184 for (i = 0; i < mp_irq_entries; i++) {
185 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
189 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
190 if (++mp_irq_entries == MAX_IRQ_SOURCES)
191 panic("Max # of irq sources exceeded!!\n");
194 struct irq_pin_list {
196 struct irq_pin_list *next;
199 static struct irq_pin_list *alloc_irq_pin_list(int node)
201 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
205 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
206 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
208 int __init arch_early_irq_init(void)
213 if (!legacy_pic->nr_legacy_irqs)
216 for (i = 0; i < nr_ioapics; i++) {
217 ioapics[i].saved_registers =
218 kzalloc(sizeof(struct IO_APIC_route_entry) *
219 ioapics[i].nr_registers, GFP_KERNEL);
220 if (!ioapics[i].saved_registers)
221 pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
225 count = ARRAY_SIZE(irq_cfgx);
226 node = cpu_to_node(0);
228 /* Make sure the legacy interrupts are marked in the bitmap */
229 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
231 for (i = 0; i < count; i++) {
232 irq_set_chip_data(i, &cfg[i]);
233 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
234 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
236 * For legacy IRQ's, start with assigning irq0 to irq15 to
237 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
239 if (i < legacy_pic->nr_legacy_irqs) {
240 cfg[i].vector = IRQ0_VECTOR + i;
241 cpumask_set_cpu(0, cfg[i].domain);
248 static struct irq_cfg *irq_cfg(unsigned int irq)
250 return irq_get_chip_data(irq);
253 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
257 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
260 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
262 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
266 free_cpumask_var(cfg->domain);
272 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
276 irq_set_chip_data(at, NULL);
277 free_cpumask_var(cfg->domain);
278 free_cpumask_var(cfg->old_domain);
282 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
284 int res = irq_alloc_desc_at(at, node);
290 cfg = irq_get_chip_data(at);
295 cfg = alloc_irq_cfg(at, node);
297 irq_set_chip_data(at, cfg);
303 static int alloc_irq_from(unsigned int from, int node)
305 return irq_alloc_desc_from(from, node);
308 static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
310 free_irq_cfg(at, cfg);
317 unsigned int unused[3];
319 unsigned int unused2[11];
323 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
325 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
326 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
329 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
331 struct io_apic __iomem *io_apic = io_apic_base(apic);
332 writel(vector, &io_apic->eoi);
335 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
337 struct io_apic __iomem *io_apic = io_apic_base(apic);
338 writel(reg, &io_apic->index);
339 return readl(&io_apic->data);
342 void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
344 struct io_apic __iomem *io_apic = io_apic_base(apic);
346 writel(reg, &io_apic->index);
347 writel(value, &io_apic->data);
351 * Re-write a value: to be used for read-modify-write
352 * cycles where the read already set up the index register.
354 * Older SiS APIC requires we rewrite the index register
356 void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
358 struct io_apic __iomem *io_apic = io_apic_base(apic);
361 writel(reg, &io_apic->index);
362 writel(value, &io_apic->data);
366 struct { u32 w1, w2; };
367 struct IO_APIC_route_entry entry;
370 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
372 union entry_union eu;
374 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
375 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
380 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
382 union entry_union eu;
385 raw_spin_lock_irqsave(&ioapic_lock, flags);
386 eu.entry = __ioapic_read_entry(apic, pin);
387 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
393 * When we write a new IO APIC routing entry, we need to write the high
394 * word first! If the mask bit in the low word is clear, we will enable
395 * the interrupt, and we need to make sure the entry is fully populated
396 * before that happens.
398 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
400 union entry_union eu = {{0, 0}};
403 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
404 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
407 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
411 raw_spin_lock_irqsave(&ioapic_lock, flags);
412 __ioapic_write_entry(apic, pin, e);
413 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
417 * When we mask an IO APIC routing entry, we need to write the low
418 * word first, in order to set the mask bit before we change the
421 static void ioapic_mask_entry(int apic, int pin)
424 union entry_union eu = { .entry.mask = 1 };
426 raw_spin_lock_irqsave(&ioapic_lock, flags);
427 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
428 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
429 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
433 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
434 * shared ISA-space IRQs, so we have to support them. We are super
435 * fast in the common case, and fast for shared ISA-space IRQs.
437 static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
439 struct irq_pin_list **last, *entry;
441 /* don't allow duplicates */
442 last = &cfg->irq_2_pin;
443 for_each_irq_pin(entry, cfg->irq_2_pin) {
444 if (entry->apic == apic && entry->pin == pin)
449 entry = alloc_irq_pin_list(node);
451 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
462 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
464 if (__add_pin_to_irq_node(cfg, node, apic, pin))
465 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
469 * Reroute an IRQ to a different pin.
471 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
472 int oldapic, int oldpin,
473 int newapic, int newpin)
475 struct irq_pin_list *entry;
477 for_each_irq_pin(entry, cfg->irq_2_pin) {
478 if (entry->apic == oldapic && entry->pin == oldpin) {
479 entry->apic = newapic;
481 /* every one is different, right? */
486 /* old apic/pin didn't exist, so just add new ones */
487 add_pin_to_irq_node(cfg, node, newapic, newpin);
490 static void __io_apic_modify_irq(struct irq_pin_list *entry,
491 int mask_and, int mask_or,
492 void (*final)(struct irq_pin_list *entry))
494 unsigned int reg, pin;
497 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
500 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
505 static void io_apic_modify_irq(struct irq_cfg *cfg,
506 int mask_and, int mask_or,
507 void (*final)(struct irq_pin_list *entry))
509 struct irq_pin_list *entry;
511 for_each_irq_pin(entry, cfg->irq_2_pin)
512 __io_apic_modify_irq(entry, mask_and, mask_or, final);
515 static void io_apic_sync(struct irq_pin_list *entry)
518 * Synchronize the IO-APIC and the CPU by doing
519 * a dummy read from the IO-APIC
521 struct io_apic __iomem *io_apic;
523 io_apic = io_apic_base(entry->apic);
524 readl(&io_apic->data);
527 static void mask_ioapic(struct irq_cfg *cfg)
531 raw_spin_lock_irqsave(&ioapic_lock, flags);
532 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
533 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
536 static void mask_ioapic_irq(struct irq_data *data)
538 mask_ioapic(data->chip_data);
541 static void __unmask_ioapic(struct irq_cfg *cfg)
543 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
546 static void unmask_ioapic(struct irq_cfg *cfg)
550 raw_spin_lock_irqsave(&ioapic_lock, flags);
551 __unmask_ioapic(cfg);
552 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
555 static void unmask_ioapic_irq(struct irq_data *data)
557 unmask_ioapic(data->chip_data);
561 * IO-APIC versions below 0x20 don't support EOI register.
562 * For the record, here is the information about various versions:
564 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
565 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
568 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
569 * version as 0x2. This is an error with documentation and these ICH chips
570 * use io-apic's of version 0x20.
572 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
573 * Otherwise, we simulate the EOI message manually by changing the trigger
574 * mode to edge and then back to level, with RTE being masked during this.
576 static void __eoi_ioapic_pin(int apic, int pin, int vector, struct irq_cfg *cfg)
578 if (mpc_ioapic_ver(apic) >= 0x20) {
580 * Intr-remapping uses pin number as the virtual vector
581 * in the RTE. Actual vector is programmed in
582 * intr-remapping table entry. Hence for the io-apic
583 * EOI we use the pin number.
585 if (cfg && irq_remapped(cfg))
586 io_apic_eoi(apic, pin);
588 io_apic_eoi(apic, vector);
590 struct IO_APIC_route_entry entry, entry1;
592 entry = entry1 = __ioapic_read_entry(apic, pin);
595 * Mask the entry and change the trigger mode to edge.
598 entry1.trigger = IOAPIC_EDGE;
600 __ioapic_write_entry(apic, pin, entry1);
603 * Restore the previous level triggered entry.
605 __ioapic_write_entry(apic, pin, entry);
609 static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
611 struct irq_pin_list *entry;
614 raw_spin_lock_irqsave(&ioapic_lock, flags);
615 for_each_irq_pin(entry, cfg->irq_2_pin)
616 __eoi_ioapic_pin(entry->apic, entry->pin, cfg->vector, cfg);
617 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
620 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
622 struct IO_APIC_route_entry entry;
624 /* Check delivery_mode to be sure we're not clearing an SMI pin */
625 entry = ioapic_read_entry(apic, pin);
626 if (entry.delivery_mode == dest_SMI)
630 * Make sure the entry is masked and re-read the contents to check
631 * if it is a level triggered pin and if the remote-IRR is set.
635 ioapic_write_entry(apic, pin, entry);
636 entry = ioapic_read_entry(apic, pin);
643 * Make sure the trigger mode is set to level. Explicit EOI
644 * doesn't clear the remote-IRR if the trigger mode is not
647 if (!entry.trigger) {
648 entry.trigger = IOAPIC_LEVEL;
649 ioapic_write_entry(apic, pin, entry);
652 raw_spin_lock_irqsave(&ioapic_lock, flags);
653 __eoi_ioapic_pin(apic, pin, entry.vector, NULL);
654 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
658 * Clear the rest of the bits in the IO-APIC RTE except for the mask
661 ioapic_mask_entry(apic, pin);
662 entry = ioapic_read_entry(apic, pin);
664 pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
665 mpc_ioapic_id(apic), pin);
668 static void clear_IO_APIC (void)
672 for (apic = 0; apic < nr_ioapics; apic++)
673 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
674 clear_IO_APIC_pin(apic, pin);
679 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
680 * specific CPU-side IRQs.
684 static int pirq_entries[MAX_PIRQS] = {
685 [0 ... MAX_PIRQS - 1] = -1
688 static int __init ioapic_pirq_setup(char *str)
691 int ints[MAX_PIRQS+1];
693 get_options(str, ARRAY_SIZE(ints), ints);
695 apic_printk(APIC_VERBOSE, KERN_INFO
696 "PIRQ redirection, working around broken MP-BIOS.\n");
698 if (ints[0] < MAX_PIRQS)
701 for (i = 0; i < max; i++) {
702 apic_printk(APIC_VERBOSE, KERN_DEBUG
703 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
705 * PIRQs are mapped upside down, usually.
707 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
712 __setup("pirq=", ioapic_pirq_setup);
713 #endif /* CONFIG_X86_32 */
716 * Saves all the IO-APIC RTE's
718 int save_ioapic_entries(void)
723 for (apic = 0; apic < nr_ioapics; apic++) {
724 if (!ioapics[apic].saved_registers) {
729 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
730 ioapics[apic].saved_registers[pin] =
731 ioapic_read_entry(apic, pin);
738 * Mask all IO APIC entries.
740 void mask_ioapic_entries(void)
744 for (apic = 0; apic < nr_ioapics; apic++) {
745 if (!ioapics[apic].saved_registers)
748 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
749 struct IO_APIC_route_entry entry;
751 entry = ioapics[apic].saved_registers[pin];
754 ioapic_write_entry(apic, pin, entry);
761 * Restore IO APIC entries which was saved in the ioapic structure.
763 int restore_ioapic_entries(void)
767 for (apic = 0; apic < nr_ioapics; apic++) {
768 if (!ioapics[apic].saved_registers)
771 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
772 ioapic_write_entry(apic, pin,
773 ioapics[apic].saved_registers[pin]);
779 * Find the IRQ entry number of a certain pin.
781 static int find_irq_entry(int ioapic_idx, int pin, int type)
785 for (i = 0; i < mp_irq_entries; i++)
786 if (mp_irqs[i].irqtype == type &&
787 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
788 mp_irqs[i].dstapic == MP_APIC_ALL) &&
789 mp_irqs[i].dstirq == pin)
796 * Find the pin to which IRQ[irq] (ISA) is connected
798 static int __init find_isa_irq_pin(int irq, int type)
802 for (i = 0; i < mp_irq_entries; i++) {
803 int lbus = mp_irqs[i].srcbus;
805 if (test_bit(lbus, mp_bus_not_pci) &&
806 (mp_irqs[i].irqtype == type) &&
807 (mp_irqs[i].srcbusirq == irq))
809 return mp_irqs[i].dstirq;
814 static int __init find_isa_irq_apic(int irq, int type)
818 for (i = 0; i < mp_irq_entries; i++) {
819 int lbus = mp_irqs[i].srcbus;
821 if (test_bit(lbus, mp_bus_not_pci) &&
822 (mp_irqs[i].irqtype == type) &&
823 (mp_irqs[i].srcbusirq == irq))
827 if (i < mp_irq_entries) {
830 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
831 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
840 * EISA Edge/Level control register, ELCR
842 static int EISA_ELCR(unsigned int irq)
844 if (irq < legacy_pic->nr_legacy_irqs) {
845 unsigned int port = 0x4d0 + (irq >> 3);
846 return (inb(port) >> (irq & 7)) & 1;
848 apic_printk(APIC_VERBOSE, KERN_INFO
849 "Broken MPtable reports ISA irq %d\n", irq);
855 /* ISA interrupts are always polarity zero edge triggered,
856 * when listed as conforming in the MP table. */
858 #define default_ISA_trigger(idx) (0)
859 #define default_ISA_polarity(idx) (0)
861 /* EISA interrupts are always polarity zero and can be edge or level
862 * trigger depending on the ELCR value. If an interrupt is listed as
863 * EISA conforming in the MP table, that means its trigger type must
864 * be read in from the ELCR */
866 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
867 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
869 /* PCI interrupts are always polarity one level triggered,
870 * when listed as conforming in the MP table. */
872 #define default_PCI_trigger(idx) (1)
873 #define default_PCI_polarity(idx) (1)
875 static int irq_polarity(int idx)
877 int bus = mp_irqs[idx].srcbus;
881 * Determine IRQ line polarity (high active or low active):
883 switch (mp_irqs[idx].irqflag & 3)
885 case 0: /* conforms, ie. bus-type dependent polarity */
886 if (test_bit(bus, mp_bus_not_pci))
887 polarity = default_ISA_polarity(idx);
889 polarity = default_PCI_polarity(idx);
891 case 1: /* high active */
896 case 2: /* reserved */
898 pr_warn("broken BIOS!!\n");
902 case 3: /* low active */
907 default: /* invalid */
909 pr_warn("broken BIOS!!\n");
917 static int irq_trigger(int idx)
919 int bus = mp_irqs[idx].srcbus;
923 * Determine IRQ trigger mode (edge or level sensitive):
925 switch ((mp_irqs[idx].irqflag>>2) & 3)
927 case 0: /* conforms, ie. bus-type dependent */
928 if (test_bit(bus, mp_bus_not_pci))
929 trigger = default_ISA_trigger(idx);
931 trigger = default_PCI_trigger(idx);
933 switch (mp_bus_id_to_type[bus]) {
934 case MP_BUS_ISA: /* ISA pin */
936 /* set before the switch */
939 case MP_BUS_EISA: /* EISA pin */
941 trigger = default_EISA_trigger(idx);
944 case MP_BUS_PCI: /* PCI pin */
946 /* set before the switch */
951 pr_warn("broken BIOS!!\n");
963 case 2: /* reserved */
965 pr_warn("broken BIOS!!\n");
974 default: /* invalid */
976 pr_warn("broken BIOS!!\n");
984 static int pin_2_irq(int idx, int apic, int pin)
987 int bus = mp_irqs[idx].srcbus;
988 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
991 * Debugging check, we are in big trouble if this message pops up!
993 if (mp_irqs[idx].dstirq != pin)
994 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
996 if (test_bit(bus, mp_bus_not_pci)) {
997 irq = mp_irqs[idx].srcbusirq;
999 u32 gsi = gsi_cfg->gsi_base + pin;
1001 if (gsi >= NR_IRQS_LEGACY)
1004 irq = gsi_top + gsi;
1007 #ifdef CONFIG_X86_32
1009 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1011 if ((pin >= 16) && (pin <= 23)) {
1012 if (pirq_entries[pin-16] != -1) {
1013 if (!pirq_entries[pin-16]) {
1014 apic_printk(APIC_VERBOSE, KERN_DEBUG
1015 "disabling PIRQ%d\n", pin-16);
1017 irq = pirq_entries[pin-16];
1018 apic_printk(APIC_VERBOSE, KERN_DEBUG
1019 "using PIRQ%d -> IRQ %d\n",
1030 * Find a specific PCI IRQ entry.
1031 * Not an __init, possibly needed by modules
1033 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1034 struct io_apic_irq_attr *irq_attr)
1036 int ioapic_idx, i, best_guess = -1;
1038 apic_printk(APIC_DEBUG,
1039 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1041 if (test_bit(bus, mp_bus_not_pci)) {
1042 apic_printk(APIC_VERBOSE,
1043 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1046 for (i = 0; i < mp_irq_entries; i++) {
1047 int lbus = mp_irqs[i].srcbus;
1049 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1050 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1051 mp_irqs[i].dstapic == MP_APIC_ALL)
1054 if (!test_bit(lbus, mp_bus_not_pci) &&
1055 !mp_irqs[i].irqtype &&
1057 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1058 int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq);
1060 if (!(ioapic_idx || IO_APIC_IRQ(irq)))
1063 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1064 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1071 * Use the first all-but-pin matching entry as a
1072 * best-guess fuzzy result for broken mptables.
1074 if (best_guess < 0) {
1075 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1085 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1087 void lock_vector_lock(void)
1089 /* Used to the online set of cpus does not change
1090 * during assign_irq_vector.
1092 raw_spin_lock(&vector_lock);
1095 void unlock_vector_lock(void)
1097 raw_spin_unlock(&vector_lock);
1101 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1104 * NOTE! The local APIC isn't very good at handling
1105 * multiple interrupts at the same interrupt level.
1106 * As the interrupt level is determined by taking the
1107 * vector number and shifting that right by 4, we
1108 * want to spread these out a bit so that they don't
1109 * all fall in the same interrupt level.
1111 * Also, we've got to be careful not to trash gate
1112 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1114 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1115 static int current_offset = VECTOR_OFFSET_START % 8;
1116 unsigned int old_vector;
1118 cpumask_var_t tmp_mask;
1120 if (cfg->move_in_progress)
1123 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1126 old_vector = cfg->vector;
1128 cpumask_and(tmp_mask, mask, cpu_online_mask);
1129 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1130 if (!cpumask_empty(tmp_mask)) {
1131 free_cpumask_var(tmp_mask);
1136 /* Only try and allocate irqs on cpus that are present */
1138 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1142 apic->vector_allocation_domain(cpu, tmp_mask);
1144 vector = current_vector;
1145 offset = current_offset;
1148 if (vector >= first_system_vector) {
1149 /* If out of vectors on large boxen, must share them. */
1150 offset = (offset + 1) % 8;
1151 vector = FIRST_EXTERNAL_VECTOR + offset;
1153 if (unlikely(current_vector == vector))
1156 if (test_bit(vector, used_vectors))
1159 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1160 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1163 current_vector = vector;
1164 current_offset = offset;
1166 cfg->move_in_progress = 1;
1167 cpumask_copy(cfg->old_domain, cfg->domain);
1169 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1170 per_cpu(vector_irq, new_cpu)[vector] = irq;
1171 cfg->vector = vector;
1172 cpumask_copy(cfg->domain, tmp_mask);
1176 free_cpumask_var(tmp_mask);
1180 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1183 unsigned long flags;
1185 raw_spin_lock_irqsave(&vector_lock, flags);
1186 err = __assign_irq_vector(irq, cfg, mask);
1187 raw_spin_unlock_irqrestore(&vector_lock, flags);
1191 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1195 BUG_ON(!cfg->vector);
1197 vector = cfg->vector;
1198 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1199 per_cpu(vector_irq, cpu)[vector] = -1;
1202 cpumask_clear(cfg->domain);
1204 if (likely(!cfg->move_in_progress))
1206 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1207 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1209 if (per_cpu(vector_irq, cpu)[vector] != irq)
1211 per_cpu(vector_irq, cpu)[vector] = -1;
1215 cfg->move_in_progress = 0;
1218 void __setup_vector_irq(int cpu)
1220 /* Initialize vector_irq on a new cpu */
1222 struct irq_cfg *cfg;
1225 * vector_lock will make sure that we don't run into irq vector
1226 * assignments that might be happening on another cpu in parallel,
1227 * while we setup our initial vector to irq mappings.
1229 raw_spin_lock(&vector_lock);
1230 /* Mark the inuse vectors */
1231 for_each_active_irq(irq) {
1232 cfg = irq_get_chip_data(irq);
1236 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1237 * will be part of the irq_cfg's domain.
1239 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1240 cpumask_set_cpu(cpu, cfg->domain);
1242 if (!cpumask_test_cpu(cpu, cfg->domain))
1244 vector = cfg->vector;
1245 per_cpu(vector_irq, cpu)[vector] = irq;
1247 /* Mark the free vectors */
1248 for (vector = 0; vector < NR_VECTORS; ++vector) {
1249 irq = per_cpu(vector_irq, cpu)[vector];
1254 if (!cpumask_test_cpu(cpu, cfg->domain))
1255 per_cpu(vector_irq, cpu)[vector] = -1;
1257 raw_spin_unlock(&vector_lock);
1260 static struct irq_chip ioapic_chip;
1262 #ifdef CONFIG_X86_32
1263 static inline int IO_APIC_irq_trigger(int irq)
1267 for (apic = 0; apic < nr_ioapics; apic++) {
1268 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1269 idx = find_irq_entry(apic, pin, mp_INT);
1270 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1271 return irq_trigger(idx);
1275 * nonexistent IRQs are edge default
1280 static inline int IO_APIC_irq_trigger(int irq)
1286 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1287 unsigned long trigger)
1289 struct irq_chip *chip = &ioapic_chip;
1290 irq_flow_handler_t hdl;
1293 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1294 trigger == IOAPIC_LEVEL) {
1295 irq_set_status_flags(irq, IRQ_LEVEL);
1298 irq_clear_status_flags(irq, IRQ_LEVEL);
1302 if (irq_remapped(cfg)) {
1303 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1304 irq_remap_modify_chip_defaults(chip);
1305 fasteoi = trigger != 0;
1308 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1309 irq_set_chip_and_handler_name(irq, chip, hdl,
1310 fasteoi ? "fasteoi" : "edge");
1313 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
1314 unsigned int destination, int vector,
1315 struct io_apic_irq_attr *attr)
1317 if (irq_remapping_enabled)
1318 return setup_ioapic_remapped_entry(irq, entry, destination,
1321 memset(entry, 0, sizeof(*entry));
1323 entry->delivery_mode = apic->irq_delivery_mode;
1324 entry->dest_mode = apic->irq_dest_mode;
1325 entry->dest = destination;
1326 entry->vector = vector;
1327 entry->mask = 0; /* enable IRQ */
1328 entry->trigger = attr->trigger;
1329 entry->polarity = attr->polarity;
1332 * Mask level triggered irqs.
1333 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1341 static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1342 struct io_apic_irq_attr *attr)
1344 struct IO_APIC_route_entry entry;
1347 if (!IO_APIC_IRQ(irq))
1350 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1351 * controllers like 8259. Now that IO-APIC can handle this irq, update
1354 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1355 apic->vector_allocation_domain(0, cfg->domain);
1357 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1360 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1362 apic_printk(APIC_VERBOSE,KERN_DEBUG
1363 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1364 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1365 attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
1366 cfg->vector, irq, attr->trigger, attr->polarity, dest);
1368 if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) {
1369 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1370 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1371 __clear_irq_vector(irq, cfg);
1376 ioapic_register_intr(irq, cfg, attr->trigger);
1377 if (irq < legacy_pic->nr_legacy_irqs)
1378 legacy_pic->mask(irq);
1380 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1383 static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin)
1388 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1389 mpc_ioapic_id(ioapic_idx), pin);
1393 static void __init __io_apic_setup_irqs(unsigned int ioapic_idx)
1395 int idx, node = cpu_to_node(0);
1396 struct io_apic_irq_attr attr;
1397 unsigned int pin, irq;
1399 for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) {
1400 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1401 if (io_apic_pin_not_connected(idx, ioapic_idx, pin))
1404 irq = pin_2_irq(idx, ioapic_idx, pin);
1406 if ((ioapic_idx > 0) && (irq > 16))
1410 * Skip the timer IRQ if there's a quirk handler
1411 * installed and if it returns 1:
1413 if (apic->multi_timer_check &&
1414 apic->multi_timer_check(ioapic_idx, irq))
1417 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1420 io_apic_setup_irq_pin(irq, node, &attr);
1424 static void __init setup_IO_APIC_irqs(void)
1426 unsigned int ioapic_idx;
1428 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1430 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1431 __io_apic_setup_irqs(ioapic_idx);
1435 * for the gsit that is not in first ioapic
1436 * but could not use acpi_register_gsi()
1437 * like some special sci in IBM x3330
1439 void setup_IO_APIC_irq_extra(u32 gsi)
1441 int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0);
1442 struct io_apic_irq_attr attr;
1445 * Convert 'gsi' to 'ioapic.pin'.
1447 ioapic_idx = mp_find_ioapic(gsi);
1451 pin = mp_find_ioapic_pin(ioapic_idx, gsi);
1452 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1456 irq = pin_2_irq(idx, ioapic_idx, pin);
1458 /* Only handle the non legacy irqs on secondary ioapics */
1459 if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY)
1462 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1465 io_apic_setup_irq_pin_once(irq, node, &attr);
1469 * Set up the timer pin, possibly with the 8259A-master behind.
1471 static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
1472 unsigned int pin, int vector)
1474 struct IO_APIC_route_entry entry;
1476 if (irq_remapping_enabled)
1479 memset(&entry, 0, sizeof(entry));
1482 * We use logical delivery to get the timer IRQ
1485 entry.dest_mode = apic->irq_dest_mode;
1486 entry.mask = 0; /* don't mask IRQ for edge */
1487 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1488 entry.delivery_mode = apic->irq_delivery_mode;
1491 entry.vector = vector;
1494 * The timer IRQ doesn't have to know that behind the
1495 * scene we may have a 8259A-master in AEOI mode ...
1497 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1501 * Add it to the IO-APIC irq-routing table:
1503 ioapic_write_entry(ioapic_idx, pin, entry);
1506 __apicdebuginit(void) print_IO_APIC(int ioapic_idx)
1509 union IO_APIC_reg_00 reg_00;
1510 union IO_APIC_reg_01 reg_01;
1511 union IO_APIC_reg_02 reg_02;
1512 union IO_APIC_reg_03 reg_03;
1513 unsigned long flags;
1515 raw_spin_lock_irqsave(&ioapic_lock, flags);
1516 reg_00.raw = io_apic_read(ioapic_idx, 0);
1517 reg_01.raw = io_apic_read(ioapic_idx, 1);
1518 if (reg_01.bits.version >= 0x10)
1519 reg_02.raw = io_apic_read(ioapic_idx, 2);
1520 if (reg_01.bits.version >= 0x20)
1521 reg_03.raw = io_apic_read(ioapic_idx, 3);
1522 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1524 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1525 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1526 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1527 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1528 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1530 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1531 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1532 reg_01.bits.entries);
1534 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1535 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1536 reg_01.bits.version);
1539 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1540 * but the value of reg_02 is read as the previous read register
1541 * value, so ignore it if reg_02 == reg_01.
1543 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1544 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1545 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1549 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1550 * or reg_03, but the value of reg_0[23] is read as the previous read
1551 * register value, so ignore it if reg_03 == reg_0[12].
1553 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1554 reg_03.raw != reg_01.raw) {
1555 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1556 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1559 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1561 if (irq_remapping_enabled) {
1562 printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR"
1563 " Pol Stat Indx2 Zero Vect:\n");
1565 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1566 " Stat Dmod Deli Vect:\n");
1569 for (i = 0; i <= reg_01.bits.entries; i++) {
1570 if (irq_remapping_enabled) {
1571 struct IO_APIC_route_entry entry;
1572 struct IR_IO_APIC_route_entry *ir_entry;
1574 entry = ioapic_read_entry(ioapic_idx, i);
1575 ir_entry = (struct IR_IO_APIC_route_entry *) &entry;
1576 printk(KERN_DEBUG " %02x %04X ",
1580 pr_cont("%1d %1d %1d %1d %1d "
1581 "%1d %1d %X %02X\n",
1587 ir_entry->delivery_status,
1593 struct IO_APIC_route_entry entry;
1595 entry = ioapic_read_entry(ioapic_idx, i);
1596 printk(KERN_DEBUG " %02x %02X ",
1600 pr_cont("%1d %1d %1d %1d %1d "
1606 entry.delivery_status,
1608 entry.delivery_mode,
1615 __apicdebuginit(void) print_IO_APICs(void)
1618 struct irq_cfg *cfg;
1620 struct irq_chip *chip;
1622 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1623 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1624 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1625 mpc_ioapic_id(ioapic_idx),
1626 ioapics[ioapic_idx].nr_registers);
1629 * We are a bit conservative about what we expect. We have to
1630 * know about every hardware change ASAP.
1632 printk(KERN_INFO "testing the IO APIC.......................\n");
1634 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1635 print_IO_APIC(ioapic_idx);
1637 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1638 for_each_active_irq(irq) {
1639 struct irq_pin_list *entry;
1641 chip = irq_get_chip(irq);
1642 if (chip != &ioapic_chip)
1645 cfg = irq_get_chip_data(irq);
1648 entry = cfg->irq_2_pin;
1651 printk(KERN_DEBUG "IRQ%d ", irq);
1652 for_each_irq_pin(entry, cfg->irq_2_pin)
1653 pr_cont("-> %d:%d", entry->apic, entry->pin);
1657 printk(KERN_INFO ".................................... done.\n");
1660 __apicdebuginit(void) print_APIC_field(int base)
1666 for (i = 0; i < 8; i++)
1667 pr_cont("%08x", apic_read(base + i*0x10));
1672 __apicdebuginit(void) print_local_APIC(void *dummy)
1674 unsigned int i, v, ver, maxlvt;
1677 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1678 smp_processor_id(), hard_smp_processor_id());
1679 v = apic_read(APIC_ID);
1680 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1681 v = apic_read(APIC_LVR);
1682 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1683 ver = GET_APIC_VERSION(v);
1684 maxlvt = lapic_get_maxlvt();
1686 v = apic_read(APIC_TASKPRI);
1687 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1689 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1690 if (!APIC_XAPIC(ver)) {
1691 v = apic_read(APIC_ARBPRI);
1692 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1693 v & APIC_ARBPRI_MASK);
1695 v = apic_read(APIC_PROCPRI);
1696 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1700 * Remote read supported only in the 82489DX and local APIC for
1701 * Pentium processors.
1703 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1704 v = apic_read(APIC_RRR);
1705 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1708 v = apic_read(APIC_LDR);
1709 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1710 if (!x2apic_enabled()) {
1711 v = apic_read(APIC_DFR);
1712 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1714 v = apic_read(APIC_SPIV);
1715 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1717 printk(KERN_DEBUG "... APIC ISR field:\n");
1718 print_APIC_field(APIC_ISR);
1719 printk(KERN_DEBUG "... APIC TMR field:\n");
1720 print_APIC_field(APIC_TMR);
1721 printk(KERN_DEBUG "... APIC IRR field:\n");
1722 print_APIC_field(APIC_IRR);
1724 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1725 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1726 apic_write(APIC_ESR, 0);
1728 v = apic_read(APIC_ESR);
1729 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1732 icr = apic_icr_read();
1733 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1734 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1736 v = apic_read(APIC_LVTT);
1737 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1739 if (maxlvt > 3) { /* PC is LVT#4. */
1740 v = apic_read(APIC_LVTPC);
1741 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1743 v = apic_read(APIC_LVT0);
1744 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1745 v = apic_read(APIC_LVT1);
1746 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1748 if (maxlvt > 2) { /* ERR is LVT#3. */
1749 v = apic_read(APIC_LVTERR);
1750 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1753 v = apic_read(APIC_TMICT);
1754 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1755 v = apic_read(APIC_TMCCT);
1756 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1757 v = apic_read(APIC_TDCR);
1758 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1760 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1761 v = apic_read(APIC_EFEAT);
1762 maxlvt = (v >> 16) & 0xff;
1763 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1764 v = apic_read(APIC_ECTRL);
1765 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1766 for (i = 0; i < maxlvt; i++) {
1767 v = apic_read(APIC_EILVTn(i));
1768 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1774 __apicdebuginit(void) print_local_APICs(int maxcpu)
1782 for_each_online_cpu(cpu) {
1785 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1790 __apicdebuginit(void) print_PIC(void)
1793 unsigned long flags;
1795 if (!legacy_pic->nr_legacy_irqs)
1798 printk(KERN_DEBUG "\nprinting PIC contents\n");
1800 raw_spin_lock_irqsave(&i8259A_lock, flags);
1802 v = inb(0xa1) << 8 | inb(0x21);
1803 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1805 v = inb(0xa0) << 8 | inb(0x20);
1806 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1810 v = inb(0xa0) << 8 | inb(0x20);
1814 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1816 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1818 v = inb(0x4d1) << 8 | inb(0x4d0);
1819 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1822 static int __initdata show_lapic = 1;
1823 static __init int setup_show_lapic(char *arg)
1827 if (strcmp(arg, "all") == 0) {
1828 show_lapic = CONFIG_NR_CPUS;
1830 get_option(&arg, &num);
1837 __setup("show_lapic=", setup_show_lapic);
1839 __apicdebuginit(int) print_ICs(void)
1841 if (apic_verbosity == APIC_QUIET)
1846 /* don't print out if apic is not there */
1847 if (!cpu_has_apic && !apic_from_smp_config())
1850 print_local_APICs(show_lapic);
1856 late_initcall(print_ICs);
1859 /* Where if anywhere is the i8259 connect in external int mode */
1860 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1862 void __init enable_IO_APIC(void)
1864 int i8259_apic, i8259_pin;
1867 if (!legacy_pic->nr_legacy_irqs)
1870 for(apic = 0; apic < nr_ioapics; apic++) {
1872 /* See if any of the pins is in ExtINT mode */
1873 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1874 struct IO_APIC_route_entry entry;
1875 entry = ioapic_read_entry(apic, pin);
1877 /* If the interrupt line is enabled and in ExtInt mode
1878 * I have found the pin where the i8259 is connected.
1880 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1881 ioapic_i8259.apic = apic;
1882 ioapic_i8259.pin = pin;
1888 /* Look to see what if the MP table has reported the ExtINT */
1889 /* If we could not find the appropriate pin by looking at the ioapic
1890 * the i8259 probably is not connected the ioapic but give the
1891 * mptable a chance anyway.
1893 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1894 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1895 /* Trust the MP table if nothing is setup in the hardware */
1896 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1897 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1898 ioapic_i8259.pin = i8259_pin;
1899 ioapic_i8259.apic = i8259_apic;
1901 /* Complain if the MP table and the hardware disagree */
1902 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1903 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1905 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1909 * Do not trust the IO-APIC being empty at bootup
1915 * Not an __init, needed by the reboot code
1917 void disable_IO_APIC(void)
1920 * Clear the IO-APIC before rebooting:
1924 if (!legacy_pic->nr_legacy_irqs)
1928 * If the i8259 is routed through an IOAPIC
1929 * Put that IOAPIC in virtual wire mode
1930 * so legacy interrupts can be delivered.
1932 * With interrupt-remapping, for now we will use virtual wire A mode,
1933 * as virtual wire B is little complex (need to configure both
1934 * IOAPIC RTE as well as interrupt-remapping table entry).
1935 * As this gets called during crash dump, keep this simple for now.
1937 if (ioapic_i8259.pin != -1 && !irq_remapping_enabled) {
1938 struct IO_APIC_route_entry entry;
1940 memset(&entry, 0, sizeof(entry));
1941 entry.mask = 0; /* Enabled */
1942 entry.trigger = 0; /* Edge */
1944 entry.polarity = 0; /* High */
1945 entry.delivery_status = 0;
1946 entry.dest_mode = 0; /* Physical */
1947 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1949 entry.dest = read_apic_id();
1952 * Add it to the IO-APIC irq-routing table:
1954 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1958 * Use virtual wire A mode when interrupt remapping is enabled.
1960 if (cpu_has_apic || apic_from_smp_config())
1961 disconnect_bsp_APIC(!irq_remapping_enabled &&
1962 ioapic_i8259.pin != -1);
1965 #ifdef CONFIG_X86_32
1967 * function to set the IO-APIC physical IDs based on the
1968 * values stored in the MPC table.
1970 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1972 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1974 union IO_APIC_reg_00 reg_00;
1975 physid_mask_t phys_id_present_map;
1978 unsigned char old_id;
1979 unsigned long flags;
1982 * This is broken; anything with a real cpu count has to
1983 * circumvent this idiocy regardless.
1985 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1988 * Set the IOAPIC ID to the value stored in the MPC table.
1990 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
1991 /* Read the register 0 value */
1992 raw_spin_lock_irqsave(&ioapic_lock, flags);
1993 reg_00.raw = io_apic_read(ioapic_idx, 0);
1994 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1996 old_id = mpc_ioapic_id(ioapic_idx);
1998 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1999 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2000 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2001 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2003 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
2007 * Sanity check, is the ID really free? Every APIC in a
2008 * system must have a unique ID or we get lots of nice
2009 * 'stuck on smp_invalidate_needed IPI wait' messages.
2011 if (apic->check_apicid_used(&phys_id_present_map,
2012 mpc_ioapic_id(ioapic_idx))) {
2013 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2014 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2015 for (i = 0; i < get_physical_broadcast(); i++)
2016 if (!physid_isset(i, phys_id_present_map))
2018 if (i >= get_physical_broadcast())
2019 panic("Max APIC ID exceeded!\n");
2020 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2022 physid_set(i, phys_id_present_map);
2023 ioapics[ioapic_idx].mp_config.apicid = i;
2026 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
2028 apic_printk(APIC_VERBOSE, "Setting %d in the "
2029 "phys_id_present_map\n",
2030 mpc_ioapic_id(ioapic_idx));
2031 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2035 * We need to adjust the IRQ routing table
2036 * if the ID changed.
2038 if (old_id != mpc_ioapic_id(ioapic_idx))
2039 for (i = 0; i < mp_irq_entries; i++)
2040 if (mp_irqs[i].dstapic == old_id)
2042 = mpc_ioapic_id(ioapic_idx);
2045 * Update the ID register according to the right value
2046 * from the MPC table if they are different.
2048 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
2051 apic_printk(APIC_VERBOSE, KERN_INFO
2052 "...changing IO-APIC physical APIC ID to %d ...",
2053 mpc_ioapic_id(ioapic_idx));
2055 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2056 raw_spin_lock_irqsave(&ioapic_lock, flags);
2057 io_apic_write(ioapic_idx, 0, reg_00.raw);
2058 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2063 raw_spin_lock_irqsave(&ioapic_lock, flags);
2064 reg_00.raw = io_apic_read(ioapic_idx, 0);
2065 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2066 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
2067 pr_cont("could not set ID!\n");
2069 apic_printk(APIC_VERBOSE, " ok.\n");
2073 void __init setup_ioapic_ids_from_mpc(void)
2079 * Don't check I/O APIC IDs for xAPIC systems. They have
2080 * no meaning without the serial APIC bus.
2082 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2083 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2085 setup_ioapic_ids_from_mpc_nocheck();
2089 int no_timer_check __initdata;
2091 static int __init notimercheck(char *s)
2096 __setup("no_timer_check", notimercheck);
2099 * There is a nasty bug in some older SMP boards, their mptable lies
2100 * about the timer IRQ. We do the following to work around the situation:
2102 * - timer IRQ defaults to IO-APIC IRQ
2103 * - if this function detects that timer IRQs are defunct, then we fall
2104 * back to ISA timer IRQs
2106 static int __init timer_irq_works(void)
2108 unsigned long t1 = jiffies;
2109 unsigned long flags;
2114 local_save_flags(flags);
2116 /* Let ten ticks pass... */
2117 mdelay((10 * 1000) / HZ);
2118 local_irq_restore(flags);
2121 * Expect a few ticks at least, to be sure some possible
2122 * glue logic does not lock up after one or two first
2123 * ticks in a non-ExtINT mode. Also the local APIC
2124 * might have cached one ExtINT interrupt. Finally, at
2125 * least one tick may be lost due to delays.
2129 if (time_after(jiffies, t1 + 4))
2135 * In the SMP+IOAPIC case it might happen that there are an unspecified
2136 * number of pending IRQ events unhandled. These cases are very rare,
2137 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2138 * better to do it this way as thus we do not have to be aware of
2139 * 'pending' interrupts in the IRQ path, except at this point.
2142 * Edge triggered needs to resend any interrupt
2143 * that was delayed but this is now handled in the device
2148 * Starting up a edge-triggered IO-APIC interrupt is
2149 * nasty - we need to make sure that we get the edge.
2150 * If it is already asserted for some reason, we need
2151 * return 1 to indicate that is was pending.
2153 * This is not complete - we should be able to fake
2154 * an edge even if it isn't on the 8259A...
2157 static unsigned int startup_ioapic_irq(struct irq_data *data)
2159 int was_pending = 0, irq = data->irq;
2160 unsigned long flags;
2162 raw_spin_lock_irqsave(&ioapic_lock, flags);
2163 if (irq < legacy_pic->nr_legacy_irqs) {
2164 legacy_pic->mask(irq);
2165 if (legacy_pic->irq_pending(irq))
2168 __unmask_ioapic(data->chip_data);
2169 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2174 static int ioapic_retrigger_irq(struct irq_data *data)
2176 struct irq_cfg *cfg = data->chip_data;
2177 unsigned long flags;
2179 raw_spin_lock_irqsave(&vector_lock, flags);
2180 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2181 raw_spin_unlock_irqrestore(&vector_lock, flags);
2187 * Level and edge triggered IO-APIC interrupts need different handling,
2188 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2189 * handled with the level-triggered descriptor, but that one has slightly
2190 * more overhead. Level-triggered interrupts cannot be handled with the
2191 * edge-triggered handler, without risking IRQ storms and other ugly
2196 void send_cleanup_vector(struct irq_cfg *cfg)
2198 cpumask_var_t cleanup_mask;
2200 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2202 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2203 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2205 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2206 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2207 free_cpumask_var(cleanup_mask);
2209 cfg->move_in_progress = 0;
2212 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2215 struct irq_pin_list *entry;
2216 u8 vector = cfg->vector;
2218 for_each_irq_pin(entry, cfg->irq_2_pin) {
2224 * With interrupt-remapping, destination information comes
2225 * from interrupt-remapping table entry.
2227 if (!irq_remapped(cfg))
2228 io_apic_write(apic, 0x11 + pin*2, dest);
2229 reg = io_apic_read(apic, 0x10 + pin*2);
2230 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2232 io_apic_modify(apic, 0x10 + pin*2, reg);
2237 * Either sets data->affinity to a valid value, and returns
2238 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2239 * leaves data->affinity untouched.
2241 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2242 unsigned int *dest_id)
2244 struct irq_cfg *cfg = data->chip_data;
2246 if (!cpumask_intersects(mask, cpu_online_mask))
2249 if (assign_irq_vector(data->irq, data->chip_data, mask))
2252 cpumask_copy(data->affinity, mask);
2254 *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain);
2259 ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2262 unsigned int dest, irq = data->irq;
2263 unsigned long flags;
2266 raw_spin_lock_irqsave(&ioapic_lock, flags);
2267 ret = __ioapic_set_affinity(data, mask, &dest);
2269 /* Only the high 8 bits are valid. */
2270 dest = SET_APIC_LOGICAL_ID(dest);
2271 __target_IO_APIC_irq(irq, dest, data->chip_data);
2273 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2277 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2279 unsigned vector, me;
2285 me = smp_processor_id();
2286 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2289 struct irq_desc *desc;
2290 struct irq_cfg *cfg;
2291 irq = __this_cpu_read(vector_irq[vector]);
2296 desc = irq_to_desc(irq);
2301 raw_spin_lock(&desc->lock);
2304 * Check if the irq migration is in progress. If so, we
2305 * haven't received the cleanup request yet for this irq.
2307 if (cfg->move_in_progress)
2310 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2313 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2315 * Check if the vector that needs to be cleanedup is
2316 * registered at the cpu's IRR. If so, then this is not
2317 * the best time to clean it up. Lets clean it up in the
2318 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2321 if (irr & (1 << (vector % 32))) {
2322 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2325 __this_cpu_write(vector_irq[vector], -1);
2327 raw_spin_unlock(&desc->lock);
2333 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2337 if (likely(!cfg->move_in_progress))
2340 me = smp_processor_id();
2342 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2343 send_cleanup_vector(cfg);
2346 static void irq_complete_move(struct irq_cfg *cfg)
2348 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2351 void irq_force_complete_move(int irq)
2353 struct irq_cfg *cfg = irq_get_chip_data(irq);
2358 __irq_complete_move(cfg, cfg->vector);
2361 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2364 static void ack_apic_edge(struct irq_data *data)
2366 irq_complete_move(data->chip_data);
2371 atomic_t irq_mis_count;
2373 #ifdef CONFIG_GENERIC_PENDING_IRQ
2374 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
2376 struct irq_pin_list *entry;
2377 unsigned long flags;
2379 raw_spin_lock_irqsave(&ioapic_lock, flags);
2380 for_each_irq_pin(entry, cfg->irq_2_pin) {
2385 reg = io_apic_read(entry->apic, 0x10 + pin*2);
2386 /* Is the remote IRR bit set? */
2387 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
2388 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2392 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2397 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2399 /* If we are moving the irq we need to mask it */
2400 if (unlikely(irqd_is_setaffinity_pending(data))) {
2407 static inline void ioapic_irqd_unmask(struct irq_data *data,
2408 struct irq_cfg *cfg, bool masked)
2410 if (unlikely(masked)) {
2411 /* Only migrate the irq if the ack has been received.
2413 * On rare occasions the broadcast level triggered ack gets
2414 * delayed going to ioapics, and if we reprogram the
2415 * vector while Remote IRR is still set the irq will never
2418 * To prevent this scenario we read the Remote IRR bit
2419 * of the ioapic. This has two effects.
2420 * - On any sane system the read of the ioapic will
2421 * flush writes (and acks) going to the ioapic from
2423 * - We get to see if the ACK has actually been delivered.
2425 * Based on failed experiments of reprogramming the
2426 * ioapic entry from outside of irq context starting
2427 * with masking the ioapic entry and then polling until
2428 * Remote IRR was clear before reprogramming the
2429 * ioapic I don't trust the Remote IRR bit to be
2430 * completey accurate.
2432 * However there appears to be no other way to plug
2433 * this race, so if the Remote IRR bit is not
2434 * accurate and is causing problems then it is a hardware bug
2435 * and you can go talk to the chipset vendor about it.
2437 if (!io_apic_level_ack_pending(cfg))
2438 irq_move_masked_irq(data);
2443 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg)
2447 static inline void ioapic_irqd_unmask(struct irq_data *data,
2448 struct irq_cfg *cfg, bool masked)
2453 static void ack_apic_level(struct irq_data *data)
2455 struct irq_cfg *cfg = data->chip_data;
2456 int i, irq = data->irq;
2460 irq_complete_move(cfg);
2461 masked = ioapic_irqd_mask(data, cfg);
2464 * It appears there is an erratum which affects at least version 0x11
2465 * of I/O APIC (that's the 82093AA and cores integrated into various
2466 * chipsets). Under certain conditions a level-triggered interrupt is
2467 * erroneously delivered as edge-triggered one but the respective IRR
2468 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2469 * message but it will never arrive and further interrupts are blocked
2470 * from the source. The exact reason is so far unknown, but the
2471 * phenomenon was observed when two consecutive interrupt requests
2472 * from a given source get delivered to the same CPU and the source is
2473 * temporarily disabled in between.
2475 * A workaround is to simulate an EOI message manually. We achieve it
2476 * by setting the trigger mode to edge and then to level when the edge
2477 * trigger mode gets detected in the TMR of a local APIC for a
2478 * level-triggered interrupt. We mask the source for the time of the
2479 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2480 * The idea is from Manfred Spraul. --macro
2482 * Also in the case when cpu goes offline, fixup_irqs() will forward
2483 * any unhandled interrupt on the offlined cpu to the new cpu
2484 * destination that is handling the corresponding interrupt. This
2485 * interrupt forwarding is done via IPI's. Hence, in this case also
2486 * level-triggered io-apic interrupt will be seen as an edge
2487 * interrupt in the IRR. And we can't rely on the cpu's EOI
2488 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2489 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2490 * supporting EOI register, we do an explicit EOI to clear the
2491 * remote IRR and on IO-APIC's which don't have an EOI register,
2492 * we use the above logic (mask+edge followed by unmask+level) from
2493 * Manfred Spraul to clear the remote IRR.
2496 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2499 * We must acknowledge the irq before we move it or the acknowledge will
2500 * not propagate properly.
2505 * Tail end of clearing remote IRR bit (either by delivering the EOI
2506 * message via io-apic EOI register write or simulating it using
2507 * mask+edge followed by unnask+level logic) manually when the
2508 * level triggered interrupt is seen as the edge triggered interrupt
2511 if (!(v & (1 << (i & 0x1f)))) {
2512 atomic_inc(&irq_mis_count);
2514 eoi_ioapic_irq(irq, cfg);
2517 ioapic_irqd_unmask(data, cfg, masked);
2520 #ifdef CONFIG_IRQ_REMAP
2521 static void ir_ack_apic_edge(struct irq_data *data)
2526 static void ir_ack_apic_level(struct irq_data *data)
2529 eoi_ioapic_irq(data->irq, data->chip_data);
2532 static void ir_print_prefix(struct irq_data *data, struct seq_file *p)
2534 seq_printf(p, " IR-%s", data->chip->name);
2537 static void irq_remap_modify_chip_defaults(struct irq_chip *chip)
2539 chip->irq_print_chip = ir_print_prefix;
2540 chip->irq_ack = ir_ack_apic_edge;
2541 chip->irq_eoi = ir_ack_apic_level;
2544 chip->irq_set_affinity = set_remapped_irq_affinity;
2547 #endif /* CONFIG_IRQ_REMAP */
2549 static struct irq_chip ioapic_chip __read_mostly = {
2551 .irq_startup = startup_ioapic_irq,
2552 .irq_mask = mask_ioapic_irq,
2553 .irq_unmask = unmask_ioapic_irq,
2554 .irq_ack = ack_apic_edge,
2555 .irq_eoi = ack_apic_level,
2557 .irq_set_affinity = ioapic_set_affinity,
2559 .irq_retrigger = ioapic_retrigger_irq,
2562 static inline void init_IO_APIC_traps(void)
2564 struct irq_cfg *cfg;
2568 * NOTE! The local APIC isn't very good at handling
2569 * multiple interrupts at the same interrupt level.
2570 * As the interrupt level is determined by taking the
2571 * vector number and shifting that right by 4, we
2572 * want to spread these out a bit so that they don't
2573 * all fall in the same interrupt level.
2575 * Also, we've got to be careful not to trash gate
2576 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2578 for_each_active_irq(irq) {
2579 cfg = irq_get_chip_data(irq);
2580 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2582 * Hmm.. We don't have an entry for this,
2583 * so default to an old-fashioned 8259
2584 * interrupt if we can..
2586 if (irq < legacy_pic->nr_legacy_irqs)
2587 legacy_pic->make_irq(irq);
2589 /* Strange. Oh, well.. */
2590 irq_set_chip(irq, &no_irq_chip);
2596 * The local APIC irq-chip implementation:
2599 static void mask_lapic_irq(struct irq_data *data)
2603 v = apic_read(APIC_LVT0);
2604 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2607 static void unmask_lapic_irq(struct irq_data *data)
2611 v = apic_read(APIC_LVT0);
2612 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2615 static void ack_lapic_irq(struct irq_data *data)
2620 static struct irq_chip lapic_chip __read_mostly = {
2621 .name = "local-APIC",
2622 .irq_mask = mask_lapic_irq,
2623 .irq_unmask = unmask_lapic_irq,
2624 .irq_ack = ack_lapic_irq,
2627 static void lapic_register_intr(int irq)
2629 irq_clear_status_flags(irq, IRQ_LEVEL);
2630 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2635 * This looks a bit hackish but it's about the only one way of sending
2636 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2637 * not support the ExtINT mode, unfortunately. We need to send these
2638 * cycles as some i82489DX-based boards have glue logic that keeps the
2639 * 8259A interrupt line asserted until INTA. --macro
2641 static inline void __init unlock_ExtINT_logic(void)
2644 struct IO_APIC_route_entry entry0, entry1;
2645 unsigned char save_control, save_freq_select;
2647 pin = find_isa_irq_pin(8, mp_INT);
2652 apic = find_isa_irq_apic(8, mp_INT);
2658 entry0 = ioapic_read_entry(apic, pin);
2659 clear_IO_APIC_pin(apic, pin);
2661 memset(&entry1, 0, sizeof(entry1));
2663 entry1.dest_mode = 0; /* physical delivery */
2664 entry1.mask = 0; /* unmask IRQ now */
2665 entry1.dest = hard_smp_processor_id();
2666 entry1.delivery_mode = dest_ExtINT;
2667 entry1.polarity = entry0.polarity;
2671 ioapic_write_entry(apic, pin, entry1);
2673 save_control = CMOS_READ(RTC_CONTROL);
2674 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2675 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2677 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2682 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2686 CMOS_WRITE(save_control, RTC_CONTROL);
2687 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2688 clear_IO_APIC_pin(apic, pin);
2690 ioapic_write_entry(apic, pin, entry0);
2693 static int disable_timer_pin_1 __initdata;
2694 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2695 static int __init disable_timer_pin_setup(char *arg)
2697 disable_timer_pin_1 = 1;
2700 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2702 int timer_through_8259 __initdata;
2705 * This code may look a bit paranoid, but it's supposed to cooperate with
2706 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2707 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2708 * fanatically on his truly buggy board.
2710 * FIXME: really need to revamp this for all platforms.
2712 static inline void __init check_timer(void)
2714 struct irq_cfg *cfg = irq_get_chip_data(0);
2715 int node = cpu_to_node(0);
2716 int apic1, pin1, apic2, pin2;
2717 unsigned long flags;
2720 local_irq_save(flags);
2723 * get/set the timer IRQ vector:
2725 legacy_pic->mask(0);
2726 assign_irq_vector(0, cfg, apic->target_cpus());
2729 * As IRQ0 is to be enabled in the 8259A, the virtual
2730 * wire has to be disabled in the local APIC. Also
2731 * timer interrupts need to be acknowledged manually in
2732 * the 8259A for the i82489DX when using the NMI
2733 * watchdog as that APIC treats NMIs as level-triggered.
2734 * The AEOI mode will finish them in the 8259A
2737 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2738 legacy_pic->init(1);
2740 pin1 = find_isa_irq_pin(0, mp_INT);
2741 apic1 = find_isa_irq_apic(0, mp_INT);
2742 pin2 = ioapic_i8259.pin;
2743 apic2 = ioapic_i8259.apic;
2745 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2746 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2747 cfg->vector, apic1, pin1, apic2, pin2);
2750 * Some BIOS writers are clueless and report the ExtINTA
2751 * I/O APIC input from the cascaded 8259A as the timer
2752 * interrupt input. So just in case, if only one pin
2753 * was found above, try it both directly and through the
2757 if (irq_remapping_enabled)
2758 panic("BIOS bug: timer not connected to IO-APIC");
2762 } else if (pin2 == -1) {
2769 * Ok, does IRQ0 through the IOAPIC work?
2772 add_pin_to_irq_node(cfg, node, apic1, pin1);
2773 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2775 /* for edge trigger, setup_ioapic_irq already
2776 * leave it unmasked.
2777 * so only need to unmask if it is level-trigger
2778 * do we really have level trigger timer?
2781 idx = find_irq_entry(apic1, pin1, mp_INT);
2782 if (idx != -1 && irq_trigger(idx))
2785 if (timer_irq_works()) {
2786 if (disable_timer_pin_1 > 0)
2787 clear_IO_APIC_pin(0, pin1);
2790 if (irq_remapping_enabled)
2791 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2792 local_irq_disable();
2793 clear_IO_APIC_pin(apic1, pin1);
2795 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2796 "8254 timer not connected to IO-APIC\n");
2798 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2799 "(IRQ0) through the 8259A ...\n");
2800 apic_printk(APIC_QUIET, KERN_INFO
2801 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2803 * legacy devices should be connected to IO APIC #0
2805 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2806 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2807 legacy_pic->unmask(0);
2808 if (timer_irq_works()) {
2809 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2810 timer_through_8259 = 1;
2814 * Cleanup, just in case ...
2816 local_irq_disable();
2817 legacy_pic->mask(0);
2818 clear_IO_APIC_pin(apic2, pin2);
2819 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2822 apic_printk(APIC_QUIET, KERN_INFO
2823 "...trying to set up timer as Virtual Wire IRQ...\n");
2825 lapic_register_intr(0);
2826 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2827 legacy_pic->unmask(0);
2829 if (timer_irq_works()) {
2830 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2833 local_irq_disable();
2834 legacy_pic->mask(0);
2835 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2836 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2838 apic_printk(APIC_QUIET, KERN_INFO
2839 "...trying to set up timer as ExtINT IRQ...\n");
2841 legacy_pic->init(0);
2842 legacy_pic->make_irq(0);
2843 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2845 unlock_ExtINT_logic();
2847 if (timer_irq_works()) {
2848 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2851 local_irq_disable();
2852 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2853 if (x2apic_preenabled)
2854 apic_printk(APIC_QUIET, KERN_INFO
2855 "Perhaps problem with the pre-enabled x2apic mode\n"
2856 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2857 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2858 "report. Then try booting with the 'noapic' option.\n");
2860 local_irq_restore(flags);
2864 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2865 * to devices. However there may be an I/O APIC pin available for
2866 * this interrupt regardless. The pin may be left unconnected, but
2867 * typically it will be reused as an ExtINT cascade interrupt for
2868 * the master 8259A. In the MPS case such a pin will normally be
2869 * reported as an ExtINT interrupt in the MP table. With ACPI
2870 * there is no provision for ExtINT interrupts, and in the absence
2871 * of an override it would be treated as an ordinary ISA I/O APIC
2872 * interrupt, that is edge-triggered and unmasked by default. We
2873 * used to do this, but it caused problems on some systems because
2874 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2875 * the same ExtINT cascade interrupt to drive the local APIC of the
2876 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2877 * the I/O APIC in all cases now. No actual device should request
2878 * it anyway. --macro
2880 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2882 void __init setup_IO_APIC(void)
2886 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2888 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
2890 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2892 * Set up IO-APIC IRQ routing.
2894 x86_init.mpparse.setup_ioapic_ids();
2897 setup_IO_APIC_irqs();
2898 init_IO_APIC_traps();
2899 if (legacy_pic->nr_legacy_irqs)
2904 * Called after all the initialization is done. If we didn't find any
2905 * APIC bugs then we can allow the modify fast path
2908 static int __init io_apic_bug_finalize(void)
2910 if (sis_apic_bug == -1)
2915 late_initcall(io_apic_bug_finalize);
2917 static void resume_ioapic_id(int ioapic_idx)
2919 unsigned long flags;
2920 union IO_APIC_reg_00 reg_00;
2922 raw_spin_lock_irqsave(&ioapic_lock, flags);
2923 reg_00.raw = io_apic_read(ioapic_idx, 0);
2924 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2925 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2926 io_apic_write(ioapic_idx, 0, reg_00.raw);
2928 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2931 static void ioapic_resume(void)
2935 for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--)
2936 resume_ioapic_id(ioapic_idx);
2938 restore_ioapic_entries();
2941 static struct syscore_ops ioapic_syscore_ops = {
2942 .suspend = save_ioapic_entries,
2943 .resume = ioapic_resume,
2946 static int __init ioapic_init_ops(void)
2948 register_syscore_ops(&ioapic_syscore_ops);
2953 device_initcall(ioapic_init_ops);
2956 * Dynamic irq allocate and deallocation
2958 unsigned int create_irq_nr(unsigned int from, int node)
2960 struct irq_cfg *cfg;
2961 unsigned long flags;
2962 unsigned int ret = 0;
2965 if (from < nr_irqs_gsi)
2968 irq = alloc_irq_from(from, node);
2971 cfg = alloc_irq_cfg(irq, node);
2973 free_irq_at(irq, NULL);
2977 raw_spin_lock_irqsave(&vector_lock, flags);
2978 if (!__assign_irq_vector(irq, cfg, apic->target_cpus()))
2980 raw_spin_unlock_irqrestore(&vector_lock, flags);
2983 irq_set_chip_data(irq, cfg);
2984 irq_clear_status_flags(irq, IRQ_NOREQUEST);
2986 free_irq_at(irq, cfg);
2991 int create_irq(void)
2993 int node = cpu_to_node(0);
2994 unsigned int irq_want;
2997 irq_want = nr_irqs_gsi;
2998 irq = create_irq_nr(irq_want, node);
3006 void destroy_irq(unsigned int irq)
3008 struct irq_cfg *cfg = irq_get_chip_data(irq);
3009 unsigned long flags;
3011 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
3013 if (irq_remapped(cfg))
3014 free_remapped_irq(irq);
3015 raw_spin_lock_irqsave(&vector_lock, flags);
3016 __clear_irq_vector(irq, cfg);
3017 raw_spin_unlock_irqrestore(&vector_lock, flags);
3018 free_irq_at(irq, cfg);
3022 * MSI message composition
3024 #ifdef CONFIG_PCI_MSI
3025 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3026 struct msi_msg *msg, u8 hpet_id)
3028 struct irq_cfg *cfg;
3036 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3040 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3042 if (irq_remapped(cfg)) {
3043 compose_remapped_msi_msg(pdev, irq, dest, msg, hpet_id);
3047 if (x2apic_enabled())
3048 msg->address_hi = MSI_ADDR_BASE_HI |
3049 MSI_ADDR_EXT_DEST_ID(dest);
3051 msg->address_hi = MSI_ADDR_BASE_HI;
3055 ((apic->irq_dest_mode == 0) ?
3056 MSI_ADDR_DEST_MODE_PHYSICAL:
3057 MSI_ADDR_DEST_MODE_LOGICAL) |
3058 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3059 MSI_ADDR_REDIRECTION_CPU:
3060 MSI_ADDR_REDIRECTION_LOWPRI) |
3061 MSI_ADDR_DEST_ID(dest);
3064 MSI_DATA_TRIGGER_EDGE |
3065 MSI_DATA_LEVEL_ASSERT |
3066 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3067 MSI_DATA_DELIVERY_FIXED:
3068 MSI_DATA_DELIVERY_LOWPRI) |
3069 MSI_DATA_VECTOR(cfg->vector);
3076 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3078 struct irq_cfg *cfg = data->chip_data;
3082 if (__ioapic_set_affinity(data, mask, &dest))
3085 __get_cached_msi_msg(data->msi_desc, &msg);
3087 msg.data &= ~MSI_DATA_VECTOR_MASK;
3088 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3089 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3090 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3092 __write_msi_msg(data->msi_desc, &msg);
3096 #endif /* CONFIG_SMP */
3099 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3100 * which implement the MSI or MSI-X Capability Structure.
3102 static struct irq_chip msi_chip = {
3104 .irq_unmask = unmask_msi_irq,
3105 .irq_mask = mask_msi_irq,
3106 .irq_ack = ack_apic_edge,
3108 .irq_set_affinity = msi_set_affinity,
3110 .irq_retrigger = ioapic_retrigger_irq,
3113 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3115 struct irq_chip *chip = &msi_chip;
3119 ret = msi_compose_msg(dev, irq, &msg, -1);
3123 irq_set_msi_desc(irq, msidesc);
3124 write_msi_msg(irq, &msg);
3126 if (irq_remapped(irq_get_chip_data(irq))) {
3127 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3128 irq_remap_modify_chip_defaults(chip);
3131 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3133 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3138 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3140 int node, ret, sub_handle, index = 0;
3141 unsigned int irq, irq_want;
3142 struct msi_desc *msidesc;
3144 /* x86 doesn't support multiple MSI yet */
3145 if (type == PCI_CAP_ID_MSI && nvec > 1)
3148 node = dev_to_node(&dev->dev);
3149 irq_want = nr_irqs_gsi;
3151 list_for_each_entry(msidesc, &dev->msi_list, list) {
3152 irq = create_irq_nr(irq_want, node);
3156 if (!irq_remapping_enabled)
3161 * allocate the consecutive block of IRTE's
3164 index = msi_alloc_remapped_irq(dev, irq, nvec);
3170 ret = msi_setup_remapped_irq(dev, irq, index,
3176 ret = setup_msi_irq(dev, msidesc, irq);
3188 void native_teardown_msi_irq(unsigned int irq)
3193 #ifdef CONFIG_DMAR_TABLE
3196 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3199 struct irq_cfg *cfg = data->chip_data;
3200 unsigned int dest, irq = data->irq;
3203 if (__ioapic_set_affinity(data, mask, &dest))
3206 dmar_msi_read(irq, &msg);
3208 msg.data &= ~MSI_DATA_VECTOR_MASK;
3209 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3210 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3211 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3212 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3214 dmar_msi_write(irq, &msg);
3219 #endif /* CONFIG_SMP */
3221 static struct irq_chip dmar_msi_type = {
3223 .irq_unmask = dmar_msi_unmask,
3224 .irq_mask = dmar_msi_mask,
3225 .irq_ack = ack_apic_edge,
3227 .irq_set_affinity = dmar_msi_set_affinity,
3229 .irq_retrigger = ioapic_retrigger_irq,
3232 int arch_setup_dmar_msi(unsigned int irq)
3237 ret = msi_compose_msg(NULL, irq, &msg, -1);
3240 dmar_msi_write(irq, &msg);
3241 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3247 #ifdef CONFIG_HPET_TIMER
3250 static int hpet_msi_set_affinity(struct irq_data *data,
3251 const struct cpumask *mask, bool force)
3253 struct irq_cfg *cfg = data->chip_data;
3257 if (__ioapic_set_affinity(data, mask, &dest))
3260 hpet_msi_read(data->handler_data, &msg);
3262 msg.data &= ~MSI_DATA_VECTOR_MASK;
3263 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3264 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3265 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3267 hpet_msi_write(data->handler_data, &msg);
3272 #endif /* CONFIG_SMP */
3274 static struct irq_chip hpet_msi_type = {
3276 .irq_unmask = hpet_msi_unmask,
3277 .irq_mask = hpet_msi_mask,
3278 .irq_ack = ack_apic_edge,
3280 .irq_set_affinity = hpet_msi_set_affinity,
3282 .irq_retrigger = ioapic_retrigger_irq,
3285 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3287 struct irq_chip *chip = &hpet_msi_type;
3291 if (irq_remapping_enabled) {
3292 if (!setup_hpet_msi_remapped(irq, id))
3296 ret = msi_compose_msg(NULL, irq, &msg, id);
3300 hpet_msi_write(irq_get_handler_data(irq), &msg);
3301 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3302 if (irq_remapped(irq_get_chip_data(irq)))
3303 irq_remap_modify_chip_defaults(chip);
3305 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3310 #endif /* CONFIG_PCI_MSI */
3312 * Hypertransport interrupt support
3314 #ifdef CONFIG_HT_IRQ
3318 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3320 struct ht_irq_msg msg;
3321 fetch_ht_irq_msg(irq, &msg);
3323 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3324 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3326 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3327 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3329 write_ht_irq_msg(irq, &msg);
3333 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3335 struct irq_cfg *cfg = data->chip_data;
3338 if (__ioapic_set_affinity(data, mask, &dest))
3341 target_ht_irq(data->irq, dest, cfg->vector);
3347 static struct irq_chip ht_irq_chip = {
3349 .irq_mask = mask_ht_irq,
3350 .irq_unmask = unmask_ht_irq,
3351 .irq_ack = ack_apic_edge,
3353 .irq_set_affinity = ht_set_affinity,
3355 .irq_retrigger = ioapic_retrigger_irq,
3358 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3360 struct irq_cfg *cfg;
3367 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3369 struct ht_irq_msg msg;
3372 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3373 apic->target_cpus());
3375 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3379 HT_IRQ_LOW_DEST_ID(dest) |
3380 HT_IRQ_LOW_VECTOR(cfg->vector) |
3381 ((apic->irq_dest_mode == 0) ?
3382 HT_IRQ_LOW_DM_PHYSICAL :
3383 HT_IRQ_LOW_DM_LOGICAL) |
3384 HT_IRQ_LOW_RQEOI_EDGE |
3385 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3386 HT_IRQ_LOW_MT_FIXED :
3387 HT_IRQ_LOW_MT_ARBITRATED) |
3388 HT_IRQ_LOW_IRQ_MASKED;
3390 write_ht_irq_msg(irq, &msg);
3392 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3393 handle_edge_irq, "edge");
3395 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3399 #endif /* CONFIG_HT_IRQ */
3402 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3404 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3409 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3411 setup_ioapic_irq(irq, cfg, attr);
3415 int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3416 struct io_apic_irq_attr *attr)
3418 unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin;
3421 /* Avoid redundant programming */
3422 if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) {
3423 pr_debug("Pin %d-%d already programmed\n",
3424 mpc_ioapic_id(ioapic_idx), pin);
3427 ret = io_apic_setup_irq_pin(irq, node, attr);
3429 set_bit(pin, ioapics[ioapic_idx].pin_programmed);
3433 static int __init io_apic_get_redir_entries(int ioapic)
3435 union IO_APIC_reg_01 reg_01;
3436 unsigned long flags;
3438 raw_spin_lock_irqsave(&ioapic_lock, flags);
3439 reg_01.raw = io_apic_read(ioapic, 1);
3440 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3442 /* The register returns the maximum index redir index
3443 * supported, which is one less than the total number of redir
3446 return reg_01.bits.entries + 1;
3449 static void __init probe_nr_irqs_gsi(void)
3453 nr = gsi_top + NR_IRQS_LEGACY;
3454 if (nr > nr_irqs_gsi)
3457 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3460 int get_nr_irqs_gsi(void)
3465 int __init arch_probe_nr_irqs(void)
3469 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3470 nr_irqs = NR_VECTORS * nr_cpu_ids;
3472 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3473 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3475 * for MSI and HT dyn irq
3477 nr += nr_irqs_gsi * 16;
3482 return NR_IRQS_LEGACY;
3485 int io_apic_set_pci_routing(struct device *dev, int irq,
3486 struct io_apic_irq_attr *irq_attr)
3490 if (!IO_APIC_IRQ(irq)) {
3491 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3496 node = dev ? dev_to_node(dev) : cpu_to_node(0);
3498 return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3501 #ifdef CONFIG_X86_32
3502 static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3504 union IO_APIC_reg_00 reg_00;
3505 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3507 unsigned long flags;
3511 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3512 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3513 * supports up to 16 on one shared APIC bus.
3515 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3516 * advantage of new APIC bus architecture.
3519 if (physids_empty(apic_id_map))
3520 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3522 raw_spin_lock_irqsave(&ioapic_lock, flags);
3523 reg_00.raw = io_apic_read(ioapic, 0);
3524 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3526 if (apic_id >= get_physical_broadcast()) {
3527 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3528 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3529 apic_id = reg_00.bits.ID;
3533 * Every APIC in a system must have a unique ID or we get lots of nice
3534 * 'stuck on smp_invalidate_needed IPI wait' messages.
3536 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3538 for (i = 0; i < get_physical_broadcast(); i++) {
3539 if (!apic->check_apicid_used(&apic_id_map, i))
3543 if (i == get_physical_broadcast())
3544 panic("Max apic_id exceeded!\n");
3546 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3547 "trying %d\n", ioapic, apic_id, i);
3552 apic->apicid_to_cpu_present(apic_id, &tmp);
3553 physids_or(apic_id_map, apic_id_map, tmp);
3555 if (reg_00.bits.ID != apic_id) {
3556 reg_00.bits.ID = apic_id;
3558 raw_spin_lock_irqsave(&ioapic_lock, flags);
3559 io_apic_write(ioapic, 0, reg_00.raw);
3560 reg_00.raw = io_apic_read(ioapic, 0);
3561 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3564 if (reg_00.bits.ID != apic_id) {
3565 pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
3571 apic_printk(APIC_VERBOSE, KERN_INFO
3572 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3577 static u8 __init io_apic_unique_id(u8 id)
3579 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3580 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3581 return io_apic_get_unique_id(nr_ioapics, id);
3586 static u8 __init io_apic_unique_id(u8 id)
3589 DECLARE_BITMAP(used, 256);
3591 bitmap_zero(used, 256);
3592 for (i = 0; i < nr_ioapics; i++) {
3593 __set_bit(mpc_ioapic_id(i), used);
3595 if (!test_bit(id, used))
3597 return find_first_zero_bit(used, 256);
3601 static int __init io_apic_get_version(int ioapic)
3603 union IO_APIC_reg_01 reg_01;
3604 unsigned long flags;
3606 raw_spin_lock_irqsave(&ioapic_lock, flags);
3607 reg_01.raw = io_apic_read(ioapic, 1);
3608 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3610 return reg_01.bits.version;
3613 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3615 int ioapic, pin, idx;
3617 if (skip_ioapic_setup)
3620 ioapic = mp_find_ioapic(gsi);
3624 pin = mp_find_ioapic_pin(ioapic, gsi);
3628 idx = find_irq_entry(ioapic, pin, mp_INT);
3632 *trigger = irq_trigger(idx);
3633 *polarity = irq_polarity(idx);
3638 * This function currently is only a helper for the i386 smp boot process where
3639 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3640 * so mask in all cases should simply be apic->target_cpus()
3643 void __init setup_ioapic_dest(void)
3645 int pin, ioapic, irq, irq_entry;
3646 const struct cpumask *mask;
3647 struct irq_data *idata;
3649 if (skip_ioapic_setup == 1)
3652 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3653 for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
3654 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3655 if (irq_entry == -1)
3657 irq = pin_2_irq(irq_entry, ioapic, pin);
3659 if ((ioapic > 0) && (irq > 16))
3662 idata = irq_get_irq_data(irq);
3665 * Honour affinities which have been set in early boot
3667 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3668 mask = idata->affinity;
3670 mask = apic->target_cpus();
3672 if (irq_remapping_enabled)
3673 set_remapped_irq_affinity(idata, mask, false);
3675 ioapic_set_affinity(idata, mask, false);
3681 #define IOAPIC_RESOURCE_NAME_SIZE 11
3683 static struct resource *ioapic_resources;
3685 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3688 struct resource *res;
3692 if (nr_ioapics <= 0)
3695 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3698 mem = alloc_bootmem(n);
3701 mem += sizeof(struct resource) * nr_ioapics;
3703 for (i = 0; i < nr_ioapics; i++) {
3705 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3706 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3707 mem += IOAPIC_RESOURCE_NAME_SIZE;
3710 ioapic_resources = res;
3715 void __init native_io_apic_init_mappings(void)
3717 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3718 struct resource *ioapic_res;
3721 ioapic_res = ioapic_setup_resources(nr_ioapics);
3722 for (i = 0; i < nr_ioapics; i++) {
3723 if (smp_found_config) {
3724 ioapic_phys = mpc_ioapic_addr(i);
3725 #ifdef CONFIG_X86_32
3728 "WARNING: bogus zero IO-APIC "
3729 "address found in MPTABLE, "
3730 "disabling IO/APIC support!\n");
3731 smp_found_config = 0;
3732 skip_ioapic_setup = 1;
3733 goto fake_ioapic_page;
3737 #ifdef CONFIG_X86_32
3740 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3741 ioapic_phys = __pa(ioapic_phys);
3743 set_fixmap_nocache(idx, ioapic_phys);
3744 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3745 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3749 ioapic_res->start = ioapic_phys;
3750 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3754 probe_nr_irqs_gsi();
3757 void __init ioapic_insert_resources(void)
3760 struct resource *r = ioapic_resources;
3765 "IO APIC resources couldn't be allocated.\n");
3769 for (i = 0; i < nr_ioapics; i++) {
3770 insert_resource(&iomem_resource, r);
3775 int mp_find_ioapic(u32 gsi)
3779 if (nr_ioapics == 0)
3782 /* Find the IOAPIC that manages this GSI. */
3783 for (i = 0; i < nr_ioapics; i++) {
3784 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
3785 if ((gsi >= gsi_cfg->gsi_base)
3786 && (gsi <= gsi_cfg->gsi_end))
3790 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3794 int mp_find_ioapic_pin(int ioapic, u32 gsi)
3796 struct mp_ioapic_gsi *gsi_cfg;
3798 if (WARN_ON(ioapic == -1))
3801 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
3802 if (WARN_ON(gsi > gsi_cfg->gsi_end))
3805 return gsi - gsi_cfg->gsi_base;
3808 static __init int bad_ioapic(unsigned long address)
3810 if (nr_ioapics >= MAX_IO_APICS) {
3811 pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
3812 MAX_IO_APICS, nr_ioapics);
3816 pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n");
3822 static __init int bad_ioapic_register(int idx)
3824 union IO_APIC_reg_00 reg_00;
3825 union IO_APIC_reg_01 reg_01;
3826 union IO_APIC_reg_02 reg_02;
3828 reg_00.raw = io_apic_read(idx, 0);
3829 reg_01.raw = io_apic_read(idx, 1);
3830 reg_02.raw = io_apic_read(idx, 2);
3832 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
3833 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
3834 mpc_ioapic_addr(idx));
3841 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
3845 struct mp_ioapic_gsi *gsi_cfg;
3847 if (bad_ioapic(address))
3852 ioapics[idx].mp_config.type = MP_IOAPIC;
3853 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
3854 ioapics[idx].mp_config.apicaddr = address;
3856 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
3858 if (bad_ioapic_register(idx)) {
3859 clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
3863 ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
3864 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
3867 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
3868 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
3870 entries = io_apic_get_redir_entries(idx);
3871 gsi_cfg = mp_ioapic_gsi_routing(idx);
3872 gsi_cfg->gsi_base = gsi_base;
3873 gsi_cfg->gsi_end = gsi_base + entries - 1;
3876 * The number of IO-APIC IRQ registers (== #pins):
3878 ioapics[idx].nr_registers = entries;
3880 if (gsi_cfg->gsi_end >= gsi_top)
3881 gsi_top = gsi_cfg->gsi_end + 1;
3883 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
3884 idx, mpc_ioapic_id(idx),
3885 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
3886 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
3891 /* Enable IOAPIC early just for system timer */
3892 void __init pre_init_apic_IRQ0(void)
3894 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
3896 printk(KERN_INFO "Early APIC setup for system timer0\n");
3898 physid_set_mask_of_physid(boot_cpu_physical_apicid,
3899 &phys_cpu_present_map);
3903 io_apic_setup_irq_pin(0, 0, &attr);
3904 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,