2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
30 #include <asm/iommu.h>
34 * definitions for the ACPI scanning code
36 #define IVRS_HEADER_LENGTH 48
38 #define ACPI_IVHD_TYPE 0x10
39 #define ACPI_IVMD_TYPE_ALL 0x20
40 #define ACPI_IVMD_TYPE 0x21
41 #define ACPI_IVMD_TYPE_RANGE 0x22
43 #define IVHD_DEV_ALL 0x01
44 #define IVHD_DEV_SELECT 0x02
45 #define IVHD_DEV_SELECT_RANGE_START 0x03
46 #define IVHD_DEV_RANGE_END 0x04
47 #define IVHD_DEV_ALIAS 0x42
48 #define IVHD_DEV_ALIAS_RANGE 0x43
49 #define IVHD_DEV_EXT_SELECT 0x46
50 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
52 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
53 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
54 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
55 #define IVHD_FLAG_ISOC_EN_MASK 0x08
57 #define IVMD_FLAG_EXCL_RANGE 0x08
58 #define IVMD_FLAG_UNITY_MAP 0x01
60 #define ACPI_DEVFLAG_INITPASS 0x01
61 #define ACPI_DEVFLAG_EXTINT 0x02
62 #define ACPI_DEVFLAG_NMI 0x04
63 #define ACPI_DEVFLAG_SYSMGT1 0x10
64 #define ACPI_DEVFLAG_SYSMGT2 0x20
65 #define ACPI_DEVFLAG_LINT0 0x40
66 #define ACPI_DEVFLAG_LINT1 0x80
67 #define ACPI_DEVFLAG_ATSDIS 0x10000000
70 * ACPI table definitions
72 * These data structures are laid over the table to parse the important values
77 * structure describing one IOMMU in the ACPI table. Typically followed by one
78 * or more ivhd_entrys.
90 } __attribute__((packed));
93 * A device entry describing which devices a specific IOMMU translates and
94 * which requestor ids they use.
101 } __attribute__((packed));
104 * An AMD IOMMU memory definition structure. It defines things like exclusion
105 * ranges for devices and regions that should be unity mapped.
116 } __attribute__((packed));
120 static int __initdata amd_iommu_detected;
122 u16 amd_iommu_last_bdf; /* largest PCI device id we have
124 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
126 #ifdef CONFIG_IOMMU_STRESS
127 bool amd_iommu_isolate = false;
129 bool amd_iommu_isolate = true; /* if true, device isolation is
133 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
135 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
139 * Pointer to the device table which is shared by all AMD IOMMUs
140 * it is indexed by the PCI device id or the HT unit id and contains
141 * information about the domain the device belongs to as well as the
142 * page table root pointer.
144 struct dev_table_entry *amd_iommu_dev_table;
147 * The alias table is a driver specific data structure which contains the
148 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
149 * More than one device can share the same requestor id.
151 u16 *amd_iommu_alias_table;
154 * The rlookup table is used to find the IOMMU which is responsible
155 * for a specific device. It is also indexed by the PCI device id.
157 struct amd_iommu **amd_iommu_rlookup_table;
160 * The pd table (protection domain table) is used to find the protection domain
161 * data structure a device belongs to. Indexed with the PCI device id too.
163 struct protection_domain **amd_iommu_pd_table;
166 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
167 * to know which ones are already in use.
169 unsigned long *amd_iommu_pd_alloc_bitmap;
171 static u32 dev_table_size; /* size of the device table */
172 static u32 alias_table_size; /* size of the alias table */
173 static u32 rlookup_table_size; /* size if the rlookup table */
175 static inline void update_last_devid(u16 devid)
177 if (devid > amd_iommu_last_bdf)
178 amd_iommu_last_bdf = devid;
181 static inline unsigned long tbl_size(int entry_size)
183 unsigned shift = PAGE_SHIFT +
184 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
189 /****************************************************************************
191 * AMD IOMMU MMIO register space handling functions
193 * These functions are used to program the IOMMU device registers in
194 * MMIO space required for that driver.
196 ****************************************************************************/
199 * This function set the exclusion range in the IOMMU. DMA accesses to the
200 * exclusion range are passed through untranslated
202 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
204 u64 start = iommu->exclusion_start & PAGE_MASK;
205 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
208 if (!iommu->exclusion_start)
211 entry = start | MMIO_EXCL_ENABLE_MASK;
212 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
213 &entry, sizeof(entry));
216 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
217 &entry, sizeof(entry));
220 /* Programs the physical address of the device table into the IOMMU hardware */
221 static void __init iommu_set_device_table(struct amd_iommu *iommu)
225 BUG_ON(iommu->mmio_base == NULL);
227 entry = virt_to_phys(amd_iommu_dev_table);
228 entry |= (dev_table_size >> 12) - 1;
229 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
230 &entry, sizeof(entry));
233 /* Generic functions to enable/disable certain features of the IOMMU. */
234 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
238 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
240 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
243 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
247 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
249 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
252 /* Function to enable the hardware */
253 static void iommu_enable(struct amd_iommu *iommu)
255 printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at %s cap 0x%hx\n",
256 dev_name(&iommu->dev->dev), iommu->cap_ptr);
258 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
261 static void iommu_disable(struct amd_iommu *iommu)
263 /* Disable command buffer */
264 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
266 /* Disable event logging and event interrupts */
267 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
268 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
270 /* Disable IOMMU hardware itself */
271 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
275 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
276 * the system has one.
278 static u8 * __init iommu_map_mmio_space(u64 address)
282 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
285 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
289 release_mem_region(address, MMIO_REGION_LENGTH);
294 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
296 if (iommu->mmio_base)
297 iounmap(iommu->mmio_base);
298 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
301 /****************************************************************************
303 * The functions below belong to the first pass of AMD IOMMU ACPI table
304 * parsing. In this pass we try to find out the highest device id this
305 * code has to handle. Upon this information the size of the shared data
306 * structures is determined later.
308 ****************************************************************************/
311 * This function calculates the length of a given IVHD entry
313 static inline int ivhd_entry_length(u8 *ivhd)
315 return 0x04 << (*ivhd >> 6);
319 * This function reads the last device id the IOMMU has to handle from the PCI
320 * capability header for this IOMMU
322 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
326 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
327 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
333 * After reading the highest device id from the IOMMU PCI capability header
334 * this function looks if there is a higher device id defined in the ACPI table
336 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
338 u8 *p = (void *)h, *end = (void *)h;
339 struct ivhd_entry *dev;
344 find_last_devid_on_pci(PCI_BUS(h->devid),
350 dev = (struct ivhd_entry *)p;
352 case IVHD_DEV_SELECT:
353 case IVHD_DEV_RANGE_END:
355 case IVHD_DEV_EXT_SELECT:
356 /* all the above subfield types refer to device ids */
357 update_last_devid(dev->devid);
362 p += ivhd_entry_length(p);
371 * Iterate over all IVHD entries in the ACPI table and find the highest device
372 * id which we need to handle. This is the first of three functions which parse
373 * the ACPI table. So we check the checksum here.
375 static int __init find_last_devid_acpi(struct acpi_table_header *table)
378 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
379 struct ivhd_header *h;
382 * Validate checksum here so we don't need to do it when
383 * we actually parse the table
385 for (i = 0; i < table->length; ++i)
388 /* ACPI table corrupt */
391 p += IVRS_HEADER_LENGTH;
393 end += table->length;
395 h = (struct ivhd_header *)p;
398 find_last_devid_from_ivhd(h);
410 /****************************************************************************
412 * The following functions belong the the code path which parses the ACPI table
413 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
414 * data structures, initialize the device/alias/rlookup table and also
415 * basically initialize the hardware.
417 ****************************************************************************/
420 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
421 * write commands to that buffer later and the IOMMU will execute them
424 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
426 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
427 get_order(CMD_BUFFER_SIZE));
432 iommu->cmd_buf_size = CMD_BUFFER_SIZE;
438 * This function writes the command buffer address to the hardware and
441 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
445 BUG_ON(iommu->cmd_buf == NULL);
447 entry = (u64)virt_to_phys(iommu->cmd_buf);
448 entry |= MMIO_CMD_SIZE_512;
450 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
451 &entry, sizeof(entry));
453 /* set head and tail to zero manually */
454 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
455 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
457 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
460 static void __init free_command_buffer(struct amd_iommu *iommu)
462 free_pages((unsigned long)iommu->cmd_buf,
463 get_order(iommu->cmd_buf_size));
466 /* allocates the memory where the IOMMU will log its events to */
467 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
469 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
470 get_order(EVT_BUFFER_SIZE));
472 if (iommu->evt_buf == NULL)
475 iommu->evt_buf_size = EVT_BUFFER_SIZE;
477 return iommu->evt_buf;
480 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
484 BUG_ON(iommu->evt_buf == NULL);
486 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
488 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
489 &entry, sizeof(entry));
491 /* set head and tail to zero manually */
492 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
493 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
495 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
498 static void __init free_event_buffer(struct amd_iommu *iommu)
500 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
503 /* sets a specific bit in the device table entry. */
504 static void set_dev_entry_bit(u16 devid, u8 bit)
506 int i = (bit >> 5) & 0x07;
507 int _bit = bit & 0x1f;
509 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
512 static int get_dev_entry_bit(u16 devid, u8 bit)
514 int i = (bit >> 5) & 0x07;
515 int _bit = bit & 0x1f;
517 return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit;
521 void amd_iommu_apply_erratum_63(u16 devid)
525 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
526 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
529 set_dev_entry_bit(devid, DEV_ENTRY_IW);
532 /* Writes the specific IOMMU for a device into the rlookup table */
533 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
535 amd_iommu_rlookup_table[devid] = iommu;
539 * This function takes the device specific flags read from the ACPI
540 * table and sets up the device table entry with that information
542 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
543 u16 devid, u32 flags, u32 ext_flags)
545 if (flags & ACPI_DEVFLAG_INITPASS)
546 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
547 if (flags & ACPI_DEVFLAG_EXTINT)
548 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
549 if (flags & ACPI_DEVFLAG_NMI)
550 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
551 if (flags & ACPI_DEVFLAG_SYSMGT1)
552 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
553 if (flags & ACPI_DEVFLAG_SYSMGT2)
554 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
555 if (flags & ACPI_DEVFLAG_LINT0)
556 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
557 if (flags & ACPI_DEVFLAG_LINT1)
558 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
560 amd_iommu_apply_erratum_63(devid);
562 set_iommu_for_device(iommu, devid);
566 * Reads the device exclusion range from ACPI and initialize IOMMU with
569 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
571 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
573 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
578 * We only can configure exclusion ranges per IOMMU, not
579 * per device. But we can enable the exclusion range per
580 * device. This is done here
582 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
583 iommu->exclusion_start = m->range_start;
584 iommu->exclusion_length = m->range_length;
589 * This function reads some important data from the IOMMU PCI space and
590 * initializes the driver data structure with it. It reads the hardware
591 * capabilities and the first/last device entries
593 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
595 int cap_ptr = iommu->cap_ptr;
598 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
600 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
602 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
605 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
607 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
609 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
613 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
614 * initializes the hardware and our data structures with it.
616 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
617 struct ivhd_header *h)
620 u8 *end = p, flags = 0;
621 u16 dev_i, devid = 0, devid_start = 0, devid_to = 0;
624 struct ivhd_entry *e;
627 * First set the recommended feature enable bits from ACPI
628 * into the IOMMU control registers
630 h->flags & IVHD_FLAG_HT_TUN_EN_MASK ?
631 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
632 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
634 h->flags & IVHD_FLAG_PASSPW_EN_MASK ?
635 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
636 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
638 h->flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
639 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
640 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
642 h->flags & IVHD_FLAG_ISOC_EN_MASK ?
643 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
644 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
647 * make IOMMU memory accesses cache coherent
649 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
652 * Done. Now parse the device entries
654 p += sizeof(struct ivhd_header);
659 e = (struct ivhd_entry *)p;
663 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
664 " last device %02x:%02x.%x flags: %02x\n",
665 PCI_BUS(iommu->first_device),
666 PCI_SLOT(iommu->first_device),
667 PCI_FUNC(iommu->first_device),
668 PCI_BUS(iommu->last_device),
669 PCI_SLOT(iommu->last_device),
670 PCI_FUNC(iommu->last_device),
673 for (dev_i = iommu->first_device;
674 dev_i <= iommu->last_device; ++dev_i)
675 set_dev_entry_from_acpi(iommu, dev_i,
678 case IVHD_DEV_SELECT:
680 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
688 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
690 case IVHD_DEV_SELECT_RANGE_START:
692 DUMP_printk(" DEV_SELECT_RANGE_START\t "
693 "devid: %02x:%02x.%x flags: %02x\n",
699 devid_start = e->devid;
706 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
707 "flags: %02x devid_to: %02x:%02x.%x\n",
712 PCI_BUS(e->ext >> 8),
713 PCI_SLOT(e->ext >> 8),
714 PCI_FUNC(e->ext >> 8));
717 devid_to = e->ext >> 8;
718 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
719 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
720 amd_iommu_alias_table[devid] = devid_to;
722 case IVHD_DEV_ALIAS_RANGE:
724 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
725 "devid: %02x:%02x.%x flags: %02x "
726 "devid_to: %02x:%02x.%x\n",
731 PCI_BUS(e->ext >> 8),
732 PCI_SLOT(e->ext >> 8),
733 PCI_FUNC(e->ext >> 8));
735 devid_start = e->devid;
737 devid_to = e->ext >> 8;
741 case IVHD_DEV_EXT_SELECT:
743 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
744 "flags: %02x ext: %08x\n",
751 set_dev_entry_from_acpi(iommu, devid, e->flags,
754 case IVHD_DEV_EXT_SELECT_RANGE:
756 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
757 "%02x:%02x.%x flags: %02x ext: %08x\n",
763 devid_start = e->devid;
768 case IVHD_DEV_RANGE_END:
770 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
776 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
778 amd_iommu_alias_table[dev_i] = devid_to;
779 set_dev_entry_from_acpi(iommu,
780 devid_to, flags, ext_flags);
782 set_dev_entry_from_acpi(iommu, dev_i,
790 p += ivhd_entry_length(p);
794 /* Initializes the device->iommu mapping for the driver */
795 static int __init init_iommu_devices(struct amd_iommu *iommu)
799 for (i = iommu->first_device; i <= iommu->last_device; ++i)
800 set_iommu_for_device(iommu, i);
805 static void __init free_iommu_one(struct amd_iommu *iommu)
807 free_command_buffer(iommu);
808 free_event_buffer(iommu);
809 iommu_unmap_mmio_space(iommu);
812 static void __init free_iommu_all(void)
814 struct amd_iommu *iommu, *next;
816 for_each_iommu_safe(iommu, next) {
817 list_del(&iommu->list);
818 free_iommu_one(iommu);
824 * This function clues the initialization function for one IOMMU
825 * together and also allocates the command buffer and programs the
826 * hardware. It does NOT enable the IOMMU. This is done afterwards.
828 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
830 spin_lock_init(&iommu->lock);
831 list_add_tail(&iommu->list, &amd_iommu_list);
834 * Copy data from ACPI table entry to the iommu struct
836 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
840 iommu->cap_ptr = h->cap_ptr;
841 iommu->pci_seg = h->pci_seg;
842 iommu->mmio_phys = h->mmio_phys;
843 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
844 if (!iommu->mmio_base)
847 iommu->cmd_buf = alloc_command_buffer(iommu);
851 iommu->evt_buf = alloc_event_buffer(iommu);
855 iommu->int_enabled = false;
857 init_iommu_from_pci(iommu);
858 init_iommu_from_acpi(iommu, h);
859 init_iommu_devices(iommu);
861 return pci_enable_device(iommu->dev);
865 * Iterates over all IOMMU entries in the ACPI table, allocates the
866 * IOMMU structure and initializes it with init_iommu_one()
868 static int __init init_iommu_all(struct acpi_table_header *table)
870 u8 *p = (u8 *)table, *end = (u8 *)table;
871 struct ivhd_header *h;
872 struct amd_iommu *iommu;
875 end += table->length;
876 p += IVRS_HEADER_LENGTH;
879 h = (struct ivhd_header *)p;
883 DUMP_printk("IOMMU: device: %02x:%02x.%01x cap: %04x "
884 "seg: %d flags: %01x info %04x\n",
885 PCI_BUS(h->devid), PCI_SLOT(h->devid),
886 PCI_FUNC(h->devid), h->cap_ptr,
887 h->pci_seg, h->flags, h->info);
888 DUMP_printk(" mmio-addr: %016llx\n",
891 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
894 ret = init_iommu_one(iommu, h);
909 /****************************************************************************
911 * The following functions initialize the MSI interrupts for all IOMMUs
912 * in the system. Its a bit challenging because there could be multiple
913 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
916 ****************************************************************************/
918 static int __init iommu_setup_msi(struct amd_iommu *iommu)
922 if (pci_enable_msi(iommu->dev))
925 r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
931 pci_disable_msi(iommu->dev);
935 iommu->int_enabled = true;
936 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
941 static int iommu_init_msi(struct amd_iommu *iommu)
943 if (iommu->int_enabled)
946 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
947 return iommu_setup_msi(iommu);
952 /****************************************************************************
954 * The next functions belong to the third pass of parsing the ACPI
955 * table. In this last pass the memory mapping requirements are
956 * gathered (like exclusion and unity mapping reanges).
958 ****************************************************************************/
960 static void __init free_unity_maps(void)
962 struct unity_map_entry *entry, *next;
964 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
965 list_del(&entry->list);
970 /* called when we find an exclusion range definition in ACPI */
971 static int __init init_exclusion_range(struct ivmd_header *m)
977 set_device_exclusion_range(m->devid, m);
979 case ACPI_IVMD_TYPE_ALL:
980 for (i = 0; i <= amd_iommu_last_bdf; ++i)
981 set_device_exclusion_range(i, m);
983 case ACPI_IVMD_TYPE_RANGE:
984 for (i = m->devid; i <= m->aux; ++i)
985 set_device_exclusion_range(i, m);
994 /* called for unity map ACPI definition */
995 static int __init init_unity_map_range(struct ivmd_header *m)
997 struct unity_map_entry *e = 0;
1000 e = kzalloc(sizeof(*e), GFP_KERNEL);
1008 case ACPI_IVMD_TYPE:
1009 s = "IVMD_TYPEi\t\t\t";
1010 e->devid_start = e->devid_end = m->devid;
1012 case ACPI_IVMD_TYPE_ALL:
1013 s = "IVMD_TYPE_ALL\t\t";
1015 e->devid_end = amd_iommu_last_bdf;
1017 case ACPI_IVMD_TYPE_RANGE:
1018 s = "IVMD_TYPE_RANGE\t\t";
1019 e->devid_start = m->devid;
1020 e->devid_end = m->aux;
1023 e->address_start = PAGE_ALIGN(m->range_start);
1024 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1025 e->prot = m->flags >> 1;
1027 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1028 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1029 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1030 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1031 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1032 e->address_start, e->address_end, m->flags);
1034 list_add_tail(&e->list, &amd_iommu_unity_map);
1039 /* iterates over all memory definitions we find in the ACPI table */
1040 static int __init init_memory_definitions(struct acpi_table_header *table)
1042 u8 *p = (u8 *)table, *end = (u8 *)table;
1043 struct ivmd_header *m;
1045 end += table->length;
1046 p += IVRS_HEADER_LENGTH;
1049 m = (struct ivmd_header *)p;
1050 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1051 init_exclusion_range(m);
1052 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1053 init_unity_map_range(m);
1062 * Init the device table to not allow DMA access for devices and
1063 * suppress all page faults
1065 static void init_device_table(void)
1069 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1070 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1071 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1076 * This function finally enables all IOMMUs found in the system after
1077 * they have been initialized
1079 static void enable_iommus(void)
1081 struct amd_iommu *iommu;
1083 for_each_iommu(iommu) {
1084 iommu_disable(iommu);
1085 iommu_set_device_table(iommu);
1086 iommu_enable_command_buffer(iommu);
1087 iommu_enable_event_buffer(iommu);
1088 iommu_set_exclusion_range(iommu);
1089 iommu_init_msi(iommu);
1090 iommu_enable(iommu);
1094 static void disable_iommus(void)
1096 struct amd_iommu *iommu;
1098 for_each_iommu(iommu)
1099 iommu_disable(iommu);
1103 * Suspend/Resume support
1104 * disable suspend until real resume implemented
1107 static int amd_iommu_resume(struct sys_device *dev)
1109 /* re-load the hardware */
1113 * we have to flush after the IOMMUs are enabled because a
1114 * disabled IOMMU will never execute the commands we send
1116 amd_iommu_flush_all_devices();
1117 amd_iommu_flush_all_domains();
1122 static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
1124 /* disable IOMMUs to go out of the way for BIOS */
1130 static struct sysdev_class amd_iommu_sysdev_class = {
1131 .name = "amd_iommu",
1132 .suspend = amd_iommu_suspend,
1133 .resume = amd_iommu_resume,
1136 static struct sys_device device_amd_iommu = {
1138 .cls = &amd_iommu_sysdev_class,
1142 * This is the core init function for AMD IOMMU hardware in the system.
1143 * This function is called from the generic x86 DMA layer initialization
1146 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1149 * 1 pass) Find the highest PCI device id the driver has to handle.
1150 * Upon this information the size of the data structures is
1151 * determined that needs to be allocated.
1153 * 2 pass) Initialize the data structures just allocated with the
1154 * information in the ACPI table about available AMD IOMMUs
1155 * in the system. It also maps the PCI devices in the
1156 * system to specific IOMMUs
1158 * 3 pass) After the basic data structures are allocated and
1159 * initialized we update them with information about memory
1160 * remapping requirements parsed out of the ACPI table in
1163 * After that the hardware is initialized and ready to go. In the last
1164 * step we do some Linux specific things like registering the driver in
1165 * the dma_ops interface and initializing the suspend/resume support
1166 * functions. Finally it prints some information about AMD IOMMUs and
1167 * the driver state and enables the hardware.
1169 int __init amd_iommu_init(void)
1175 printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n");
1179 if (!amd_iommu_detected)
1183 * First parse ACPI tables to find the largest Bus/Dev/Func
1184 * we need to handle. Upon this information the shared data
1185 * structures for the IOMMUs in the system will be allocated
1187 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1190 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1191 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1192 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1196 /* Device table - directly used by all IOMMUs */
1197 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1198 get_order(dev_table_size));
1199 if (amd_iommu_dev_table == NULL)
1203 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1204 * IOMMU see for that device
1206 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1207 get_order(alias_table_size));
1208 if (amd_iommu_alias_table == NULL)
1211 /* IOMMU rlookup table - find the IOMMU for a specific device */
1212 amd_iommu_rlookup_table = (void *)__get_free_pages(
1213 GFP_KERNEL | __GFP_ZERO,
1214 get_order(rlookup_table_size));
1215 if (amd_iommu_rlookup_table == NULL)
1219 * Protection Domain table - maps devices to protection domains
1220 * This table has the same size as the rlookup_table
1222 amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1223 get_order(rlookup_table_size));
1224 if (amd_iommu_pd_table == NULL)
1227 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1228 GFP_KERNEL | __GFP_ZERO,
1229 get_order(MAX_DOMAIN_ID/8));
1230 if (amd_iommu_pd_alloc_bitmap == NULL)
1233 /* init the device table */
1234 init_device_table();
1237 * let all alias entries point to itself
1239 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1240 amd_iommu_alias_table[i] = i;
1243 * never allocate domain 0 because its used as the non-allocated and
1244 * error value placeholder
1246 amd_iommu_pd_alloc_bitmap[0] = 1;
1249 * now the data structures are allocated and basically initialized
1250 * start the real acpi table scan
1253 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1256 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1259 ret = sysdev_class_register(&amd_iommu_sysdev_class);
1263 ret = sysdev_register(&device_amd_iommu);
1267 ret = amd_iommu_init_dma_ops();
1273 printk(KERN_INFO "AMD IOMMU: device isolation ");
1274 if (amd_iommu_isolate)
1275 printk("enabled\n");
1277 printk("disabled\n");
1279 if (amd_iommu_unmap_flush)
1280 printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n");
1282 printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n");
1288 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1289 get_order(MAX_DOMAIN_ID/8));
1291 free_pages((unsigned long)amd_iommu_pd_table,
1292 get_order(rlookup_table_size));
1294 free_pages((unsigned long)amd_iommu_rlookup_table,
1295 get_order(rlookup_table_size));
1297 free_pages((unsigned long)amd_iommu_alias_table,
1298 get_order(alias_table_size));
1300 free_pages((unsigned long)amd_iommu_dev_table,
1301 get_order(dev_table_size));
1310 void amd_iommu_shutdown(void)
1315 /****************************************************************************
1317 * Early detect code. This code runs at IOMMU detection time in the DMA
1318 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1321 ****************************************************************************/
1322 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1327 void __init amd_iommu_detect(void)
1329 if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture))
1332 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1334 amd_iommu_detected = 1;
1335 #ifdef CONFIG_GART_IOMMU
1336 gart_iommu_aperture_disabled = 1;
1337 gart_iommu_aperture = 0;
1342 /****************************************************************************
1344 * Parsing functions for the AMD IOMMU specific kernel command line
1347 ****************************************************************************/
1349 static int __init parse_amd_iommu_dump(char *str)
1351 amd_iommu_dump = true;
1356 static int __init parse_amd_iommu_options(char *str)
1358 for (; *str; ++str) {
1359 if (strncmp(str, "isolate", 7) == 0)
1360 amd_iommu_isolate = true;
1361 if (strncmp(str, "share", 5) == 0)
1362 amd_iommu_isolate = false;
1363 if (strncmp(str, "fullflush", 9) == 0)
1364 amd_iommu_unmap_flush = true;
1370 __setup("amd_iommu_dump", parse_amd_iommu_dump);
1371 __setup("amd_iommu=", parse_amd_iommu_options);