2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_types.h>
32 #include <asm/amd_iommu.h>
34 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
36 #define EXIT_LOOP_COUNT 10000000
38 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
40 /* A list of preallocated protection domains */
41 static LIST_HEAD(iommu_pd_list);
42 static DEFINE_SPINLOCK(iommu_pd_list_lock);
45 * Domain for untranslated devices - only allocated
46 * if iommu=pt passed on kernel cmd line.
48 static struct protection_domain *pt_domain;
50 #ifdef CONFIG_IOMMU_API
51 static struct iommu_ops amd_iommu_ops;
55 * general struct to manage commands send to an IOMMU
61 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
62 struct unity_map_entry *e);
63 static struct dma_ops_domain *find_protection_domain(u16 devid);
64 static u64* alloc_pte(struct protection_domain *dom,
65 unsigned long address, u64
66 **pte_page, gfp_t gfp);
67 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
68 unsigned long start_page,
71 #ifndef BUS_NOTIFY_UNBOUND_DRIVER
72 #define BUS_NOTIFY_UNBOUND_DRIVER 0x0005
75 #ifdef CONFIG_AMD_IOMMU_STATS
78 * Initialization code for statistics collection
81 DECLARE_STATS_COUNTER(compl_wait);
82 DECLARE_STATS_COUNTER(cnt_map_single);
83 DECLARE_STATS_COUNTER(cnt_unmap_single);
84 DECLARE_STATS_COUNTER(cnt_map_sg);
85 DECLARE_STATS_COUNTER(cnt_unmap_sg);
86 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
87 DECLARE_STATS_COUNTER(cnt_free_coherent);
88 DECLARE_STATS_COUNTER(cross_page);
89 DECLARE_STATS_COUNTER(domain_flush_single);
90 DECLARE_STATS_COUNTER(domain_flush_all);
91 DECLARE_STATS_COUNTER(alloced_io_mem);
92 DECLARE_STATS_COUNTER(total_map_requests);
94 static struct dentry *stats_dir;
95 static struct dentry *de_isolate;
96 static struct dentry *de_fflush;
98 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
100 if (stats_dir == NULL)
103 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
107 static void amd_iommu_stats_init(void)
109 stats_dir = debugfs_create_dir("amd-iommu", NULL);
110 if (stats_dir == NULL)
113 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
114 (u32 *)&amd_iommu_isolate);
116 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
117 (u32 *)&amd_iommu_unmap_flush);
119 amd_iommu_stats_add(&compl_wait);
120 amd_iommu_stats_add(&cnt_map_single);
121 amd_iommu_stats_add(&cnt_unmap_single);
122 amd_iommu_stats_add(&cnt_map_sg);
123 amd_iommu_stats_add(&cnt_unmap_sg);
124 amd_iommu_stats_add(&cnt_alloc_coherent);
125 amd_iommu_stats_add(&cnt_free_coherent);
126 amd_iommu_stats_add(&cross_page);
127 amd_iommu_stats_add(&domain_flush_single);
128 amd_iommu_stats_add(&domain_flush_all);
129 amd_iommu_stats_add(&alloced_io_mem);
130 amd_iommu_stats_add(&total_map_requests);
135 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
136 static int iommu_has_npcache(struct amd_iommu *iommu)
138 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
141 /****************************************************************************
143 * Interrupt handling functions
145 ****************************************************************************/
147 static void iommu_print_event(void *__evt)
150 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
151 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
152 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
153 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
154 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
156 printk(KERN_ERR "AMD IOMMU: Event logged [");
159 case EVENT_TYPE_ILL_DEV:
160 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
161 "address=0x%016llx flags=0x%04x]\n",
162 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
165 case EVENT_TYPE_IO_FAULT:
166 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
167 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
168 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
169 domid, address, flags);
171 case EVENT_TYPE_DEV_TAB_ERR:
172 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
173 "address=0x%016llx flags=0x%04x]\n",
174 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
177 case EVENT_TYPE_PAGE_TAB_ERR:
178 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
179 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
180 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
181 domid, address, flags);
183 case EVENT_TYPE_ILL_CMD:
184 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
186 case EVENT_TYPE_CMD_HARD_ERR:
187 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
188 "flags=0x%04x]\n", address, flags);
190 case EVENT_TYPE_IOTLB_INV_TO:
191 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
192 "address=0x%016llx]\n",
193 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
196 case EVENT_TYPE_INV_DEV_REQ:
197 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
198 "address=0x%016llx flags=0x%04x]\n",
199 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
203 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
207 static void iommu_poll_events(struct amd_iommu *iommu)
212 spin_lock_irqsave(&iommu->lock, flags);
214 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
215 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
217 while (head != tail) {
218 iommu_print_event(iommu->evt_buf + head);
219 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
222 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
224 spin_unlock_irqrestore(&iommu->lock, flags);
227 irqreturn_t amd_iommu_int_handler(int irq, void *data)
229 struct amd_iommu *iommu;
231 for_each_iommu(iommu)
232 iommu_poll_events(iommu);
237 /****************************************************************************
239 * IOMMU command queuing functions
241 ****************************************************************************/
244 * Writes the command to the IOMMUs command buffer and informs the
245 * hardware about the new command. Must be called with iommu->lock held.
247 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
252 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
253 target = iommu->cmd_buf + tail;
254 memcpy_toio(target, cmd, sizeof(*cmd));
255 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
256 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
259 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
265 * General queuing function for commands. Takes iommu->lock and calls
266 * __iommu_queue_command().
268 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
273 spin_lock_irqsave(&iommu->lock, flags);
274 ret = __iommu_queue_command(iommu, cmd);
276 iommu->need_sync = true;
277 spin_unlock_irqrestore(&iommu->lock, flags);
283 * This function waits until an IOMMU has completed a completion
286 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
292 INC_STATS_COUNTER(compl_wait);
294 while (!ready && (i < EXIT_LOOP_COUNT)) {
296 /* wait for the bit to become one */
297 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
298 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
301 /* set bit back to zero */
302 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
303 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
305 if (unlikely(i == EXIT_LOOP_COUNT))
306 panic("AMD IOMMU: Completion wait loop failed\n");
310 * This function queues a completion wait command into the command
313 static int __iommu_completion_wait(struct amd_iommu *iommu)
315 struct iommu_cmd cmd;
317 memset(&cmd, 0, sizeof(cmd));
318 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
319 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
321 return __iommu_queue_command(iommu, &cmd);
325 * This function is called whenever we need to ensure that the IOMMU has
326 * completed execution of all commands we sent. It sends a
327 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
328 * us about that by writing a value to a physical address we pass with
331 static int iommu_completion_wait(struct amd_iommu *iommu)
336 spin_lock_irqsave(&iommu->lock, flags);
338 if (!iommu->need_sync)
341 ret = __iommu_completion_wait(iommu);
343 iommu->need_sync = false;
348 __iommu_wait_for_completion(iommu);
351 spin_unlock_irqrestore(&iommu->lock, flags);
357 * Command send function for invalidating a device table entry
359 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
361 struct iommu_cmd cmd;
364 BUG_ON(iommu == NULL);
366 memset(&cmd, 0, sizeof(cmd));
367 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
370 ret = iommu_queue_command(iommu, &cmd);
375 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
376 u16 domid, int pde, int s)
378 memset(cmd, 0, sizeof(*cmd));
379 address &= PAGE_MASK;
380 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
381 cmd->data[1] |= domid;
382 cmd->data[2] = lower_32_bits(address);
383 cmd->data[3] = upper_32_bits(address);
384 if (s) /* size bit - we flush more than one 4kb page */
385 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
386 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
387 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
391 * Generic command send function for invalidaing TLB entries
393 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
394 u64 address, u16 domid, int pde, int s)
396 struct iommu_cmd cmd;
399 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
401 ret = iommu_queue_command(iommu, &cmd);
407 * TLB invalidation function which is called from the mapping functions.
408 * It invalidates a single PTE if the range to flush is within a single
409 * page. Otherwise it flushes the whole TLB of the IOMMU.
411 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
412 u64 address, size_t size)
415 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
417 address &= PAGE_MASK;
421 * If we have to flush more than one page, flush all
422 * TLB entries for this domain
424 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
428 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
433 /* Flush the whole IO/TLB for a given protection domain */
434 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
436 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
438 INC_STATS_COUNTER(domain_flush_single);
440 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
443 /* Flush the whole IO/TLB for a given protection domain - including PDE */
444 static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid)
446 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
448 INC_STATS_COUNTER(domain_flush_single);
450 iommu_queue_inv_iommu_pages(iommu, address, domid, 1, 1);
454 * This function is used to flush the IO/TLB for a given protection domain
455 * on every IOMMU in the system
457 static void iommu_flush_domain(u16 domid)
460 struct amd_iommu *iommu;
461 struct iommu_cmd cmd;
463 INC_STATS_COUNTER(domain_flush_all);
465 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
468 for_each_iommu(iommu) {
469 spin_lock_irqsave(&iommu->lock, flags);
470 __iommu_queue_command(iommu, &cmd);
471 __iommu_completion_wait(iommu);
472 __iommu_wait_for_completion(iommu);
473 spin_unlock_irqrestore(&iommu->lock, flags);
477 void amd_iommu_flush_all_domains(void)
481 for (i = 1; i < MAX_DOMAIN_ID; ++i) {
482 if (!test_bit(i, amd_iommu_pd_alloc_bitmap))
484 iommu_flush_domain(i);
488 void amd_iommu_flush_all_devices(void)
490 struct amd_iommu *iommu;
493 for (i = 0; i <= amd_iommu_last_bdf; ++i) {
494 if (amd_iommu_pd_table[i] == NULL)
497 iommu = amd_iommu_rlookup_table[i];
501 iommu_queue_inv_dev_entry(iommu, i);
502 iommu_completion_wait(iommu);
506 /****************************************************************************
508 * The functions below are used the create the page table mappings for
509 * unity mapped regions.
511 ****************************************************************************/
514 * Generic mapping functions. It maps a physical address into a DMA
515 * address space. It allocates the page table pages if necessary.
516 * In the future it can be extended to a generic mapping function
517 * supporting all features of AMD IOMMU page tables like level skipping
518 * and full 64 bit address spaces.
520 static int iommu_map_page(struct protection_domain *dom,
521 unsigned long bus_addr,
522 unsigned long phys_addr,
527 bus_addr = PAGE_ALIGN(bus_addr);
528 phys_addr = PAGE_ALIGN(phys_addr);
530 /* only support 512GB address spaces for now */
531 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
534 pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL);
536 if (IOMMU_PTE_PRESENT(*pte))
539 __pte = phys_addr | IOMMU_PTE_P;
540 if (prot & IOMMU_PROT_IR)
541 __pte |= IOMMU_PTE_IR;
542 if (prot & IOMMU_PROT_IW)
543 __pte |= IOMMU_PTE_IW;
550 static void iommu_unmap_page(struct protection_domain *dom,
551 unsigned long bus_addr)
555 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
557 if (!IOMMU_PTE_PRESENT(*pte))
560 pte = IOMMU_PTE_PAGE(*pte);
561 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
563 if (!IOMMU_PTE_PRESENT(*pte))
566 pte = IOMMU_PTE_PAGE(*pte);
567 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
573 * This function checks if a specific unity mapping entry is needed for
574 * this specific IOMMU.
576 static int iommu_for_unity_map(struct amd_iommu *iommu,
577 struct unity_map_entry *entry)
581 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
582 bdf = amd_iommu_alias_table[i];
583 if (amd_iommu_rlookup_table[bdf] == iommu)
591 * Init the unity mappings for a specific IOMMU in the system
593 * Basically iterates over all unity mapping entries and applies them to
594 * the default domain DMA of that IOMMU if necessary.
596 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
598 struct unity_map_entry *entry;
601 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
602 if (!iommu_for_unity_map(iommu, entry))
604 ret = dma_ops_unity_map(iommu->default_dom, entry);
613 * This function actually applies the mapping to the page table of the
616 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
617 struct unity_map_entry *e)
622 for (addr = e->address_start; addr < e->address_end;
624 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
628 * if unity mapping is in aperture range mark the page
629 * as allocated in the aperture
631 if (addr < dma_dom->aperture_size)
632 __set_bit(addr >> PAGE_SHIFT,
633 dma_dom->aperture[0]->bitmap);
640 * Inits the unity mappings required for a specific device
642 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
645 struct unity_map_entry *e;
648 list_for_each_entry(e, &amd_iommu_unity_map, list) {
649 if (!(devid >= e->devid_start && devid <= e->devid_end))
651 ret = dma_ops_unity_map(dma_dom, e);
659 /****************************************************************************
661 * The next functions belong to the address allocator for the dma_ops
662 * interface functions. They work like the allocators in the other IOMMU
663 * drivers. Its basically a bitmap which marks the allocated pages in
664 * the aperture. Maybe it could be enhanced in the future to a more
665 * efficient allocator.
667 ****************************************************************************/
670 * The address allocator core functions.
672 * called with domain->lock held
676 * This function checks if there is a PTE for a given dma address. If
677 * there is one, it returns the pointer to it.
679 static u64* fetch_pte(struct protection_domain *domain,
680 unsigned long address)
684 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(address)];
686 if (!IOMMU_PTE_PRESENT(*pte))
689 pte = IOMMU_PTE_PAGE(*pte);
690 pte = &pte[IOMMU_PTE_L1_INDEX(address)];
692 if (!IOMMU_PTE_PRESENT(*pte))
695 pte = IOMMU_PTE_PAGE(*pte);
696 pte = &pte[IOMMU_PTE_L0_INDEX(address)];
702 * This function is used to add a new aperture range to an existing
703 * aperture in case of dma_ops domain allocation or address allocation
706 static int alloc_new_range(struct amd_iommu *iommu,
707 struct dma_ops_domain *dma_dom,
708 bool populate, gfp_t gfp)
710 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
713 #ifdef CONFIG_IOMMU_STRESS
717 if (index >= APERTURE_MAX_RANGES)
720 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
721 if (!dma_dom->aperture[index])
724 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
725 if (!dma_dom->aperture[index]->bitmap)
728 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
731 unsigned long address = dma_dom->aperture_size;
732 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
735 for (i = 0; i < num_ptes; ++i) {
736 pte = alloc_pte(&dma_dom->domain, address,
741 dma_dom->aperture[index]->pte_pages[i] = pte_page;
743 address += APERTURE_RANGE_SIZE / 64;
747 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
749 /* Intialize the exclusion range if necessary */
750 if (iommu->exclusion_start &&
751 iommu->exclusion_start >= dma_dom->aperture[index]->offset &&
752 iommu->exclusion_start < dma_dom->aperture_size) {
753 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
754 int pages = iommu_num_pages(iommu->exclusion_start,
755 iommu->exclusion_length,
757 dma_ops_reserve_addresses(dma_dom, startpage, pages);
761 * Check for areas already mapped as present in the new aperture
762 * range and mark those pages as reserved in the allocator. Such
763 * mappings may already exist as a result of requested unity
764 * mappings for devices.
766 for (i = dma_dom->aperture[index]->offset;
767 i < dma_dom->aperture_size;
769 u64 *pte = fetch_pte(&dma_dom->domain, i);
770 if (!pte || !IOMMU_PTE_PRESENT(*pte))
773 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
779 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
781 kfree(dma_dom->aperture[index]);
782 dma_dom->aperture[index] = NULL;
787 static unsigned long dma_ops_area_alloc(struct device *dev,
788 struct dma_ops_domain *dom,
790 unsigned long align_mask,
794 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
795 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
796 int i = start >> APERTURE_RANGE_SHIFT;
797 unsigned long boundary_size;
798 unsigned long address = -1;
801 next_bit >>= PAGE_SHIFT;
803 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
804 PAGE_SIZE) >> PAGE_SHIFT;
806 for (;i < max_index; ++i) {
807 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
809 if (dom->aperture[i]->offset >= dma_mask)
812 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
813 dma_mask >> PAGE_SHIFT);
815 address = iommu_area_alloc(dom->aperture[i]->bitmap,
816 limit, next_bit, pages, 0,
817 boundary_size, align_mask);
819 address = dom->aperture[i]->offset +
820 (address << PAGE_SHIFT);
821 dom->next_address = address + (pages << PAGE_SHIFT);
831 static unsigned long dma_ops_alloc_addresses(struct device *dev,
832 struct dma_ops_domain *dom,
834 unsigned long align_mask,
837 unsigned long address;
839 #ifdef CONFIG_IOMMU_STRESS
840 dom->next_address = 0;
841 dom->need_flush = true;
844 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
845 dma_mask, dom->next_address);
848 dom->next_address = 0;
849 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
851 dom->need_flush = true;
854 if (unlikely(address == -1))
855 address = bad_dma_address;
857 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
863 * The address free function.
865 * called with domain->lock held
867 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
868 unsigned long address,
871 unsigned i = address >> APERTURE_RANGE_SHIFT;
872 struct aperture_range *range = dom->aperture[i];
874 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
876 #ifdef CONFIG_IOMMU_STRESS
881 if (address >= dom->next_address)
882 dom->need_flush = true;
884 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
886 iommu_area_free(range->bitmap, address, pages);
890 /****************************************************************************
892 * The next functions belong to the domain allocation. A domain is
893 * allocated for every IOMMU as the default domain. If device isolation
894 * is enabled, every device get its own domain. The most important thing
895 * about domains is the page table mapping the DMA address space they
898 ****************************************************************************/
900 static u16 domain_id_alloc(void)
905 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
906 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
908 if (id > 0 && id < MAX_DOMAIN_ID)
909 __set_bit(id, amd_iommu_pd_alloc_bitmap);
912 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
917 static void domain_id_free(int id)
921 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
922 if (id > 0 && id < MAX_DOMAIN_ID)
923 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
924 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
928 * Used to reserve address ranges in the aperture (e.g. for exclusion
931 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
932 unsigned long start_page,
935 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
937 if (start_page + pages > last_page)
938 pages = last_page - start_page;
940 for (i = start_page; i < start_page + pages; ++i) {
941 int index = i / APERTURE_RANGE_PAGES;
942 int page = i % APERTURE_RANGE_PAGES;
943 __set_bit(page, dom->aperture[index]->bitmap);
947 static void free_pagetable(struct protection_domain *domain)
952 p1 = domain->pt_root;
957 for (i = 0; i < 512; ++i) {
958 if (!IOMMU_PTE_PRESENT(p1[i]))
961 p2 = IOMMU_PTE_PAGE(p1[i]);
962 for (j = 0; j < 512; ++j) {
963 if (!IOMMU_PTE_PRESENT(p2[j]))
965 p3 = IOMMU_PTE_PAGE(p2[j]);
966 free_page((unsigned long)p3);
969 free_page((unsigned long)p2);
972 free_page((unsigned long)p1);
974 domain->pt_root = NULL;
978 * Free a domain, only used if something went wrong in the
979 * allocation path and we need to free an already allocated page table
981 static void dma_ops_domain_free(struct dma_ops_domain *dom)
988 free_pagetable(&dom->domain);
990 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
991 if (!dom->aperture[i])
993 free_page((unsigned long)dom->aperture[i]->bitmap);
994 kfree(dom->aperture[i]);
1001 * Allocates a new protection domain usable for the dma_ops functions.
1002 * It also intializes the page table and the address allocator data
1003 * structures required for the dma_ops interface
1005 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu)
1007 struct dma_ops_domain *dma_dom;
1009 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1013 spin_lock_init(&dma_dom->domain.lock);
1015 dma_dom->domain.id = domain_id_alloc();
1016 if (dma_dom->domain.id == 0)
1018 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1019 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1020 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1021 dma_dom->domain.priv = dma_dom;
1022 if (!dma_dom->domain.pt_root)
1025 dma_dom->need_flush = false;
1026 dma_dom->target_dev = 0xffff;
1028 if (alloc_new_range(iommu, dma_dom, true, GFP_KERNEL))
1032 * mark the first page as allocated so we never return 0 as
1033 * a valid dma-address. So we can use 0 as error value
1035 dma_dom->aperture[0]->bitmap[0] = 1;
1036 dma_dom->next_address = 0;
1042 dma_ops_domain_free(dma_dom);
1048 * little helper function to check whether a given protection domain is a
1051 static bool dma_ops_domain(struct protection_domain *domain)
1053 return domain->flags & PD_DMA_OPS_MASK;
1057 * Find out the protection domain structure for a given PCI device. This
1058 * will give us the pointer to the page table root for example.
1060 static struct protection_domain *domain_for_device(u16 devid)
1062 struct protection_domain *dom;
1063 unsigned long flags;
1065 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1066 dom = amd_iommu_pd_table[devid];
1067 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1073 * If a device is not yet associated with a domain, this function does
1074 * assigns it visible for the hardware
1076 static void __attach_device(struct amd_iommu *iommu,
1077 struct protection_domain *domain,
1083 spin_lock(&domain->lock);
1085 pte_root = virt_to_phys(domain->pt_root);
1087 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1088 << DEV_ENTRY_MODE_SHIFT;
1089 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1091 amd_iommu_dev_table[devid].data[2] = domain->id;
1092 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1093 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1095 amd_iommu_pd_table[devid] = domain;
1097 domain->dev_cnt += 1;
1100 spin_unlock(&domain->lock);
1103 static void attach_device(struct amd_iommu *iommu,
1104 struct protection_domain *domain,
1107 unsigned long flags;
1109 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1110 __attach_device(iommu, domain, devid);
1111 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1114 * We might boot into a crash-kernel here. The crashed kernel
1115 * left the caches in the IOMMU dirty. So we have to flush
1116 * here to evict all dirty stuff.
1118 iommu_queue_inv_dev_entry(iommu, devid);
1119 iommu_flush_tlb_pde(iommu, domain->id);
1123 * Removes a device from a protection domain (unlocked)
1125 static void __detach_device(struct protection_domain *domain, u16 devid)
1129 spin_lock(&domain->lock);
1131 /* remove domain from the lookup table */
1132 amd_iommu_pd_table[devid] = NULL;
1134 /* remove entry from the device table seen by the hardware */
1135 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1136 amd_iommu_dev_table[devid].data[1] = 0;
1137 amd_iommu_dev_table[devid].data[2] = 0;
1139 /* decrease reference counter */
1140 domain->dev_cnt -= 1;
1143 spin_unlock(&domain->lock);
1146 * If we run in passthrough mode the device must be assigned to the
1147 * passthrough domain if it is detached from any other domain
1149 if (iommu_pass_through) {
1150 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1151 __attach_device(iommu, pt_domain, devid);
1156 * Removes a device from a protection domain (with devtable_lock held)
1158 static void detach_device(struct protection_domain *domain, u16 devid)
1160 unsigned long flags;
1162 /* lock device table */
1163 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1164 __detach_device(domain, devid);
1165 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1168 static int device_change_notifier(struct notifier_block *nb,
1169 unsigned long action, void *data)
1171 struct device *dev = data;
1172 struct pci_dev *pdev = to_pci_dev(dev);
1173 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
1174 struct protection_domain *domain;
1175 struct dma_ops_domain *dma_domain;
1176 struct amd_iommu *iommu;
1177 unsigned long flags;
1179 if (devid > amd_iommu_last_bdf)
1182 devid = amd_iommu_alias_table[devid];
1184 iommu = amd_iommu_rlookup_table[devid];
1188 domain = domain_for_device(devid);
1190 if (domain && !dma_ops_domain(domain))
1191 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
1192 "to a non-dma-ops domain\n", dev_name(dev));
1195 case BUS_NOTIFY_UNBOUND_DRIVER:
1198 if (iommu_pass_through)
1200 detach_device(domain, devid);
1202 case BUS_NOTIFY_ADD_DEVICE:
1203 /* allocate a protection domain if a device is added */
1204 dma_domain = find_protection_domain(devid);
1207 dma_domain = dma_ops_domain_alloc(iommu);
1210 dma_domain->target_dev = devid;
1212 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1213 list_add_tail(&dma_domain->list, &iommu_pd_list);
1214 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1221 iommu_queue_inv_dev_entry(iommu, devid);
1222 iommu_completion_wait(iommu);
1228 static struct notifier_block device_nb = {
1229 .notifier_call = device_change_notifier,
1232 /*****************************************************************************
1234 * The next functions belong to the dma_ops mapping/unmapping code.
1236 *****************************************************************************/
1239 * This function checks if the driver got a valid device from the caller to
1240 * avoid dereferencing invalid pointers.
1242 static bool check_device(struct device *dev)
1244 if (!dev || !dev->dma_mask)
1251 * In this function the list of preallocated protection domains is traversed to
1252 * find the domain for a specific device
1254 static struct dma_ops_domain *find_protection_domain(u16 devid)
1256 struct dma_ops_domain *entry, *ret = NULL;
1257 unsigned long flags;
1259 if (list_empty(&iommu_pd_list))
1262 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1264 list_for_each_entry(entry, &iommu_pd_list, list) {
1265 if (entry->target_dev == devid) {
1271 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1277 * In the dma_ops path we only have the struct device. This function
1278 * finds the corresponding IOMMU, the protection domain and the
1279 * requestor id for a given device.
1280 * If the device is not yet associated with a domain this is also done
1283 static int get_device_resources(struct device *dev,
1284 struct amd_iommu **iommu,
1285 struct protection_domain **domain,
1288 struct dma_ops_domain *dma_dom;
1289 struct pci_dev *pcidev;
1296 if (dev->bus != &pci_bus_type)
1299 pcidev = to_pci_dev(dev);
1300 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1302 /* device not translated by any IOMMU in the system? */
1303 if (_bdf > amd_iommu_last_bdf)
1306 *bdf = amd_iommu_alias_table[_bdf];
1308 *iommu = amd_iommu_rlookup_table[*bdf];
1311 *domain = domain_for_device(*bdf);
1312 if (*domain == NULL) {
1313 dma_dom = find_protection_domain(*bdf);
1315 dma_dom = (*iommu)->default_dom;
1316 *domain = &dma_dom->domain;
1317 attach_device(*iommu, *domain, *bdf);
1318 DUMP_printk("Using protection domain %d for device %s\n",
1319 (*domain)->id, dev_name(dev));
1322 if (domain_for_device(_bdf) == NULL)
1323 attach_device(*iommu, *domain, _bdf);
1329 * If the pte_page is not yet allocated this function is called
1331 static u64* alloc_pte(struct protection_domain *dom,
1332 unsigned long address, u64 **pte_page, gfp_t gfp)
1336 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)];
1338 if (!IOMMU_PTE_PRESENT(*pte)) {
1339 page = (u64 *)get_zeroed_page(gfp);
1342 *pte = IOMMU_L2_PDE(virt_to_phys(page));
1345 pte = IOMMU_PTE_PAGE(*pte);
1346 pte = &pte[IOMMU_PTE_L1_INDEX(address)];
1348 if (!IOMMU_PTE_PRESENT(*pte)) {
1349 page = (u64 *)get_zeroed_page(gfp);
1352 *pte = IOMMU_L1_PDE(virt_to_phys(page));
1355 pte = IOMMU_PTE_PAGE(*pte);
1360 pte = &pte[IOMMU_PTE_L0_INDEX(address)];
1366 * This function fetches the PTE for a given address in the aperture
1368 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1369 unsigned long address)
1371 struct aperture_range *aperture;
1372 u64 *pte, *pte_page;
1374 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1378 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1380 pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC);
1381 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1383 pte += IOMMU_PTE_L0_INDEX(address);
1389 * This is the generic map function. It maps one 4kb page at paddr to
1390 * the given address in the DMA address space for the domain.
1392 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1393 struct dma_ops_domain *dom,
1394 unsigned long address,
1400 WARN_ON(address > dom->aperture_size);
1404 pte = dma_ops_get_pte(dom, address);
1406 return bad_dma_address;
1408 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1410 if (direction == DMA_TO_DEVICE)
1411 __pte |= IOMMU_PTE_IR;
1412 else if (direction == DMA_FROM_DEVICE)
1413 __pte |= IOMMU_PTE_IW;
1414 else if (direction == DMA_BIDIRECTIONAL)
1415 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1421 return (dma_addr_t)address;
1425 * The generic unmapping function for on page in the DMA address space.
1427 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1428 struct dma_ops_domain *dom,
1429 unsigned long address)
1431 struct aperture_range *aperture;
1434 if (address >= dom->aperture_size)
1437 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1441 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1445 pte += IOMMU_PTE_L0_INDEX(address);
1453 * This function contains common code for mapping of a physically
1454 * contiguous memory region into DMA address space. It is used by all
1455 * mapping functions provided with this IOMMU driver.
1456 * Must be called with the domain lock held.
1458 static dma_addr_t __map_single(struct device *dev,
1459 struct amd_iommu *iommu,
1460 struct dma_ops_domain *dma_dom,
1467 dma_addr_t offset = paddr & ~PAGE_MASK;
1468 dma_addr_t address, start, ret;
1470 unsigned long align_mask = 0;
1473 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1476 INC_STATS_COUNTER(total_map_requests);
1479 INC_STATS_COUNTER(cross_page);
1482 align_mask = (1UL << get_order(size)) - 1;
1485 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1487 if (unlikely(address == bad_dma_address)) {
1489 * setting next_address here will let the address
1490 * allocator only scan the new allocated range in the
1491 * first run. This is a small optimization.
1493 dma_dom->next_address = dma_dom->aperture_size;
1495 if (alloc_new_range(iommu, dma_dom, false, GFP_ATOMIC))
1499 * aperture was sucessfully enlarged by 128 MB, try
1506 for (i = 0; i < pages; ++i) {
1507 ret = dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1508 if (ret == bad_dma_address)
1516 ADD_STATS_COUNTER(alloced_io_mem, size);
1518 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1519 iommu_flush_tlb(iommu, dma_dom->domain.id);
1520 dma_dom->need_flush = false;
1521 } else if (unlikely(iommu_has_npcache(iommu)))
1522 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1529 for (--i; i >= 0; --i) {
1531 dma_ops_domain_unmap(iommu, dma_dom, start);
1534 dma_ops_free_addresses(dma_dom, address, pages);
1536 return bad_dma_address;
1540 * Does the reverse of the __map_single function. Must be called with
1541 * the domain lock held too
1543 static void __unmap_single(struct amd_iommu *iommu,
1544 struct dma_ops_domain *dma_dom,
1545 dma_addr_t dma_addr,
1549 dma_addr_t i, start;
1552 if ((dma_addr == bad_dma_address) ||
1553 (dma_addr + size > dma_dom->aperture_size))
1556 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1557 dma_addr &= PAGE_MASK;
1560 for (i = 0; i < pages; ++i) {
1561 dma_ops_domain_unmap(iommu, dma_dom, start);
1565 SUB_STATS_COUNTER(alloced_io_mem, size);
1567 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1569 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1570 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1571 dma_dom->need_flush = false;
1576 * The exported map_single function for dma_ops.
1578 static dma_addr_t map_page(struct device *dev, struct page *page,
1579 unsigned long offset, size_t size,
1580 enum dma_data_direction dir,
1581 struct dma_attrs *attrs)
1583 unsigned long flags;
1584 struct amd_iommu *iommu;
1585 struct protection_domain *domain;
1589 phys_addr_t paddr = page_to_phys(page) + offset;
1591 INC_STATS_COUNTER(cnt_map_single);
1593 if (!check_device(dev))
1594 return bad_dma_address;
1596 dma_mask = *dev->dma_mask;
1598 get_device_resources(dev, &iommu, &domain, &devid);
1600 if (iommu == NULL || domain == NULL)
1601 /* device not handled by any AMD IOMMU */
1602 return (dma_addr_t)paddr;
1604 if (!dma_ops_domain(domain))
1605 return bad_dma_address;
1607 spin_lock_irqsave(&domain->lock, flags);
1608 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1610 if (addr == bad_dma_address)
1613 iommu_completion_wait(iommu);
1616 spin_unlock_irqrestore(&domain->lock, flags);
1622 * The exported unmap_single function for dma_ops.
1624 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1625 enum dma_data_direction dir, struct dma_attrs *attrs)
1627 unsigned long flags;
1628 struct amd_iommu *iommu;
1629 struct protection_domain *domain;
1632 INC_STATS_COUNTER(cnt_unmap_single);
1634 if (!check_device(dev) ||
1635 !get_device_resources(dev, &iommu, &domain, &devid))
1636 /* device not handled by any AMD IOMMU */
1639 if (!dma_ops_domain(domain))
1642 spin_lock_irqsave(&domain->lock, flags);
1644 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1646 iommu_completion_wait(iommu);
1648 spin_unlock_irqrestore(&domain->lock, flags);
1652 * This is a special map_sg function which is used if we should map a
1653 * device which is not handled by an AMD IOMMU in the system.
1655 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1656 int nelems, int dir)
1658 struct scatterlist *s;
1661 for_each_sg(sglist, s, nelems, i) {
1662 s->dma_address = (dma_addr_t)sg_phys(s);
1663 s->dma_length = s->length;
1670 * The exported map_sg function for dma_ops (handles scatter-gather
1673 static int map_sg(struct device *dev, struct scatterlist *sglist,
1674 int nelems, enum dma_data_direction dir,
1675 struct dma_attrs *attrs)
1677 unsigned long flags;
1678 struct amd_iommu *iommu;
1679 struct protection_domain *domain;
1682 struct scatterlist *s;
1684 int mapped_elems = 0;
1687 INC_STATS_COUNTER(cnt_map_sg);
1689 if (!check_device(dev))
1692 dma_mask = *dev->dma_mask;
1694 get_device_resources(dev, &iommu, &domain, &devid);
1696 if (!iommu || !domain)
1697 return map_sg_no_iommu(dev, sglist, nelems, dir);
1699 if (!dma_ops_domain(domain))
1702 spin_lock_irqsave(&domain->lock, flags);
1704 for_each_sg(sglist, s, nelems, i) {
1707 s->dma_address = __map_single(dev, iommu, domain->priv,
1708 paddr, s->length, dir, false,
1711 if (s->dma_address) {
1712 s->dma_length = s->length;
1718 iommu_completion_wait(iommu);
1721 spin_unlock_irqrestore(&domain->lock, flags);
1723 return mapped_elems;
1725 for_each_sg(sglist, s, mapped_elems, i) {
1727 __unmap_single(iommu, domain->priv, s->dma_address,
1728 s->dma_length, dir);
1729 s->dma_address = s->dma_length = 0;
1738 * The exported map_sg function for dma_ops (handles scatter-gather
1741 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1742 int nelems, enum dma_data_direction dir,
1743 struct dma_attrs *attrs)
1745 unsigned long flags;
1746 struct amd_iommu *iommu;
1747 struct protection_domain *domain;
1748 struct scatterlist *s;
1752 INC_STATS_COUNTER(cnt_unmap_sg);
1754 if (!check_device(dev) ||
1755 !get_device_resources(dev, &iommu, &domain, &devid))
1758 if (!dma_ops_domain(domain))
1761 spin_lock_irqsave(&domain->lock, flags);
1763 for_each_sg(sglist, s, nelems, i) {
1764 __unmap_single(iommu, domain->priv, s->dma_address,
1765 s->dma_length, dir);
1766 s->dma_address = s->dma_length = 0;
1769 iommu_completion_wait(iommu);
1771 spin_unlock_irqrestore(&domain->lock, flags);
1775 * The exported alloc_coherent function for dma_ops.
1777 static void *alloc_coherent(struct device *dev, size_t size,
1778 dma_addr_t *dma_addr, gfp_t flag)
1780 unsigned long flags;
1782 struct amd_iommu *iommu;
1783 struct protection_domain *domain;
1786 u64 dma_mask = dev->coherent_dma_mask;
1788 INC_STATS_COUNTER(cnt_alloc_coherent);
1790 if (!check_device(dev))
1793 if (!get_device_resources(dev, &iommu, &domain, &devid))
1794 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1797 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1801 paddr = virt_to_phys(virt_addr);
1803 if (!iommu || !domain) {
1804 *dma_addr = (dma_addr_t)paddr;
1808 if (!dma_ops_domain(domain))
1812 dma_mask = *dev->dma_mask;
1814 spin_lock_irqsave(&domain->lock, flags);
1816 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1817 size, DMA_BIDIRECTIONAL, true, dma_mask);
1819 if (*dma_addr == bad_dma_address) {
1820 spin_unlock_irqrestore(&domain->lock, flags);
1824 iommu_completion_wait(iommu);
1826 spin_unlock_irqrestore(&domain->lock, flags);
1832 free_pages((unsigned long)virt_addr, get_order(size));
1838 * The exported free_coherent function for dma_ops.
1840 static void free_coherent(struct device *dev, size_t size,
1841 void *virt_addr, dma_addr_t dma_addr)
1843 unsigned long flags;
1844 struct amd_iommu *iommu;
1845 struct protection_domain *domain;
1848 INC_STATS_COUNTER(cnt_free_coherent);
1850 if (!check_device(dev))
1853 get_device_resources(dev, &iommu, &domain, &devid);
1855 if (!iommu || !domain)
1858 if (!dma_ops_domain(domain))
1861 spin_lock_irqsave(&domain->lock, flags);
1863 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1865 iommu_completion_wait(iommu);
1867 spin_unlock_irqrestore(&domain->lock, flags);
1870 free_pages((unsigned long)virt_addr, get_order(size));
1874 * This function is called by the DMA layer to find out if we can handle a
1875 * particular device. It is part of the dma_ops.
1877 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1880 struct pci_dev *pcidev;
1882 /* No device or no PCI device */
1883 if (!dev || dev->bus != &pci_bus_type)
1886 pcidev = to_pci_dev(dev);
1888 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1890 /* Out of our scope? */
1891 if (bdf > amd_iommu_last_bdf)
1898 * The function for pre-allocating protection domains.
1900 * If the driver core informs the DMA layer if a driver grabs a device
1901 * we don't need to preallocate the protection domains anymore.
1902 * For now we have to.
1904 static void prealloc_protection_domains(void)
1906 struct pci_dev *dev = NULL;
1907 struct dma_ops_domain *dma_dom;
1908 struct amd_iommu *iommu;
1911 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1912 devid = calc_devid(dev->bus->number, dev->devfn);
1913 if (devid > amd_iommu_last_bdf)
1915 devid = amd_iommu_alias_table[devid];
1916 if (domain_for_device(devid))
1918 iommu = amd_iommu_rlookup_table[devid];
1921 dma_dom = dma_ops_domain_alloc(iommu);
1924 init_unity_mappings_for_device(dma_dom, devid);
1925 dma_dom->target_dev = devid;
1927 list_add_tail(&dma_dom->list, &iommu_pd_list);
1931 static struct dma_map_ops amd_iommu_dma_ops = {
1932 .alloc_coherent = alloc_coherent,
1933 .free_coherent = free_coherent,
1934 .map_page = map_page,
1935 .unmap_page = unmap_page,
1937 .unmap_sg = unmap_sg,
1938 .dma_supported = amd_iommu_dma_supported,
1942 * The function which clues the AMD IOMMU driver into dma_ops.
1944 int __init amd_iommu_init_dma_ops(void)
1946 struct amd_iommu *iommu;
1950 * first allocate a default protection domain for every IOMMU we
1951 * found in the system. Devices not assigned to any other
1952 * protection domain will be assigned to the default one.
1954 for_each_iommu(iommu) {
1955 iommu->default_dom = dma_ops_domain_alloc(iommu);
1956 if (iommu->default_dom == NULL)
1958 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1959 ret = iommu_init_unity_mappings(iommu);
1965 * If device isolation is enabled, pre-allocate the protection
1966 * domains for each device.
1968 if (amd_iommu_isolate)
1969 prealloc_protection_domains();
1973 bad_dma_address = 0;
1974 #ifdef CONFIG_GART_IOMMU
1975 gart_iommu_aperture_disabled = 1;
1976 gart_iommu_aperture = 0;
1979 /* Make the driver finally visible to the drivers */
1980 dma_ops = &amd_iommu_dma_ops;
1982 register_iommu(&amd_iommu_ops);
1984 bus_register_notifier(&pci_bus_type, &device_nb);
1986 amd_iommu_stats_init();
1992 for_each_iommu(iommu) {
1993 if (iommu->default_dom)
1994 dma_ops_domain_free(iommu->default_dom);
2000 /*****************************************************************************
2002 * The following functions belong to the exported interface of AMD IOMMU
2004 * This interface allows access to lower level functions of the IOMMU
2005 * like protection domain handling and assignement of devices to domains
2006 * which is not possible with the dma_ops interface.
2008 *****************************************************************************/
2010 static void cleanup_domain(struct protection_domain *domain)
2012 unsigned long flags;
2015 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2017 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2018 if (amd_iommu_pd_table[devid] == domain)
2019 __detach_device(domain, devid);
2021 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2024 static void protection_domain_free(struct protection_domain *domain)
2030 domain_id_free(domain->id);
2035 static struct protection_domain *protection_domain_alloc(void)
2037 struct protection_domain *domain;
2039 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2043 spin_lock_init(&domain->lock);
2044 domain->id = domain_id_alloc();
2056 static int amd_iommu_domain_init(struct iommu_domain *dom)
2058 struct protection_domain *domain;
2060 domain = protection_domain_alloc();
2064 domain->mode = PAGE_MODE_3_LEVEL;
2065 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2066 if (!domain->pt_root)
2074 protection_domain_free(domain);
2079 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2081 struct protection_domain *domain = dom->priv;
2086 if (domain->dev_cnt > 0)
2087 cleanup_domain(domain);
2089 BUG_ON(domain->dev_cnt != 0);
2091 free_pagetable(domain);
2093 domain_id_free(domain->id);
2100 static void amd_iommu_detach_device(struct iommu_domain *dom,
2103 struct protection_domain *domain = dom->priv;
2104 struct amd_iommu *iommu;
2105 struct pci_dev *pdev;
2108 if (dev->bus != &pci_bus_type)
2111 pdev = to_pci_dev(dev);
2113 devid = calc_devid(pdev->bus->number, pdev->devfn);
2116 detach_device(domain, devid);
2118 iommu = amd_iommu_rlookup_table[devid];
2122 iommu_queue_inv_dev_entry(iommu, devid);
2123 iommu_completion_wait(iommu);
2126 static int amd_iommu_attach_device(struct iommu_domain *dom,
2129 struct protection_domain *domain = dom->priv;
2130 struct protection_domain *old_domain;
2131 struct amd_iommu *iommu;
2132 struct pci_dev *pdev;
2135 if (dev->bus != &pci_bus_type)
2138 pdev = to_pci_dev(dev);
2140 devid = calc_devid(pdev->bus->number, pdev->devfn);
2142 if (devid >= amd_iommu_last_bdf ||
2143 devid != amd_iommu_alias_table[devid])
2146 iommu = amd_iommu_rlookup_table[devid];
2150 old_domain = domain_for_device(devid);
2152 detach_device(old_domain, devid);
2154 attach_device(iommu, domain, devid);
2156 iommu_completion_wait(iommu);
2161 static int amd_iommu_map_range(struct iommu_domain *dom,
2162 unsigned long iova, phys_addr_t paddr,
2163 size_t size, int iommu_prot)
2165 struct protection_domain *domain = dom->priv;
2166 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
2170 if (iommu_prot & IOMMU_READ)
2171 prot |= IOMMU_PROT_IR;
2172 if (iommu_prot & IOMMU_WRITE)
2173 prot |= IOMMU_PROT_IW;
2178 for (i = 0; i < npages; ++i) {
2179 ret = iommu_map_page(domain, iova, paddr, prot);
2190 static void amd_iommu_unmap_range(struct iommu_domain *dom,
2191 unsigned long iova, size_t size)
2194 struct protection_domain *domain = dom->priv;
2195 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
2199 for (i = 0; i < npages; ++i) {
2200 iommu_unmap_page(domain, iova);
2204 iommu_flush_domain(domain->id);
2207 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2210 struct protection_domain *domain = dom->priv;
2211 unsigned long offset = iova & ~PAGE_MASK;
2215 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
2217 if (!IOMMU_PTE_PRESENT(*pte))
2220 pte = IOMMU_PTE_PAGE(*pte);
2221 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
2223 if (!IOMMU_PTE_PRESENT(*pte))
2226 pte = IOMMU_PTE_PAGE(*pte);
2227 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
2229 if (!IOMMU_PTE_PRESENT(*pte))
2232 paddr = *pte & IOMMU_PAGE_MASK;
2238 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2244 static struct iommu_ops amd_iommu_ops = {
2245 .domain_init = amd_iommu_domain_init,
2246 .domain_destroy = amd_iommu_domain_destroy,
2247 .attach_dev = amd_iommu_attach_device,
2248 .detach_dev = amd_iommu_detach_device,
2249 .map = amd_iommu_map_range,
2250 .unmap = amd_iommu_unmap_range,
2251 .iova_to_phys = amd_iommu_iova_to_phys,
2252 .domain_has_cap = amd_iommu_domain_has_cap,
2255 /*****************************************************************************
2257 * The next functions do a basic initialization of IOMMU for pass through
2260 * In passthrough mode the IOMMU is initialized and enabled but not used for
2261 * DMA-API translation.
2263 *****************************************************************************/
2265 int __init amd_iommu_init_passthrough(void)
2267 struct pci_dev *dev = NULL;
2270 /* allocate passthroug domain */
2271 pt_domain = protection_domain_alloc();
2275 pt_domain->mode |= PAGE_MODE_NONE;
2277 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
2278 struct amd_iommu *iommu;
2280 devid = calc_devid(dev->bus->number, dev->devfn);
2281 if (devid > amd_iommu_last_bdf)
2284 devid2 = amd_iommu_alias_table[devid];
2286 iommu = amd_iommu_rlookup_table[devid2];
2290 __attach_device(iommu, pt_domain, devid);
2291 __attach_device(iommu, pt_domain, devid2);
2294 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");