2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/bitmap.h>
22 #include <linux/slab.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_proto.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37 #define EXIT_LOOP_COUNT 10000000
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
46 * Domain for untranslated devices - only allocated
47 * if iommu=pt passed on kernel cmd line.
49 static struct protection_domain *pt_domain;
51 static struct iommu_ops amd_iommu_ops;
54 * general struct to manage commands send to an IOMMU
60 static void reset_iommu_command_buffer(struct amd_iommu *iommu);
61 static void update_domain(struct protection_domain *domain);
63 /****************************************************************************
67 ****************************************************************************/
69 static inline u16 get_device_id(struct device *dev)
71 struct pci_dev *pdev = to_pci_dev(dev);
73 return calc_devid(pdev->bus->number, pdev->devfn);
76 static struct iommu_dev_data *get_dev_data(struct device *dev)
78 return dev->archdata.iommu;
82 * In this function the list of preallocated protection domains is traversed to
83 * find the domain for a specific device
85 static struct dma_ops_domain *find_protection_domain(u16 devid)
87 struct dma_ops_domain *entry, *ret = NULL;
89 u16 alias = amd_iommu_alias_table[devid];
91 if (list_empty(&iommu_pd_list))
94 spin_lock_irqsave(&iommu_pd_list_lock, flags);
96 list_for_each_entry(entry, &iommu_pd_list, list) {
97 if (entry->target_dev == devid ||
98 entry->target_dev == alias) {
104 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
110 * This function checks if the driver got a valid device from the caller to
111 * avoid dereferencing invalid pointers.
113 static bool check_device(struct device *dev)
117 if (!dev || !dev->dma_mask)
120 /* No device or no PCI device */
121 if (dev->bus != &pci_bus_type)
124 devid = get_device_id(dev);
126 /* Out of our scope? */
127 if (devid > amd_iommu_last_bdf)
130 if (amd_iommu_rlookup_table[devid] == NULL)
136 static int iommu_init_device(struct device *dev)
138 struct iommu_dev_data *dev_data;
139 struct pci_dev *pdev;
142 if (dev->archdata.iommu)
145 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
151 devid = get_device_id(dev);
152 alias = amd_iommu_alias_table[devid];
153 pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff);
155 dev_data->alias = &pdev->dev;
157 atomic_set(&dev_data->bind, 0);
159 dev->archdata.iommu = dev_data;
165 static void iommu_uninit_device(struct device *dev)
167 kfree(dev->archdata.iommu);
170 void __init amd_iommu_uninit_devices(void)
172 struct pci_dev *pdev = NULL;
174 for_each_pci_dev(pdev) {
176 if (!check_device(&pdev->dev))
179 iommu_uninit_device(&pdev->dev);
183 int __init amd_iommu_init_devices(void)
185 struct pci_dev *pdev = NULL;
188 for_each_pci_dev(pdev) {
190 if (!check_device(&pdev->dev))
193 ret = iommu_init_device(&pdev->dev);
202 amd_iommu_uninit_devices();
206 #ifdef CONFIG_AMD_IOMMU_STATS
209 * Initialization code for statistics collection
212 DECLARE_STATS_COUNTER(compl_wait);
213 DECLARE_STATS_COUNTER(cnt_map_single);
214 DECLARE_STATS_COUNTER(cnt_unmap_single);
215 DECLARE_STATS_COUNTER(cnt_map_sg);
216 DECLARE_STATS_COUNTER(cnt_unmap_sg);
217 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
218 DECLARE_STATS_COUNTER(cnt_free_coherent);
219 DECLARE_STATS_COUNTER(cross_page);
220 DECLARE_STATS_COUNTER(domain_flush_single);
221 DECLARE_STATS_COUNTER(domain_flush_all);
222 DECLARE_STATS_COUNTER(alloced_io_mem);
223 DECLARE_STATS_COUNTER(total_map_requests);
225 static struct dentry *stats_dir;
226 static struct dentry *de_fflush;
228 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
230 if (stats_dir == NULL)
233 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
237 static void amd_iommu_stats_init(void)
239 stats_dir = debugfs_create_dir("amd-iommu", NULL);
240 if (stats_dir == NULL)
243 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
244 (u32 *)&amd_iommu_unmap_flush);
246 amd_iommu_stats_add(&compl_wait);
247 amd_iommu_stats_add(&cnt_map_single);
248 amd_iommu_stats_add(&cnt_unmap_single);
249 amd_iommu_stats_add(&cnt_map_sg);
250 amd_iommu_stats_add(&cnt_unmap_sg);
251 amd_iommu_stats_add(&cnt_alloc_coherent);
252 amd_iommu_stats_add(&cnt_free_coherent);
253 amd_iommu_stats_add(&cross_page);
254 amd_iommu_stats_add(&domain_flush_single);
255 amd_iommu_stats_add(&domain_flush_all);
256 amd_iommu_stats_add(&alloced_io_mem);
257 amd_iommu_stats_add(&total_map_requests);
262 /****************************************************************************
264 * Interrupt handling functions
266 ****************************************************************************/
268 static void dump_dte_entry(u16 devid)
272 for (i = 0; i < 8; ++i)
273 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
274 amd_iommu_dev_table[devid].data[i]);
277 static void dump_command(unsigned long phys_addr)
279 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
282 for (i = 0; i < 4; ++i)
283 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
286 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
289 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
290 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
291 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
292 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
293 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
295 printk(KERN_ERR "AMD-Vi: Event logged [");
298 case EVENT_TYPE_ILL_DEV:
299 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
300 "address=0x%016llx flags=0x%04x]\n",
301 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
303 dump_dte_entry(devid);
305 case EVENT_TYPE_IO_FAULT:
306 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
307 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
308 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
309 domid, address, flags);
311 case EVENT_TYPE_DEV_TAB_ERR:
312 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
313 "address=0x%016llx flags=0x%04x]\n",
314 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
317 case EVENT_TYPE_PAGE_TAB_ERR:
318 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
319 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
320 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
321 domid, address, flags);
323 case EVENT_TYPE_ILL_CMD:
324 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
325 iommu->reset_in_progress = true;
326 reset_iommu_command_buffer(iommu);
327 dump_command(address);
329 case EVENT_TYPE_CMD_HARD_ERR:
330 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
331 "flags=0x%04x]\n", address, flags);
333 case EVENT_TYPE_IOTLB_INV_TO:
334 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
335 "address=0x%016llx]\n",
336 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
339 case EVENT_TYPE_INV_DEV_REQ:
340 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
341 "address=0x%016llx flags=0x%04x]\n",
342 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
346 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
350 static void iommu_poll_events(struct amd_iommu *iommu)
355 spin_lock_irqsave(&iommu->lock, flags);
357 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
358 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
360 while (head != tail) {
361 iommu_print_event(iommu, iommu->evt_buf + head);
362 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
365 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
367 spin_unlock_irqrestore(&iommu->lock, flags);
370 irqreturn_t amd_iommu_int_handler(int irq, void *data)
372 struct amd_iommu *iommu;
374 for_each_iommu(iommu)
375 iommu_poll_events(iommu);
380 /****************************************************************************
382 * IOMMU command queuing functions
384 ****************************************************************************/
386 static void build_completion_wait(struct iommu_cmd *cmd)
388 memset(cmd, 0, sizeof(*cmd));
389 cmd->data[0] = CMD_COMPL_WAIT_INT_MASK;
390 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
393 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
395 memset(cmd, 0, sizeof(*cmd));
396 cmd->data[0] = devid;
397 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
401 * Writes the command to the IOMMUs command buffer and informs the
402 * hardware about the new command. Must be called with iommu->lock held.
404 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
409 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
410 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
411 target = iommu->cmd_buf + tail;
412 memcpy_toio(target, cmd, sizeof(*cmd));
413 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
414 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
417 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
423 * General queuing function for commands. Takes iommu->lock and calls
424 * __iommu_queue_command().
426 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
431 spin_lock_irqsave(&iommu->lock, flags);
432 ret = __iommu_queue_command(iommu, cmd);
434 iommu->need_sync = true;
435 spin_unlock_irqrestore(&iommu->lock, flags);
441 * This function waits until an IOMMU has completed a completion
444 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
450 INC_STATS_COUNTER(compl_wait);
452 while (!ready && (i < EXIT_LOOP_COUNT)) {
454 /* wait for the bit to become one */
455 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
456 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
459 /* set bit back to zero */
460 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
461 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
463 if (unlikely(i == EXIT_LOOP_COUNT))
464 iommu->reset_in_progress = true;
468 * This function queues a completion wait command into the command
471 static int __iommu_completion_wait(struct amd_iommu *iommu)
473 struct iommu_cmd cmd;
475 build_completion_wait(&cmd);
477 return __iommu_queue_command(iommu, &cmd);
481 * This function is called whenever we need to ensure that the IOMMU has
482 * completed execution of all commands we sent. It sends a
483 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
484 * us about that by writing a value to a physical address we pass with
487 static int iommu_completion_wait(struct amd_iommu *iommu)
492 spin_lock_irqsave(&iommu->lock, flags);
494 if (!iommu->need_sync)
497 ret = __iommu_completion_wait(iommu);
499 iommu->need_sync = false;
504 __iommu_wait_for_completion(iommu);
507 spin_unlock_irqrestore(&iommu->lock, flags);
509 if (iommu->reset_in_progress)
510 reset_iommu_command_buffer(iommu);
515 static void iommu_flush_complete(struct protection_domain *domain)
519 for (i = 0; i < amd_iommus_present; ++i) {
520 if (!domain->dev_iommu[i])
524 * Devices of this domain are behind this IOMMU
525 * We need to wait for completion of all commands.
527 iommu_completion_wait(amd_iommus[i]);
532 * Command send function for invalidating a device table entry
534 static int iommu_flush_device(struct device *dev)
536 struct amd_iommu *iommu;
537 struct iommu_cmd cmd;
540 devid = get_device_id(dev);
541 iommu = amd_iommu_rlookup_table[devid];
543 build_inv_dte(&cmd, devid);
545 return iommu_queue_command(iommu, &cmd);
548 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
549 u16 domid, int pde, int s)
551 memset(cmd, 0, sizeof(*cmd));
552 address &= PAGE_MASK;
553 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
554 cmd->data[1] |= domid;
555 cmd->data[2] = lower_32_bits(address);
556 cmd->data[3] = upper_32_bits(address);
557 if (s) /* size bit - we flush more than one 4kb page */
558 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
559 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
560 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
564 * Generic command send function for invalidaing TLB entries
566 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
567 u64 address, u16 domid, int pde, int s)
569 struct iommu_cmd cmd;
572 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
574 ret = iommu_queue_command(iommu, &cmd);
580 * TLB invalidation function which is called from the mapping functions.
581 * It invalidates a single PTE if the range to flush is within a single
582 * page. Otherwise it flushes the whole TLB of the IOMMU.
584 static void __iommu_flush_pages(struct protection_domain *domain,
585 u64 address, size_t size, int pde)
588 unsigned long pages = iommu_num_pages(address, size, PAGE_SIZE);
590 address &= PAGE_MASK;
594 * If we have to flush more than one page, flush all
595 * TLB entries for this domain
597 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
602 for (i = 0; i < amd_iommus_present; ++i) {
603 if (!domain->dev_iommu[i])
607 * Devices of this domain are behind this IOMMU
608 * We need a TLB flush
610 iommu_queue_inv_iommu_pages(amd_iommus[i], address,
617 static void iommu_flush_pages(struct protection_domain *domain,
618 u64 address, size_t size)
620 __iommu_flush_pages(domain, address, size, 0);
623 /* Flush the whole IO/TLB for a given protection domain */
624 static void iommu_flush_tlb(struct protection_domain *domain)
626 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
629 /* Flush the whole IO/TLB for a given protection domain - including PDE */
630 static void iommu_flush_tlb_pde(struct protection_domain *domain)
632 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
637 * This function flushes the DTEs for all devices in domain
639 static void iommu_flush_domain_devices(struct protection_domain *domain)
641 struct iommu_dev_data *dev_data;
644 spin_lock_irqsave(&domain->lock, flags);
646 list_for_each_entry(dev_data, &domain->dev_list, list)
647 iommu_flush_device(dev_data->dev);
649 spin_unlock_irqrestore(&domain->lock, flags);
652 static void iommu_flush_all_domain_devices(void)
654 struct protection_domain *domain;
657 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
659 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
660 iommu_flush_domain_devices(domain);
661 iommu_flush_complete(domain);
664 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
667 void amd_iommu_flush_all_devices(void)
669 iommu_flush_all_domain_devices();
673 * This function uses heavy locking and may disable irqs for some time. But
674 * this is no issue because it is only called during resume.
676 void amd_iommu_flush_all_domains(void)
678 struct protection_domain *domain;
681 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
683 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
684 spin_lock(&domain->lock);
685 iommu_flush_tlb_pde(domain);
686 iommu_flush_complete(domain);
687 spin_unlock(&domain->lock);
690 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
693 static void reset_iommu_command_buffer(struct amd_iommu *iommu)
695 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
697 if (iommu->reset_in_progress)
698 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
700 amd_iommu_reset_cmd_buffer(iommu);
701 amd_iommu_flush_all_devices();
702 amd_iommu_flush_all_domains();
704 iommu->reset_in_progress = false;
707 /****************************************************************************
709 * The functions below are used the create the page table mappings for
710 * unity mapped regions.
712 ****************************************************************************/
715 * This function is used to add another level to an IO page table. Adding
716 * another level increases the size of the address space by 9 bits to a size up
719 static bool increase_address_space(struct protection_domain *domain,
724 if (domain->mode == PAGE_MODE_6_LEVEL)
725 /* address space already 64 bit large */
728 pte = (void *)get_zeroed_page(gfp);
732 *pte = PM_LEVEL_PDE(domain->mode,
733 virt_to_phys(domain->pt_root));
734 domain->pt_root = pte;
736 domain->updated = true;
741 static u64 *alloc_pte(struct protection_domain *domain,
742 unsigned long address,
743 unsigned long page_size,
750 BUG_ON(!is_power_of_2(page_size));
752 while (address > PM_LEVEL_SIZE(domain->mode))
753 increase_address_space(domain, gfp);
755 level = domain->mode - 1;
756 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
757 address = PAGE_SIZE_ALIGN(address, page_size);
758 end_lvl = PAGE_SIZE_LEVEL(page_size);
760 while (level > end_lvl) {
761 if (!IOMMU_PTE_PRESENT(*pte)) {
762 page = (u64 *)get_zeroed_page(gfp);
765 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
768 /* No level skipping support yet */
769 if (PM_PTE_LEVEL(*pte) != level)
774 pte = IOMMU_PTE_PAGE(*pte);
776 if (pte_page && level == end_lvl)
779 pte = &pte[PM_LEVEL_INDEX(level, address)];
786 * This function checks if there is a PTE for a given dma address. If
787 * there is one, it returns the pointer to it.
789 static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
794 if (address > PM_LEVEL_SIZE(domain->mode))
797 level = domain->mode - 1;
798 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
803 if (!IOMMU_PTE_PRESENT(*pte))
807 if (PM_PTE_LEVEL(*pte) == 0x07) {
808 unsigned long pte_mask, __pte;
811 * If we have a series of large PTEs, make
812 * sure to return a pointer to the first one.
814 pte_mask = PTE_PAGE_SIZE(*pte);
815 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
816 __pte = ((unsigned long)pte) & pte_mask;
821 /* No level skipping support yet */
822 if (PM_PTE_LEVEL(*pte) != level)
827 /* Walk to the next level */
828 pte = IOMMU_PTE_PAGE(*pte);
829 pte = &pte[PM_LEVEL_INDEX(level, address)];
836 * Generic mapping functions. It maps a physical address into a DMA
837 * address space. It allocates the page table pages if necessary.
838 * In the future it can be extended to a generic mapping function
839 * supporting all features of AMD IOMMU page tables like level skipping
840 * and full 64 bit address spaces.
842 static int iommu_map_page(struct protection_domain *dom,
843 unsigned long bus_addr,
844 unsigned long phys_addr,
846 unsigned long page_size)
851 if (!(prot & IOMMU_PROT_MASK))
854 bus_addr = PAGE_ALIGN(bus_addr);
855 phys_addr = PAGE_ALIGN(phys_addr);
856 count = PAGE_SIZE_PTE_COUNT(page_size);
857 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
859 for (i = 0; i < count; ++i)
860 if (IOMMU_PTE_PRESENT(pte[i]))
863 if (page_size > PAGE_SIZE) {
864 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
865 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
867 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
869 if (prot & IOMMU_PROT_IR)
870 __pte |= IOMMU_PTE_IR;
871 if (prot & IOMMU_PROT_IW)
872 __pte |= IOMMU_PTE_IW;
874 for (i = 0; i < count; ++i)
882 static unsigned long iommu_unmap_page(struct protection_domain *dom,
883 unsigned long bus_addr,
884 unsigned long page_size)
886 unsigned long long unmap_size, unmapped;
889 BUG_ON(!is_power_of_2(page_size));
893 while (unmapped < page_size) {
895 pte = fetch_pte(dom, bus_addr);
899 * No PTE for this address
900 * move forward in 4kb steps
902 unmap_size = PAGE_SIZE;
903 } else if (PM_PTE_LEVEL(*pte) == 0) {
904 /* 4kb PTE found for this address */
905 unmap_size = PAGE_SIZE;
910 /* Large PTE found which maps this address */
911 unmap_size = PTE_PAGE_SIZE(*pte);
912 count = PAGE_SIZE_PTE_COUNT(unmap_size);
913 for (i = 0; i < count; i++)
917 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
918 unmapped += unmap_size;
921 BUG_ON(!is_power_of_2(unmapped));
927 * This function checks if a specific unity mapping entry is needed for
928 * this specific IOMMU.
930 static int iommu_for_unity_map(struct amd_iommu *iommu,
931 struct unity_map_entry *entry)
935 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
936 bdf = amd_iommu_alias_table[i];
937 if (amd_iommu_rlookup_table[bdf] == iommu)
945 * This function actually applies the mapping to the page table of the
948 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
949 struct unity_map_entry *e)
954 for (addr = e->address_start; addr < e->address_end;
956 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
961 * if unity mapping is in aperture range mark the page
962 * as allocated in the aperture
964 if (addr < dma_dom->aperture_size)
965 __set_bit(addr >> PAGE_SHIFT,
966 dma_dom->aperture[0]->bitmap);
973 * Init the unity mappings for a specific IOMMU in the system
975 * Basically iterates over all unity mapping entries and applies them to
976 * the default domain DMA of that IOMMU if necessary.
978 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
980 struct unity_map_entry *entry;
983 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
984 if (!iommu_for_unity_map(iommu, entry))
986 ret = dma_ops_unity_map(iommu->default_dom, entry);
995 * Inits the unity mappings required for a specific device
997 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1000 struct unity_map_entry *e;
1003 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1004 if (!(devid >= e->devid_start && devid <= e->devid_end))
1006 ret = dma_ops_unity_map(dma_dom, e);
1014 /****************************************************************************
1016 * The next functions belong to the address allocator for the dma_ops
1017 * interface functions. They work like the allocators in the other IOMMU
1018 * drivers. Its basically a bitmap which marks the allocated pages in
1019 * the aperture. Maybe it could be enhanced in the future to a more
1020 * efficient allocator.
1022 ****************************************************************************/
1025 * The address allocator core functions.
1027 * called with domain->lock held
1031 * Used to reserve address ranges in the aperture (e.g. for exclusion
1034 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1035 unsigned long start_page,
1038 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1040 if (start_page + pages > last_page)
1041 pages = last_page - start_page;
1043 for (i = start_page; i < start_page + pages; ++i) {
1044 int index = i / APERTURE_RANGE_PAGES;
1045 int page = i % APERTURE_RANGE_PAGES;
1046 __set_bit(page, dom->aperture[index]->bitmap);
1051 * This function is used to add a new aperture range to an existing
1052 * aperture in case of dma_ops domain allocation or address allocation
1055 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1056 bool populate, gfp_t gfp)
1058 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1059 struct amd_iommu *iommu;
1062 #ifdef CONFIG_IOMMU_STRESS
1066 if (index >= APERTURE_MAX_RANGES)
1069 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1070 if (!dma_dom->aperture[index])
1073 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1074 if (!dma_dom->aperture[index]->bitmap)
1077 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1080 unsigned long address = dma_dom->aperture_size;
1081 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1082 u64 *pte, *pte_page;
1084 for (i = 0; i < num_ptes; ++i) {
1085 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1090 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1092 address += APERTURE_RANGE_SIZE / 64;
1096 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1098 /* Initialize the exclusion range if necessary */
1099 for_each_iommu(iommu) {
1100 if (iommu->exclusion_start &&
1101 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1102 && iommu->exclusion_start < dma_dom->aperture_size) {
1103 unsigned long startpage;
1104 int pages = iommu_num_pages(iommu->exclusion_start,
1105 iommu->exclusion_length,
1107 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1108 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1113 * Check for areas already mapped as present in the new aperture
1114 * range and mark those pages as reserved in the allocator. Such
1115 * mappings may already exist as a result of requested unity
1116 * mappings for devices.
1118 for (i = dma_dom->aperture[index]->offset;
1119 i < dma_dom->aperture_size;
1121 u64 *pte = fetch_pte(&dma_dom->domain, i);
1122 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1125 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
1128 update_domain(&dma_dom->domain);
1133 update_domain(&dma_dom->domain);
1135 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1137 kfree(dma_dom->aperture[index]);
1138 dma_dom->aperture[index] = NULL;
1143 static unsigned long dma_ops_area_alloc(struct device *dev,
1144 struct dma_ops_domain *dom,
1146 unsigned long align_mask,
1148 unsigned long start)
1150 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1151 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1152 int i = start >> APERTURE_RANGE_SHIFT;
1153 unsigned long boundary_size;
1154 unsigned long address = -1;
1155 unsigned long limit;
1157 next_bit >>= PAGE_SHIFT;
1159 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1160 PAGE_SIZE) >> PAGE_SHIFT;
1162 for (;i < max_index; ++i) {
1163 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1165 if (dom->aperture[i]->offset >= dma_mask)
1168 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1169 dma_mask >> PAGE_SHIFT);
1171 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1172 limit, next_bit, pages, 0,
1173 boundary_size, align_mask);
1174 if (address != -1) {
1175 address = dom->aperture[i]->offset +
1176 (address << PAGE_SHIFT);
1177 dom->next_address = address + (pages << PAGE_SHIFT);
1187 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1188 struct dma_ops_domain *dom,
1190 unsigned long align_mask,
1193 unsigned long address;
1195 #ifdef CONFIG_IOMMU_STRESS
1196 dom->next_address = 0;
1197 dom->need_flush = true;
1200 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1201 dma_mask, dom->next_address);
1203 if (address == -1) {
1204 dom->next_address = 0;
1205 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1207 dom->need_flush = true;
1210 if (unlikely(address == -1))
1211 address = DMA_ERROR_CODE;
1213 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1219 * The address free function.
1221 * called with domain->lock held
1223 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1224 unsigned long address,
1227 unsigned i = address >> APERTURE_RANGE_SHIFT;
1228 struct aperture_range *range = dom->aperture[i];
1230 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1232 #ifdef CONFIG_IOMMU_STRESS
1237 if (address >= dom->next_address)
1238 dom->need_flush = true;
1240 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1242 bitmap_clear(range->bitmap, address, pages);
1246 /****************************************************************************
1248 * The next functions belong to the domain allocation. A domain is
1249 * allocated for every IOMMU as the default domain. If device isolation
1250 * is enabled, every device get its own domain. The most important thing
1251 * about domains is the page table mapping the DMA address space they
1254 ****************************************************************************/
1257 * This function adds a protection domain to the global protection domain list
1259 static void add_domain_to_list(struct protection_domain *domain)
1261 unsigned long flags;
1263 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1264 list_add(&domain->list, &amd_iommu_pd_list);
1265 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1269 * This function removes a protection domain to the global
1270 * protection domain list
1272 static void del_domain_from_list(struct protection_domain *domain)
1274 unsigned long flags;
1276 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1277 list_del(&domain->list);
1278 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1281 static u16 domain_id_alloc(void)
1283 unsigned long flags;
1286 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1287 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1289 if (id > 0 && id < MAX_DOMAIN_ID)
1290 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1293 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1298 static void domain_id_free(int id)
1300 unsigned long flags;
1302 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1303 if (id > 0 && id < MAX_DOMAIN_ID)
1304 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1305 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1308 static void free_pagetable(struct protection_domain *domain)
1313 p1 = domain->pt_root;
1318 for (i = 0; i < 512; ++i) {
1319 if (!IOMMU_PTE_PRESENT(p1[i]))
1322 p2 = IOMMU_PTE_PAGE(p1[i]);
1323 for (j = 0; j < 512; ++j) {
1324 if (!IOMMU_PTE_PRESENT(p2[j]))
1326 p3 = IOMMU_PTE_PAGE(p2[j]);
1327 free_page((unsigned long)p3);
1330 free_page((unsigned long)p2);
1333 free_page((unsigned long)p1);
1335 domain->pt_root = NULL;
1339 * Free a domain, only used if something went wrong in the
1340 * allocation path and we need to free an already allocated page table
1342 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1349 del_domain_from_list(&dom->domain);
1351 free_pagetable(&dom->domain);
1353 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1354 if (!dom->aperture[i])
1356 free_page((unsigned long)dom->aperture[i]->bitmap);
1357 kfree(dom->aperture[i]);
1364 * Allocates a new protection domain usable for the dma_ops functions.
1365 * It also initializes the page table and the address allocator data
1366 * structures required for the dma_ops interface
1368 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1370 struct dma_ops_domain *dma_dom;
1372 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1376 spin_lock_init(&dma_dom->domain.lock);
1378 dma_dom->domain.id = domain_id_alloc();
1379 if (dma_dom->domain.id == 0)
1381 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1382 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1383 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1384 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1385 dma_dom->domain.priv = dma_dom;
1386 if (!dma_dom->domain.pt_root)
1389 dma_dom->need_flush = false;
1390 dma_dom->target_dev = 0xffff;
1392 add_domain_to_list(&dma_dom->domain);
1394 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1398 * mark the first page as allocated so we never return 0 as
1399 * a valid dma-address. So we can use 0 as error value
1401 dma_dom->aperture[0]->bitmap[0] = 1;
1402 dma_dom->next_address = 0;
1408 dma_ops_domain_free(dma_dom);
1414 * little helper function to check whether a given protection domain is a
1417 static bool dma_ops_domain(struct protection_domain *domain)
1419 return domain->flags & PD_DMA_OPS_MASK;
1422 static void set_dte_entry(u16 devid, struct protection_domain *domain)
1424 u64 pte_root = virt_to_phys(domain->pt_root);
1426 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1427 << DEV_ENTRY_MODE_SHIFT;
1428 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1430 amd_iommu_dev_table[devid].data[2] = domain->id;
1431 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1432 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1435 static void clear_dte_entry(u16 devid)
1437 /* remove entry from the device table seen by the hardware */
1438 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1439 amd_iommu_dev_table[devid].data[1] = 0;
1440 amd_iommu_dev_table[devid].data[2] = 0;
1442 amd_iommu_apply_erratum_63(devid);
1445 static void do_attach(struct device *dev, struct protection_domain *domain)
1447 struct iommu_dev_data *dev_data;
1448 struct amd_iommu *iommu;
1451 devid = get_device_id(dev);
1452 iommu = amd_iommu_rlookup_table[devid];
1453 dev_data = get_dev_data(dev);
1455 /* Update data structures */
1456 dev_data->domain = domain;
1457 list_add(&dev_data->list, &domain->dev_list);
1458 set_dte_entry(devid, domain);
1460 /* Do reference counting */
1461 domain->dev_iommu[iommu->index] += 1;
1462 domain->dev_cnt += 1;
1464 /* Flush the DTE entry */
1465 iommu_flush_device(dev);
1468 static void do_detach(struct device *dev)
1470 struct iommu_dev_data *dev_data;
1471 struct amd_iommu *iommu;
1474 devid = get_device_id(dev);
1475 iommu = amd_iommu_rlookup_table[devid];
1476 dev_data = get_dev_data(dev);
1478 /* decrease reference counters */
1479 dev_data->domain->dev_iommu[iommu->index] -= 1;
1480 dev_data->domain->dev_cnt -= 1;
1482 /* Update data structures */
1483 dev_data->domain = NULL;
1484 list_del(&dev_data->list);
1485 clear_dte_entry(devid);
1487 /* Flush the DTE entry */
1488 iommu_flush_device(dev);
1492 * If a device is not yet associated with a domain, this function does
1493 * assigns it visible for the hardware
1495 static int __attach_device(struct device *dev,
1496 struct protection_domain *domain)
1498 struct iommu_dev_data *dev_data, *alias_data;
1501 dev_data = get_dev_data(dev);
1502 alias_data = get_dev_data(dev_data->alias);
1508 spin_lock(&domain->lock);
1510 /* Some sanity checks */
1512 if (alias_data->domain != NULL &&
1513 alias_data->domain != domain)
1516 if (dev_data->domain != NULL &&
1517 dev_data->domain != domain)
1520 /* Do real assignment */
1521 if (dev_data->alias != dev) {
1522 alias_data = get_dev_data(dev_data->alias);
1523 if (alias_data->domain == NULL)
1524 do_attach(dev_data->alias, domain);
1526 atomic_inc(&alias_data->bind);
1529 if (dev_data->domain == NULL)
1530 do_attach(dev, domain);
1532 atomic_inc(&dev_data->bind);
1539 spin_unlock(&domain->lock);
1545 * If a device is not yet associated with a domain, this function does
1546 * assigns it visible for the hardware
1548 static int attach_device(struct device *dev,
1549 struct protection_domain *domain)
1551 unsigned long flags;
1554 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1555 ret = __attach_device(dev, domain);
1556 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1559 * We might boot into a crash-kernel here. The crashed kernel
1560 * left the caches in the IOMMU dirty. So we have to flush
1561 * here to evict all dirty stuff.
1563 iommu_flush_tlb_pde(domain);
1569 * Removes a device from a protection domain (unlocked)
1571 static void __detach_device(struct device *dev)
1573 struct iommu_dev_data *dev_data = get_dev_data(dev);
1574 struct iommu_dev_data *alias_data;
1575 struct protection_domain *domain;
1576 unsigned long flags;
1578 BUG_ON(!dev_data->domain);
1580 domain = dev_data->domain;
1582 spin_lock_irqsave(&domain->lock, flags);
1584 if (dev_data->alias != dev) {
1585 alias_data = get_dev_data(dev_data->alias);
1586 if (atomic_dec_and_test(&alias_data->bind))
1587 do_detach(dev_data->alias);
1590 if (atomic_dec_and_test(&dev_data->bind))
1593 spin_unlock_irqrestore(&domain->lock, flags);
1596 * If we run in passthrough mode the device must be assigned to the
1597 * passthrough domain if it is detached from any other domain.
1598 * Make sure we can deassign from the pt_domain itself.
1600 if (iommu_pass_through &&
1601 (dev_data->domain == NULL && domain != pt_domain))
1602 __attach_device(dev, pt_domain);
1606 * Removes a device from a protection domain (with devtable_lock held)
1608 static void detach_device(struct device *dev)
1610 unsigned long flags;
1612 /* lock device table */
1613 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1614 __detach_device(dev);
1615 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1619 * Find out the protection domain structure for a given PCI device. This
1620 * will give us the pointer to the page table root for example.
1622 static struct protection_domain *domain_for_device(struct device *dev)
1624 struct protection_domain *dom;
1625 struct iommu_dev_data *dev_data, *alias_data;
1626 unsigned long flags;
1629 devid = get_device_id(dev);
1630 alias = amd_iommu_alias_table[devid];
1631 dev_data = get_dev_data(dev);
1632 alias_data = get_dev_data(dev_data->alias);
1636 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1637 dom = dev_data->domain;
1639 alias_data->domain != NULL) {
1640 __attach_device(dev, alias_data->domain);
1641 dom = alias_data->domain;
1644 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1649 static int device_change_notifier(struct notifier_block *nb,
1650 unsigned long action, void *data)
1652 struct device *dev = data;
1654 struct protection_domain *domain;
1655 struct dma_ops_domain *dma_domain;
1656 struct amd_iommu *iommu;
1657 unsigned long flags;
1659 if (!check_device(dev))
1662 devid = get_device_id(dev);
1663 iommu = amd_iommu_rlookup_table[devid];
1666 case BUS_NOTIFY_UNBOUND_DRIVER:
1668 domain = domain_for_device(dev);
1672 if (iommu_pass_through)
1676 case BUS_NOTIFY_ADD_DEVICE:
1678 iommu_init_device(dev);
1680 domain = domain_for_device(dev);
1682 /* allocate a protection domain if a device is added */
1683 dma_domain = find_protection_domain(devid);
1686 dma_domain = dma_ops_domain_alloc();
1689 dma_domain->target_dev = devid;
1691 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1692 list_add_tail(&dma_domain->list, &iommu_pd_list);
1693 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1696 case BUS_NOTIFY_DEL_DEVICE:
1698 iommu_uninit_device(dev);
1704 iommu_flush_device(dev);
1705 iommu_completion_wait(iommu);
1711 static struct notifier_block device_nb = {
1712 .notifier_call = device_change_notifier,
1715 void amd_iommu_init_notifier(void)
1717 bus_register_notifier(&pci_bus_type, &device_nb);
1720 /*****************************************************************************
1722 * The next functions belong to the dma_ops mapping/unmapping code.
1724 *****************************************************************************/
1727 * In the dma_ops path we only have the struct device. This function
1728 * finds the corresponding IOMMU, the protection domain and the
1729 * requestor id for a given device.
1730 * If the device is not yet associated with a domain this is also done
1733 static struct protection_domain *get_domain(struct device *dev)
1735 struct protection_domain *domain;
1736 struct dma_ops_domain *dma_dom;
1737 u16 devid = get_device_id(dev);
1739 if (!check_device(dev))
1740 return ERR_PTR(-EINVAL);
1742 domain = domain_for_device(dev);
1743 if (domain != NULL && !dma_ops_domain(domain))
1744 return ERR_PTR(-EBUSY);
1749 /* Device not bount yet - bind it */
1750 dma_dom = find_protection_domain(devid);
1752 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
1753 attach_device(dev, &dma_dom->domain);
1754 DUMP_printk("Using protection domain %d for device %s\n",
1755 dma_dom->domain.id, dev_name(dev));
1757 return &dma_dom->domain;
1760 static void update_device_table(struct protection_domain *domain)
1762 struct iommu_dev_data *dev_data;
1764 list_for_each_entry(dev_data, &domain->dev_list, list) {
1765 u16 devid = get_device_id(dev_data->dev);
1766 set_dte_entry(devid, domain);
1770 static void update_domain(struct protection_domain *domain)
1772 if (!domain->updated)
1775 update_device_table(domain);
1776 iommu_flush_domain_devices(domain);
1777 iommu_flush_tlb_pde(domain);
1779 domain->updated = false;
1783 * This function fetches the PTE for a given address in the aperture
1785 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1786 unsigned long address)
1788 struct aperture_range *aperture;
1789 u64 *pte, *pte_page;
1791 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1795 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1797 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
1799 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1801 pte += PM_LEVEL_INDEX(0, address);
1803 update_domain(&dom->domain);
1809 * This is the generic map function. It maps one 4kb page at paddr to
1810 * the given address in the DMA address space for the domain.
1812 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
1813 unsigned long address,
1819 WARN_ON(address > dom->aperture_size);
1823 pte = dma_ops_get_pte(dom, address);
1825 return DMA_ERROR_CODE;
1827 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1829 if (direction == DMA_TO_DEVICE)
1830 __pte |= IOMMU_PTE_IR;
1831 else if (direction == DMA_FROM_DEVICE)
1832 __pte |= IOMMU_PTE_IW;
1833 else if (direction == DMA_BIDIRECTIONAL)
1834 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1840 return (dma_addr_t)address;
1844 * The generic unmapping function for on page in the DMA address space.
1846 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
1847 unsigned long address)
1849 struct aperture_range *aperture;
1852 if (address >= dom->aperture_size)
1855 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1859 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1863 pte += PM_LEVEL_INDEX(0, address);
1871 * This function contains common code for mapping of a physically
1872 * contiguous memory region into DMA address space. It is used by all
1873 * mapping functions provided with this IOMMU driver.
1874 * Must be called with the domain lock held.
1876 static dma_addr_t __map_single(struct device *dev,
1877 struct dma_ops_domain *dma_dom,
1884 dma_addr_t offset = paddr & ~PAGE_MASK;
1885 dma_addr_t address, start, ret;
1887 unsigned long align_mask = 0;
1890 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1893 INC_STATS_COUNTER(total_map_requests);
1896 INC_STATS_COUNTER(cross_page);
1899 align_mask = (1UL << get_order(size)) - 1;
1902 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1904 if (unlikely(address == DMA_ERROR_CODE)) {
1906 * setting next_address here will let the address
1907 * allocator only scan the new allocated range in the
1908 * first run. This is a small optimization.
1910 dma_dom->next_address = dma_dom->aperture_size;
1912 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
1916 * aperture was successfully enlarged by 128 MB, try
1923 for (i = 0; i < pages; ++i) {
1924 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
1925 if (ret == DMA_ERROR_CODE)
1933 ADD_STATS_COUNTER(alloced_io_mem, size);
1935 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1936 iommu_flush_tlb(&dma_dom->domain);
1937 dma_dom->need_flush = false;
1938 } else if (unlikely(amd_iommu_np_cache))
1939 iommu_flush_pages(&dma_dom->domain, address, size);
1946 for (--i; i >= 0; --i) {
1948 dma_ops_domain_unmap(dma_dom, start);
1951 dma_ops_free_addresses(dma_dom, address, pages);
1953 return DMA_ERROR_CODE;
1957 * Does the reverse of the __map_single function. Must be called with
1958 * the domain lock held too
1960 static void __unmap_single(struct dma_ops_domain *dma_dom,
1961 dma_addr_t dma_addr,
1965 dma_addr_t flush_addr;
1966 dma_addr_t i, start;
1969 if ((dma_addr == DMA_ERROR_CODE) ||
1970 (dma_addr + size > dma_dom->aperture_size))
1973 flush_addr = dma_addr;
1974 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1975 dma_addr &= PAGE_MASK;
1978 for (i = 0; i < pages; ++i) {
1979 dma_ops_domain_unmap(dma_dom, start);
1983 SUB_STATS_COUNTER(alloced_io_mem, size);
1985 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1987 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1988 iommu_flush_pages(&dma_dom->domain, flush_addr, size);
1989 dma_dom->need_flush = false;
1994 * The exported map_single function for dma_ops.
1996 static dma_addr_t map_page(struct device *dev, struct page *page,
1997 unsigned long offset, size_t size,
1998 enum dma_data_direction dir,
1999 struct dma_attrs *attrs)
2001 unsigned long flags;
2002 struct protection_domain *domain;
2005 phys_addr_t paddr = page_to_phys(page) + offset;
2007 INC_STATS_COUNTER(cnt_map_single);
2009 domain = get_domain(dev);
2010 if (PTR_ERR(domain) == -EINVAL)
2011 return (dma_addr_t)paddr;
2012 else if (IS_ERR(domain))
2013 return DMA_ERROR_CODE;
2015 dma_mask = *dev->dma_mask;
2017 spin_lock_irqsave(&domain->lock, flags);
2019 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2021 if (addr == DMA_ERROR_CODE)
2024 iommu_flush_complete(domain);
2027 spin_unlock_irqrestore(&domain->lock, flags);
2033 * The exported unmap_single function for dma_ops.
2035 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2036 enum dma_data_direction dir, struct dma_attrs *attrs)
2038 unsigned long flags;
2039 struct protection_domain *domain;
2041 INC_STATS_COUNTER(cnt_unmap_single);
2043 domain = get_domain(dev);
2047 spin_lock_irqsave(&domain->lock, flags);
2049 __unmap_single(domain->priv, dma_addr, size, dir);
2051 iommu_flush_complete(domain);
2053 spin_unlock_irqrestore(&domain->lock, flags);
2057 * This is a special map_sg function which is used if we should map a
2058 * device which is not handled by an AMD IOMMU in the system.
2060 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
2061 int nelems, int dir)
2063 struct scatterlist *s;
2066 for_each_sg(sglist, s, nelems, i) {
2067 s->dma_address = (dma_addr_t)sg_phys(s);
2068 s->dma_length = s->length;
2075 * The exported map_sg function for dma_ops (handles scatter-gather
2078 static int map_sg(struct device *dev, struct scatterlist *sglist,
2079 int nelems, enum dma_data_direction dir,
2080 struct dma_attrs *attrs)
2082 unsigned long flags;
2083 struct protection_domain *domain;
2085 struct scatterlist *s;
2087 int mapped_elems = 0;
2090 INC_STATS_COUNTER(cnt_map_sg);
2092 domain = get_domain(dev);
2093 if (PTR_ERR(domain) == -EINVAL)
2094 return map_sg_no_iommu(dev, sglist, nelems, dir);
2095 else if (IS_ERR(domain))
2098 dma_mask = *dev->dma_mask;
2100 spin_lock_irqsave(&domain->lock, flags);
2102 for_each_sg(sglist, s, nelems, i) {
2105 s->dma_address = __map_single(dev, domain->priv,
2106 paddr, s->length, dir, false,
2109 if (s->dma_address) {
2110 s->dma_length = s->length;
2116 iommu_flush_complete(domain);
2119 spin_unlock_irqrestore(&domain->lock, flags);
2121 return mapped_elems;
2123 for_each_sg(sglist, s, mapped_elems, i) {
2125 __unmap_single(domain->priv, s->dma_address,
2126 s->dma_length, dir);
2127 s->dma_address = s->dma_length = 0;
2136 * The exported map_sg function for dma_ops (handles scatter-gather
2139 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2140 int nelems, enum dma_data_direction dir,
2141 struct dma_attrs *attrs)
2143 unsigned long flags;
2144 struct protection_domain *domain;
2145 struct scatterlist *s;
2148 INC_STATS_COUNTER(cnt_unmap_sg);
2150 domain = get_domain(dev);
2154 spin_lock_irqsave(&domain->lock, flags);
2156 for_each_sg(sglist, s, nelems, i) {
2157 __unmap_single(domain->priv, s->dma_address,
2158 s->dma_length, dir);
2159 s->dma_address = s->dma_length = 0;
2162 iommu_flush_complete(domain);
2164 spin_unlock_irqrestore(&domain->lock, flags);
2168 * The exported alloc_coherent function for dma_ops.
2170 static void *alloc_coherent(struct device *dev, size_t size,
2171 dma_addr_t *dma_addr, gfp_t flag)
2173 unsigned long flags;
2175 struct protection_domain *domain;
2177 u64 dma_mask = dev->coherent_dma_mask;
2179 INC_STATS_COUNTER(cnt_alloc_coherent);
2181 domain = get_domain(dev);
2182 if (PTR_ERR(domain) == -EINVAL) {
2183 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2184 *dma_addr = __pa(virt_addr);
2186 } else if (IS_ERR(domain))
2189 dma_mask = dev->coherent_dma_mask;
2190 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2193 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2197 paddr = virt_to_phys(virt_addr);
2200 dma_mask = *dev->dma_mask;
2202 spin_lock_irqsave(&domain->lock, flags);
2204 *dma_addr = __map_single(dev, domain->priv, paddr,
2205 size, DMA_BIDIRECTIONAL, true, dma_mask);
2207 if (*dma_addr == DMA_ERROR_CODE) {
2208 spin_unlock_irqrestore(&domain->lock, flags);
2212 iommu_flush_complete(domain);
2214 spin_unlock_irqrestore(&domain->lock, flags);
2220 free_pages((unsigned long)virt_addr, get_order(size));
2226 * The exported free_coherent function for dma_ops.
2228 static void free_coherent(struct device *dev, size_t size,
2229 void *virt_addr, dma_addr_t dma_addr)
2231 unsigned long flags;
2232 struct protection_domain *domain;
2234 INC_STATS_COUNTER(cnt_free_coherent);
2236 domain = get_domain(dev);
2240 spin_lock_irqsave(&domain->lock, flags);
2242 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2244 iommu_flush_complete(domain);
2246 spin_unlock_irqrestore(&domain->lock, flags);
2249 free_pages((unsigned long)virt_addr, get_order(size));
2253 * This function is called by the DMA layer to find out if we can handle a
2254 * particular device. It is part of the dma_ops.
2256 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2258 return check_device(dev);
2262 * The function for pre-allocating protection domains.
2264 * If the driver core informs the DMA layer if a driver grabs a device
2265 * we don't need to preallocate the protection domains anymore.
2266 * For now we have to.
2268 static void prealloc_protection_domains(void)
2270 struct pci_dev *dev = NULL;
2271 struct dma_ops_domain *dma_dom;
2274 for_each_pci_dev(dev) {
2276 /* Do we handle this device? */
2277 if (!check_device(&dev->dev))
2280 /* Is there already any domain for it? */
2281 if (domain_for_device(&dev->dev))
2284 devid = get_device_id(&dev->dev);
2286 dma_dom = dma_ops_domain_alloc();
2289 init_unity_mappings_for_device(dma_dom, devid);
2290 dma_dom->target_dev = devid;
2292 attach_device(&dev->dev, &dma_dom->domain);
2294 list_add_tail(&dma_dom->list, &iommu_pd_list);
2298 static struct dma_map_ops amd_iommu_dma_ops = {
2299 .alloc_coherent = alloc_coherent,
2300 .free_coherent = free_coherent,
2301 .map_page = map_page,
2302 .unmap_page = unmap_page,
2304 .unmap_sg = unmap_sg,
2305 .dma_supported = amd_iommu_dma_supported,
2309 * The function which clues the AMD IOMMU driver into dma_ops.
2312 void __init amd_iommu_init_api(void)
2314 register_iommu(&amd_iommu_ops);
2317 int __init amd_iommu_init_dma_ops(void)
2319 struct amd_iommu *iommu;
2323 * first allocate a default protection domain for every IOMMU we
2324 * found in the system. Devices not assigned to any other
2325 * protection domain will be assigned to the default one.
2327 for_each_iommu(iommu) {
2328 iommu->default_dom = dma_ops_domain_alloc();
2329 if (iommu->default_dom == NULL)
2331 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2332 ret = iommu_init_unity_mappings(iommu);
2338 * Pre-allocate the protection domains for each device.
2340 prealloc_protection_domains();
2345 /* Make the driver finally visible to the drivers */
2346 dma_ops = &amd_iommu_dma_ops;
2348 amd_iommu_stats_init();
2354 for_each_iommu(iommu) {
2355 if (iommu->default_dom)
2356 dma_ops_domain_free(iommu->default_dom);
2362 /*****************************************************************************
2364 * The following functions belong to the exported interface of AMD IOMMU
2366 * This interface allows access to lower level functions of the IOMMU
2367 * like protection domain handling and assignement of devices to domains
2368 * which is not possible with the dma_ops interface.
2370 *****************************************************************************/
2372 static void cleanup_domain(struct protection_domain *domain)
2374 struct iommu_dev_data *dev_data, *next;
2375 unsigned long flags;
2377 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2379 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
2380 struct device *dev = dev_data->dev;
2382 __detach_device(dev);
2383 atomic_set(&dev_data->bind, 0);
2386 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2389 static void protection_domain_free(struct protection_domain *domain)
2394 del_domain_from_list(domain);
2397 domain_id_free(domain->id);
2402 static struct protection_domain *protection_domain_alloc(void)
2404 struct protection_domain *domain;
2406 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2410 spin_lock_init(&domain->lock);
2411 mutex_init(&domain->api_lock);
2412 domain->id = domain_id_alloc();
2415 INIT_LIST_HEAD(&domain->dev_list);
2417 add_domain_to_list(domain);
2427 static int amd_iommu_domain_init(struct iommu_domain *dom)
2429 struct protection_domain *domain;
2431 domain = protection_domain_alloc();
2435 domain->mode = PAGE_MODE_3_LEVEL;
2436 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2437 if (!domain->pt_root)
2445 protection_domain_free(domain);
2450 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2452 struct protection_domain *domain = dom->priv;
2457 if (domain->dev_cnt > 0)
2458 cleanup_domain(domain);
2460 BUG_ON(domain->dev_cnt != 0);
2462 free_pagetable(domain);
2464 protection_domain_free(domain);
2469 static void amd_iommu_detach_device(struct iommu_domain *dom,
2472 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2473 struct amd_iommu *iommu;
2476 if (!check_device(dev))
2479 devid = get_device_id(dev);
2481 if (dev_data->domain != NULL)
2484 iommu = amd_iommu_rlookup_table[devid];
2488 iommu_flush_device(dev);
2489 iommu_completion_wait(iommu);
2492 static int amd_iommu_attach_device(struct iommu_domain *dom,
2495 struct protection_domain *domain = dom->priv;
2496 struct iommu_dev_data *dev_data;
2497 struct amd_iommu *iommu;
2501 if (!check_device(dev))
2504 dev_data = dev->archdata.iommu;
2506 devid = get_device_id(dev);
2508 iommu = amd_iommu_rlookup_table[devid];
2512 if (dev_data->domain)
2515 ret = attach_device(dev, domain);
2517 iommu_completion_wait(iommu);
2522 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2523 phys_addr_t paddr, int gfp_order, int iommu_prot)
2525 unsigned long page_size = 0x1000UL << gfp_order;
2526 struct protection_domain *domain = dom->priv;
2530 if (iommu_prot & IOMMU_READ)
2531 prot |= IOMMU_PROT_IR;
2532 if (iommu_prot & IOMMU_WRITE)
2533 prot |= IOMMU_PROT_IW;
2535 mutex_lock(&domain->api_lock);
2536 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
2537 mutex_unlock(&domain->api_lock);
2542 static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2545 struct protection_domain *domain = dom->priv;
2546 unsigned long page_size, unmap_size;
2548 page_size = 0x1000UL << gfp_order;
2550 mutex_lock(&domain->api_lock);
2551 unmap_size = iommu_unmap_page(domain, iova, page_size);
2552 mutex_unlock(&domain->api_lock);
2554 iommu_flush_tlb_pde(domain);
2556 return get_order(unmap_size);
2559 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2562 struct protection_domain *domain = dom->priv;
2563 unsigned long offset_mask;
2567 pte = fetch_pte(domain, iova);
2569 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2572 if (PM_PTE_LEVEL(*pte) == 0)
2573 offset_mask = PAGE_SIZE - 1;
2575 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
2577 __pte = *pte & PM_ADDR_MASK;
2578 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
2583 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2587 case IOMMU_CAP_CACHE_COHERENCY:
2594 static struct iommu_ops amd_iommu_ops = {
2595 .domain_init = amd_iommu_domain_init,
2596 .domain_destroy = amd_iommu_domain_destroy,
2597 .attach_dev = amd_iommu_attach_device,
2598 .detach_dev = amd_iommu_detach_device,
2599 .map = amd_iommu_map,
2600 .unmap = amd_iommu_unmap,
2601 .iova_to_phys = amd_iommu_iova_to_phys,
2602 .domain_has_cap = amd_iommu_domain_has_cap,
2605 /*****************************************************************************
2607 * The next functions do a basic initialization of IOMMU for pass through
2610 * In passthrough mode the IOMMU is initialized and enabled but not used for
2611 * DMA-API translation.
2613 *****************************************************************************/
2615 int __init amd_iommu_init_passthrough(void)
2617 struct amd_iommu *iommu;
2618 struct pci_dev *dev = NULL;
2621 /* allocate passthrough domain */
2622 pt_domain = protection_domain_alloc();
2626 pt_domain->mode |= PAGE_MODE_NONE;
2628 for_each_pci_dev(dev) {
2629 if (!check_device(&dev->dev))
2632 devid = get_device_id(&dev->dev);
2634 iommu = amd_iommu_rlookup_table[devid];
2638 attach_device(&dev->dev, pt_domain);
2641 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");