2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/bitmap.h>
22 #include <linux/slab.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <linux/delay.h>
29 #include <asm/proto.h>
30 #include <asm/iommu.h>
32 #include <asm/amd_iommu_proto.h>
33 #include <asm/amd_iommu_types.h>
34 #include <asm/amd_iommu.h>
36 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
38 #define LOOP_TIMEOUT 100000
40 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
42 /* A list of preallocated protection domains */
43 static LIST_HEAD(iommu_pd_list);
44 static DEFINE_SPINLOCK(iommu_pd_list_lock);
47 * Domain for untranslated devices - only allocated
48 * if iommu=pt passed on kernel cmd line.
50 static struct protection_domain *pt_domain;
52 static struct iommu_ops amd_iommu_ops;
55 * general struct to manage commands send to an IOMMU
61 static void reset_iommu_command_buffer(struct amd_iommu *iommu);
62 static void update_domain(struct protection_domain *domain);
64 /****************************************************************************
68 ****************************************************************************/
70 static inline u16 get_device_id(struct device *dev)
72 struct pci_dev *pdev = to_pci_dev(dev);
74 return calc_devid(pdev->bus->number, pdev->devfn);
77 static struct iommu_dev_data *get_dev_data(struct device *dev)
79 return dev->archdata.iommu;
83 * In this function the list of preallocated protection domains is traversed to
84 * find the domain for a specific device
86 static struct dma_ops_domain *find_protection_domain(u16 devid)
88 struct dma_ops_domain *entry, *ret = NULL;
90 u16 alias = amd_iommu_alias_table[devid];
92 if (list_empty(&iommu_pd_list))
95 spin_lock_irqsave(&iommu_pd_list_lock, flags);
97 list_for_each_entry(entry, &iommu_pd_list, list) {
98 if (entry->target_dev == devid ||
99 entry->target_dev == alias) {
105 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
111 * This function checks if the driver got a valid device from the caller to
112 * avoid dereferencing invalid pointers.
114 static bool check_device(struct device *dev)
118 if (!dev || !dev->dma_mask)
121 /* No device or no PCI device */
122 if (dev->bus != &pci_bus_type)
125 devid = get_device_id(dev);
127 /* Out of our scope? */
128 if (devid > amd_iommu_last_bdf)
131 if (amd_iommu_rlookup_table[devid] == NULL)
137 static int iommu_init_device(struct device *dev)
139 struct iommu_dev_data *dev_data;
140 struct pci_dev *pdev;
143 if (dev->archdata.iommu)
146 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
152 devid = get_device_id(dev);
153 alias = amd_iommu_alias_table[devid];
154 pdev = pci_get_bus_and_slot(PCI_BUS(alias), alias & 0xff);
156 dev_data->alias = &pdev->dev;
158 atomic_set(&dev_data->bind, 0);
160 dev->archdata.iommu = dev_data;
166 static void iommu_uninit_device(struct device *dev)
168 kfree(dev->archdata.iommu);
171 void __init amd_iommu_uninit_devices(void)
173 struct pci_dev *pdev = NULL;
175 for_each_pci_dev(pdev) {
177 if (!check_device(&pdev->dev))
180 iommu_uninit_device(&pdev->dev);
184 int __init amd_iommu_init_devices(void)
186 struct pci_dev *pdev = NULL;
189 for_each_pci_dev(pdev) {
191 if (!check_device(&pdev->dev))
194 ret = iommu_init_device(&pdev->dev);
203 amd_iommu_uninit_devices();
207 #ifdef CONFIG_AMD_IOMMU_STATS
210 * Initialization code for statistics collection
213 DECLARE_STATS_COUNTER(compl_wait);
214 DECLARE_STATS_COUNTER(cnt_map_single);
215 DECLARE_STATS_COUNTER(cnt_unmap_single);
216 DECLARE_STATS_COUNTER(cnt_map_sg);
217 DECLARE_STATS_COUNTER(cnt_unmap_sg);
218 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
219 DECLARE_STATS_COUNTER(cnt_free_coherent);
220 DECLARE_STATS_COUNTER(cross_page);
221 DECLARE_STATS_COUNTER(domain_flush_single);
222 DECLARE_STATS_COUNTER(domain_flush_all);
223 DECLARE_STATS_COUNTER(alloced_io_mem);
224 DECLARE_STATS_COUNTER(total_map_requests);
226 static struct dentry *stats_dir;
227 static struct dentry *de_fflush;
229 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
231 if (stats_dir == NULL)
234 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
238 static void amd_iommu_stats_init(void)
240 stats_dir = debugfs_create_dir("amd-iommu", NULL);
241 if (stats_dir == NULL)
244 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
245 (u32 *)&amd_iommu_unmap_flush);
247 amd_iommu_stats_add(&compl_wait);
248 amd_iommu_stats_add(&cnt_map_single);
249 amd_iommu_stats_add(&cnt_unmap_single);
250 amd_iommu_stats_add(&cnt_map_sg);
251 amd_iommu_stats_add(&cnt_unmap_sg);
252 amd_iommu_stats_add(&cnt_alloc_coherent);
253 amd_iommu_stats_add(&cnt_free_coherent);
254 amd_iommu_stats_add(&cross_page);
255 amd_iommu_stats_add(&domain_flush_single);
256 amd_iommu_stats_add(&domain_flush_all);
257 amd_iommu_stats_add(&alloced_io_mem);
258 amd_iommu_stats_add(&total_map_requests);
263 /****************************************************************************
265 * Interrupt handling functions
267 ****************************************************************************/
269 static void dump_dte_entry(u16 devid)
273 for (i = 0; i < 8; ++i)
274 pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
275 amd_iommu_dev_table[devid].data[i]);
278 static void dump_command(unsigned long phys_addr)
280 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
283 for (i = 0; i < 4; ++i)
284 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
287 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
290 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
291 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
292 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
293 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
294 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
296 printk(KERN_ERR "AMD-Vi: Event logged [");
299 case EVENT_TYPE_ILL_DEV:
300 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
301 "address=0x%016llx flags=0x%04x]\n",
302 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
304 dump_dte_entry(devid);
306 case EVENT_TYPE_IO_FAULT:
307 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
308 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
309 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
310 domid, address, flags);
312 case EVENT_TYPE_DEV_TAB_ERR:
313 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
314 "address=0x%016llx flags=0x%04x]\n",
315 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
318 case EVENT_TYPE_PAGE_TAB_ERR:
319 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
320 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
321 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
322 domid, address, flags);
324 case EVENT_TYPE_ILL_CMD:
325 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
326 iommu->reset_in_progress = true;
327 reset_iommu_command_buffer(iommu);
328 dump_command(address);
330 case EVENT_TYPE_CMD_HARD_ERR:
331 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
332 "flags=0x%04x]\n", address, flags);
334 case EVENT_TYPE_IOTLB_INV_TO:
335 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
336 "address=0x%016llx]\n",
337 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
340 case EVENT_TYPE_INV_DEV_REQ:
341 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
342 "address=0x%016llx flags=0x%04x]\n",
343 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
347 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
351 static void iommu_poll_events(struct amd_iommu *iommu)
356 spin_lock_irqsave(&iommu->lock, flags);
358 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
359 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
361 while (head != tail) {
362 iommu_print_event(iommu, iommu->evt_buf + head);
363 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
366 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
368 spin_unlock_irqrestore(&iommu->lock, flags);
371 irqreturn_t amd_iommu_int_handler(int irq, void *data)
373 struct amd_iommu *iommu;
375 for_each_iommu(iommu)
376 iommu_poll_events(iommu);
381 /****************************************************************************
383 * IOMMU command queuing functions
385 ****************************************************************************/
387 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
389 WARN_ON(address & 0x7ULL);
391 memset(cmd, 0, sizeof(*cmd));
392 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
393 cmd->data[1] = upper_32_bits(__pa(address));
395 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
398 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
400 memset(cmd, 0, sizeof(*cmd));
401 cmd->data[0] = devid;
402 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
405 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
406 size_t size, u16 domid, int pde)
411 pages = iommu_num_pages(address, size, PAGE_SIZE);
416 * If we have to flush more than one page, flush all
417 * TLB entries for this domain
419 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
423 address &= PAGE_MASK;
425 memset(cmd, 0, sizeof(*cmd));
426 cmd->data[1] |= domid;
427 cmd->data[2] = lower_32_bits(address);
428 cmd->data[3] = upper_32_bits(address);
429 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
430 if (s) /* size bit - we flush more than one 4kb page */
431 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
432 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
433 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
437 * Writes the command to the IOMMUs command buffer and informs the
438 * hardware about the new command. Must be called with iommu->lock held.
440 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
446 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
447 spin_lock_irqsave(&iommu->lock, flags);
448 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
449 target = iommu->cmd_buf + tail;
450 memcpy_toio(target, cmd, sizeof(*cmd));
451 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
452 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
455 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
456 iommu->need_sync = true;
457 spin_unlock_irqrestore(&iommu->lock, flags);
463 * This function queues a completion wait command into the command
466 static int iommu_completion_wait(struct amd_iommu *iommu)
468 struct iommu_cmd cmd;
469 volatile u64 sem = 0;
472 if (!iommu->need_sync)
475 build_completion_wait(&cmd, (u64)&sem);
477 ret = iommu_queue_command(iommu, &cmd);
481 while (sem == 0 && i < LOOP_TIMEOUT) {
486 if (i == LOOP_TIMEOUT) {
487 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
488 iommu->reset_in_progress = true;
489 reset_iommu_command_buffer(iommu);
495 static void iommu_flush_complete(struct protection_domain *domain)
499 for (i = 0; i < amd_iommus_present; ++i) {
500 if (!domain->dev_iommu[i])
504 * Devices of this domain are behind this IOMMU
505 * We need to wait for completion of all commands.
507 iommu_completion_wait(amd_iommus[i]);
512 * Command send function for invalidating a device table entry
514 static int iommu_flush_device(struct device *dev)
516 struct amd_iommu *iommu;
517 struct iommu_cmd cmd;
520 devid = get_device_id(dev);
521 iommu = amd_iommu_rlookup_table[devid];
523 build_inv_dte(&cmd, devid);
525 return iommu_queue_command(iommu, &cmd);
529 * TLB invalidation function which is called from the mapping functions.
530 * It invalidates a single PTE if the range to flush is within a single
531 * page. Otherwise it flushes the whole TLB of the IOMMU.
533 static void __iommu_flush_pages(struct protection_domain *domain,
534 u64 address, size_t size, int pde)
536 struct iommu_cmd cmd;
539 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
541 for (i = 0; i < amd_iommus_present; ++i) {
542 if (!domain->dev_iommu[i])
546 * Devices of this domain are behind this IOMMU
547 * We need a TLB flush
549 ret |= iommu_queue_command(amd_iommus[i], &cmd);
555 static void iommu_flush_pages(struct protection_domain *domain,
556 u64 address, size_t size)
558 __iommu_flush_pages(domain, address, size, 0);
561 /* Flush the whole IO/TLB for a given protection domain */
562 static void iommu_flush_tlb(struct protection_domain *domain)
564 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
567 /* Flush the whole IO/TLB for a given protection domain - including PDE */
568 static void iommu_flush_tlb_pde(struct protection_domain *domain)
570 __iommu_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
575 * This function flushes the DTEs for all devices in domain
577 static void iommu_flush_domain_devices(struct protection_domain *domain)
579 struct iommu_dev_data *dev_data;
582 spin_lock_irqsave(&domain->lock, flags);
584 list_for_each_entry(dev_data, &domain->dev_list, list)
585 iommu_flush_device(dev_data->dev);
587 spin_unlock_irqrestore(&domain->lock, flags);
590 static void iommu_flush_all_domain_devices(void)
592 struct protection_domain *domain;
595 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
597 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
598 iommu_flush_domain_devices(domain);
599 iommu_flush_complete(domain);
602 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
605 void amd_iommu_flush_all_devices(void)
607 iommu_flush_all_domain_devices();
611 * This function uses heavy locking and may disable irqs for some time. But
612 * this is no issue because it is only called during resume.
614 void amd_iommu_flush_all_domains(void)
616 struct protection_domain *domain;
619 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
621 list_for_each_entry(domain, &amd_iommu_pd_list, list) {
622 spin_lock(&domain->lock);
623 iommu_flush_tlb_pde(domain);
624 iommu_flush_complete(domain);
625 spin_unlock(&domain->lock);
628 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
631 static void reset_iommu_command_buffer(struct amd_iommu *iommu)
633 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
635 if (iommu->reset_in_progress)
636 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
638 amd_iommu_reset_cmd_buffer(iommu);
639 amd_iommu_flush_all_devices();
640 amd_iommu_flush_all_domains();
642 iommu->reset_in_progress = false;
645 /****************************************************************************
647 * The functions below are used the create the page table mappings for
648 * unity mapped regions.
650 ****************************************************************************/
653 * This function is used to add another level to an IO page table. Adding
654 * another level increases the size of the address space by 9 bits to a size up
657 static bool increase_address_space(struct protection_domain *domain,
662 if (domain->mode == PAGE_MODE_6_LEVEL)
663 /* address space already 64 bit large */
666 pte = (void *)get_zeroed_page(gfp);
670 *pte = PM_LEVEL_PDE(domain->mode,
671 virt_to_phys(domain->pt_root));
672 domain->pt_root = pte;
674 domain->updated = true;
679 static u64 *alloc_pte(struct protection_domain *domain,
680 unsigned long address,
681 unsigned long page_size,
688 BUG_ON(!is_power_of_2(page_size));
690 while (address > PM_LEVEL_SIZE(domain->mode))
691 increase_address_space(domain, gfp);
693 level = domain->mode - 1;
694 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
695 address = PAGE_SIZE_ALIGN(address, page_size);
696 end_lvl = PAGE_SIZE_LEVEL(page_size);
698 while (level > end_lvl) {
699 if (!IOMMU_PTE_PRESENT(*pte)) {
700 page = (u64 *)get_zeroed_page(gfp);
703 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
706 /* No level skipping support yet */
707 if (PM_PTE_LEVEL(*pte) != level)
712 pte = IOMMU_PTE_PAGE(*pte);
714 if (pte_page && level == end_lvl)
717 pte = &pte[PM_LEVEL_INDEX(level, address)];
724 * This function checks if there is a PTE for a given dma address. If
725 * there is one, it returns the pointer to it.
727 static u64 *fetch_pte(struct protection_domain *domain, unsigned long address)
732 if (address > PM_LEVEL_SIZE(domain->mode))
735 level = domain->mode - 1;
736 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
741 if (!IOMMU_PTE_PRESENT(*pte))
745 if (PM_PTE_LEVEL(*pte) == 0x07) {
746 unsigned long pte_mask, __pte;
749 * If we have a series of large PTEs, make
750 * sure to return a pointer to the first one.
752 pte_mask = PTE_PAGE_SIZE(*pte);
753 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
754 __pte = ((unsigned long)pte) & pte_mask;
759 /* No level skipping support yet */
760 if (PM_PTE_LEVEL(*pte) != level)
765 /* Walk to the next level */
766 pte = IOMMU_PTE_PAGE(*pte);
767 pte = &pte[PM_LEVEL_INDEX(level, address)];
774 * Generic mapping functions. It maps a physical address into a DMA
775 * address space. It allocates the page table pages if necessary.
776 * In the future it can be extended to a generic mapping function
777 * supporting all features of AMD IOMMU page tables like level skipping
778 * and full 64 bit address spaces.
780 static int iommu_map_page(struct protection_domain *dom,
781 unsigned long bus_addr,
782 unsigned long phys_addr,
784 unsigned long page_size)
789 if (!(prot & IOMMU_PROT_MASK))
792 bus_addr = PAGE_ALIGN(bus_addr);
793 phys_addr = PAGE_ALIGN(phys_addr);
794 count = PAGE_SIZE_PTE_COUNT(page_size);
795 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
797 for (i = 0; i < count; ++i)
798 if (IOMMU_PTE_PRESENT(pte[i]))
801 if (page_size > PAGE_SIZE) {
802 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
803 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
805 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
807 if (prot & IOMMU_PROT_IR)
808 __pte |= IOMMU_PTE_IR;
809 if (prot & IOMMU_PROT_IW)
810 __pte |= IOMMU_PTE_IW;
812 for (i = 0; i < count; ++i)
820 static unsigned long iommu_unmap_page(struct protection_domain *dom,
821 unsigned long bus_addr,
822 unsigned long page_size)
824 unsigned long long unmap_size, unmapped;
827 BUG_ON(!is_power_of_2(page_size));
831 while (unmapped < page_size) {
833 pte = fetch_pte(dom, bus_addr);
837 * No PTE for this address
838 * move forward in 4kb steps
840 unmap_size = PAGE_SIZE;
841 } else if (PM_PTE_LEVEL(*pte) == 0) {
842 /* 4kb PTE found for this address */
843 unmap_size = PAGE_SIZE;
848 /* Large PTE found which maps this address */
849 unmap_size = PTE_PAGE_SIZE(*pte);
850 count = PAGE_SIZE_PTE_COUNT(unmap_size);
851 for (i = 0; i < count; i++)
855 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
856 unmapped += unmap_size;
859 BUG_ON(!is_power_of_2(unmapped));
865 * This function checks if a specific unity mapping entry is needed for
866 * this specific IOMMU.
868 static int iommu_for_unity_map(struct amd_iommu *iommu,
869 struct unity_map_entry *entry)
873 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
874 bdf = amd_iommu_alias_table[i];
875 if (amd_iommu_rlookup_table[bdf] == iommu)
883 * This function actually applies the mapping to the page table of the
886 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
887 struct unity_map_entry *e)
892 for (addr = e->address_start; addr < e->address_end;
894 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
899 * if unity mapping is in aperture range mark the page
900 * as allocated in the aperture
902 if (addr < dma_dom->aperture_size)
903 __set_bit(addr >> PAGE_SHIFT,
904 dma_dom->aperture[0]->bitmap);
911 * Init the unity mappings for a specific IOMMU in the system
913 * Basically iterates over all unity mapping entries and applies them to
914 * the default domain DMA of that IOMMU if necessary.
916 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
918 struct unity_map_entry *entry;
921 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
922 if (!iommu_for_unity_map(iommu, entry))
924 ret = dma_ops_unity_map(iommu->default_dom, entry);
933 * Inits the unity mappings required for a specific device
935 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
938 struct unity_map_entry *e;
941 list_for_each_entry(e, &amd_iommu_unity_map, list) {
942 if (!(devid >= e->devid_start && devid <= e->devid_end))
944 ret = dma_ops_unity_map(dma_dom, e);
952 /****************************************************************************
954 * The next functions belong to the address allocator for the dma_ops
955 * interface functions. They work like the allocators in the other IOMMU
956 * drivers. Its basically a bitmap which marks the allocated pages in
957 * the aperture. Maybe it could be enhanced in the future to a more
958 * efficient allocator.
960 ****************************************************************************/
963 * The address allocator core functions.
965 * called with domain->lock held
969 * Used to reserve address ranges in the aperture (e.g. for exclusion
972 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
973 unsigned long start_page,
976 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
978 if (start_page + pages > last_page)
979 pages = last_page - start_page;
981 for (i = start_page; i < start_page + pages; ++i) {
982 int index = i / APERTURE_RANGE_PAGES;
983 int page = i % APERTURE_RANGE_PAGES;
984 __set_bit(page, dom->aperture[index]->bitmap);
989 * This function is used to add a new aperture range to an existing
990 * aperture in case of dma_ops domain allocation or address allocation
993 static int alloc_new_range(struct dma_ops_domain *dma_dom,
994 bool populate, gfp_t gfp)
996 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
997 struct amd_iommu *iommu;
1000 #ifdef CONFIG_IOMMU_STRESS
1004 if (index >= APERTURE_MAX_RANGES)
1007 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1008 if (!dma_dom->aperture[index])
1011 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1012 if (!dma_dom->aperture[index]->bitmap)
1015 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1018 unsigned long address = dma_dom->aperture_size;
1019 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1020 u64 *pte, *pte_page;
1022 for (i = 0; i < num_ptes; ++i) {
1023 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1028 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1030 address += APERTURE_RANGE_SIZE / 64;
1034 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1036 /* Initialize the exclusion range if necessary */
1037 for_each_iommu(iommu) {
1038 if (iommu->exclusion_start &&
1039 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1040 && iommu->exclusion_start < dma_dom->aperture_size) {
1041 unsigned long startpage;
1042 int pages = iommu_num_pages(iommu->exclusion_start,
1043 iommu->exclusion_length,
1045 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1046 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1051 * Check for areas already mapped as present in the new aperture
1052 * range and mark those pages as reserved in the allocator. Such
1053 * mappings may already exist as a result of requested unity
1054 * mappings for devices.
1056 for (i = dma_dom->aperture[index]->offset;
1057 i < dma_dom->aperture_size;
1059 u64 *pte = fetch_pte(&dma_dom->domain, i);
1060 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1063 dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
1066 update_domain(&dma_dom->domain);
1071 update_domain(&dma_dom->domain);
1073 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1075 kfree(dma_dom->aperture[index]);
1076 dma_dom->aperture[index] = NULL;
1081 static unsigned long dma_ops_area_alloc(struct device *dev,
1082 struct dma_ops_domain *dom,
1084 unsigned long align_mask,
1086 unsigned long start)
1088 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1089 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1090 int i = start >> APERTURE_RANGE_SHIFT;
1091 unsigned long boundary_size;
1092 unsigned long address = -1;
1093 unsigned long limit;
1095 next_bit >>= PAGE_SHIFT;
1097 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1098 PAGE_SIZE) >> PAGE_SHIFT;
1100 for (;i < max_index; ++i) {
1101 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1103 if (dom->aperture[i]->offset >= dma_mask)
1106 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1107 dma_mask >> PAGE_SHIFT);
1109 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1110 limit, next_bit, pages, 0,
1111 boundary_size, align_mask);
1112 if (address != -1) {
1113 address = dom->aperture[i]->offset +
1114 (address << PAGE_SHIFT);
1115 dom->next_address = address + (pages << PAGE_SHIFT);
1125 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1126 struct dma_ops_domain *dom,
1128 unsigned long align_mask,
1131 unsigned long address;
1133 #ifdef CONFIG_IOMMU_STRESS
1134 dom->next_address = 0;
1135 dom->need_flush = true;
1138 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1139 dma_mask, dom->next_address);
1141 if (address == -1) {
1142 dom->next_address = 0;
1143 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1145 dom->need_flush = true;
1148 if (unlikely(address == -1))
1149 address = DMA_ERROR_CODE;
1151 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1157 * The address free function.
1159 * called with domain->lock held
1161 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1162 unsigned long address,
1165 unsigned i = address >> APERTURE_RANGE_SHIFT;
1166 struct aperture_range *range = dom->aperture[i];
1168 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1170 #ifdef CONFIG_IOMMU_STRESS
1175 if (address >= dom->next_address)
1176 dom->need_flush = true;
1178 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1180 bitmap_clear(range->bitmap, address, pages);
1184 /****************************************************************************
1186 * The next functions belong to the domain allocation. A domain is
1187 * allocated for every IOMMU as the default domain. If device isolation
1188 * is enabled, every device get its own domain. The most important thing
1189 * about domains is the page table mapping the DMA address space they
1192 ****************************************************************************/
1195 * This function adds a protection domain to the global protection domain list
1197 static void add_domain_to_list(struct protection_domain *domain)
1199 unsigned long flags;
1201 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1202 list_add(&domain->list, &amd_iommu_pd_list);
1203 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1207 * This function removes a protection domain to the global
1208 * protection domain list
1210 static void del_domain_from_list(struct protection_domain *domain)
1212 unsigned long flags;
1214 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1215 list_del(&domain->list);
1216 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1219 static u16 domain_id_alloc(void)
1221 unsigned long flags;
1224 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1225 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1227 if (id > 0 && id < MAX_DOMAIN_ID)
1228 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1231 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1236 static void domain_id_free(int id)
1238 unsigned long flags;
1240 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1241 if (id > 0 && id < MAX_DOMAIN_ID)
1242 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1243 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1246 static void free_pagetable(struct protection_domain *domain)
1251 p1 = domain->pt_root;
1256 for (i = 0; i < 512; ++i) {
1257 if (!IOMMU_PTE_PRESENT(p1[i]))
1260 p2 = IOMMU_PTE_PAGE(p1[i]);
1261 for (j = 0; j < 512; ++j) {
1262 if (!IOMMU_PTE_PRESENT(p2[j]))
1264 p3 = IOMMU_PTE_PAGE(p2[j]);
1265 free_page((unsigned long)p3);
1268 free_page((unsigned long)p2);
1271 free_page((unsigned long)p1);
1273 domain->pt_root = NULL;
1277 * Free a domain, only used if something went wrong in the
1278 * allocation path and we need to free an already allocated page table
1280 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1287 del_domain_from_list(&dom->domain);
1289 free_pagetable(&dom->domain);
1291 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1292 if (!dom->aperture[i])
1294 free_page((unsigned long)dom->aperture[i]->bitmap);
1295 kfree(dom->aperture[i]);
1302 * Allocates a new protection domain usable for the dma_ops functions.
1303 * It also initializes the page table and the address allocator data
1304 * structures required for the dma_ops interface
1306 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1308 struct dma_ops_domain *dma_dom;
1310 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1314 spin_lock_init(&dma_dom->domain.lock);
1316 dma_dom->domain.id = domain_id_alloc();
1317 if (dma_dom->domain.id == 0)
1319 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
1320 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
1321 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1322 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1323 dma_dom->domain.priv = dma_dom;
1324 if (!dma_dom->domain.pt_root)
1327 dma_dom->need_flush = false;
1328 dma_dom->target_dev = 0xffff;
1330 add_domain_to_list(&dma_dom->domain);
1332 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
1336 * mark the first page as allocated so we never return 0 as
1337 * a valid dma-address. So we can use 0 as error value
1339 dma_dom->aperture[0]->bitmap[0] = 1;
1340 dma_dom->next_address = 0;
1346 dma_ops_domain_free(dma_dom);
1352 * little helper function to check whether a given protection domain is a
1355 static bool dma_ops_domain(struct protection_domain *domain)
1357 return domain->flags & PD_DMA_OPS_MASK;
1360 static void set_dte_entry(u16 devid, struct protection_domain *domain)
1362 u64 pte_root = virt_to_phys(domain->pt_root);
1364 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1365 << DEV_ENTRY_MODE_SHIFT;
1366 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1368 amd_iommu_dev_table[devid].data[2] = domain->id;
1369 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
1370 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
1373 static void clear_dte_entry(u16 devid)
1375 /* remove entry from the device table seen by the hardware */
1376 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1377 amd_iommu_dev_table[devid].data[1] = 0;
1378 amd_iommu_dev_table[devid].data[2] = 0;
1380 amd_iommu_apply_erratum_63(devid);
1383 static void do_attach(struct device *dev, struct protection_domain *domain)
1385 struct iommu_dev_data *dev_data;
1386 struct amd_iommu *iommu;
1389 devid = get_device_id(dev);
1390 iommu = amd_iommu_rlookup_table[devid];
1391 dev_data = get_dev_data(dev);
1393 /* Update data structures */
1394 dev_data->domain = domain;
1395 list_add(&dev_data->list, &domain->dev_list);
1396 set_dte_entry(devid, domain);
1398 /* Do reference counting */
1399 domain->dev_iommu[iommu->index] += 1;
1400 domain->dev_cnt += 1;
1402 /* Flush the DTE entry */
1403 iommu_flush_device(dev);
1406 static void do_detach(struct device *dev)
1408 struct iommu_dev_data *dev_data;
1409 struct amd_iommu *iommu;
1412 devid = get_device_id(dev);
1413 iommu = amd_iommu_rlookup_table[devid];
1414 dev_data = get_dev_data(dev);
1416 /* decrease reference counters */
1417 dev_data->domain->dev_iommu[iommu->index] -= 1;
1418 dev_data->domain->dev_cnt -= 1;
1420 /* Update data structures */
1421 dev_data->domain = NULL;
1422 list_del(&dev_data->list);
1423 clear_dte_entry(devid);
1425 /* Flush the DTE entry */
1426 iommu_flush_device(dev);
1430 * If a device is not yet associated with a domain, this function does
1431 * assigns it visible for the hardware
1433 static int __attach_device(struct device *dev,
1434 struct protection_domain *domain)
1436 struct iommu_dev_data *dev_data, *alias_data;
1439 dev_data = get_dev_data(dev);
1440 alias_data = get_dev_data(dev_data->alias);
1446 spin_lock(&domain->lock);
1448 /* Some sanity checks */
1450 if (alias_data->domain != NULL &&
1451 alias_data->domain != domain)
1454 if (dev_data->domain != NULL &&
1455 dev_data->domain != domain)
1458 /* Do real assignment */
1459 if (dev_data->alias != dev) {
1460 alias_data = get_dev_data(dev_data->alias);
1461 if (alias_data->domain == NULL)
1462 do_attach(dev_data->alias, domain);
1464 atomic_inc(&alias_data->bind);
1467 if (dev_data->domain == NULL)
1468 do_attach(dev, domain);
1470 atomic_inc(&dev_data->bind);
1477 spin_unlock(&domain->lock);
1483 * If a device is not yet associated with a domain, this function does
1484 * assigns it visible for the hardware
1486 static int attach_device(struct device *dev,
1487 struct protection_domain *domain)
1489 unsigned long flags;
1492 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1493 ret = __attach_device(dev, domain);
1494 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1497 * We might boot into a crash-kernel here. The crashed kernel
1498 * left the caches in the IOMMU dirty. So we have to flush
1499 * here to evict all dirty stuff.
1501 iommu_flush_tlb_pde(domain);
1507 * Removes a device from a protection domain (unlocked)
1509 static void __detach_device(struct device *dev)
1511 struct iommu_dev_data *dev_data = get_dev_data(dev);
1512 struct iommu_dev_data *alias_data;
1513 struct protection_domain *domain;
1514 unsigned long flags;
1516 BUG_ON(!dev_data->domain);
1518 domain = dev_data->domain;
1520 spin_lock_irqsave(&domain->lock, flags);
1522 if (dev_data->alias != dev) {
1523 alias_data = get_dev_data(dev_data->alias);
1524 if (atomic_dec_and_test(&alias_data->bind))
1525 do_detach(dev_data->alias);
1528 if (atomic_dec_and_test(&dev_data->bind))
1531 spin_unlock_irqrestore(&domain->lock, flags);
1534 * If we run in passthrough mode the device must be assigned to the
1535 * passthrough domain if it is detached from any other domain.
1536 * Make sure we can deassign from the pt_domain itself.
1538 if (iommu_pass_through &&
1539 (dev_data->domain == NULL && domain != pt_domain))
1540 __attach_device(dev, pt_domain);
1544 * Removes a device from a protection domain (with devtable_lock held)
1546 static void detach_device(struct device *dev)
1548 unsigned long flags;
1550 /* lock device table */
1551 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1552 __detach_device(dev);
1553 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1557 * Find out the protection domain structure for a given PCI device. This
1558 * will give us the pointer to the page table root for example.
1560 static struct protection_domain *domain_for_device(struct device *dev)
1562 struct protection_domain *dom;
1563 struct iommu_dev_data *dev_data, *alias_data;
1564 unsigned long flags;
1567 devid = get_device_id(dev);
1568 alias = amd_iommu_alias_table[devid];
1569 dev_data = get_dev_data(dev);
1570 alias_data = get_dev_data(dev_data->alias);
1574 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
1575 dom = dev_data->domain;
1577 alias_data->domain != NULL) {
1578 __attach_device(dev, alias_data->domain);
1579 dom = alias_data->domain;
1582 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1587 static int device_change_notifier(struct notifier_block *nb,
1588 unsigned long action, void *data)
1590 struct device *dev = data;
1592 struct protection_domain *domain;
1593 struct dma_ops_domain *dma_domain;
1594 struct amd_iommu *iommu;
1595 unsigned long flags;
1597 if (!check_device(dev))
1600 devid = get_device_id(dev);
1601 iommu = amd_iommu_rlookup_table[devid];
1604 case BUS_NOTIFY_UNBOUND_DRIVER:
1606 domain = domain_for_device(dev);
1610 if (iommu_pass_through)
1614 case BUS_NOTIFY_ADD_DEVICE:
1616 iommu_init_device(dev);
1618 domain = domain_for_device(dev);
1620 /* allocate a protection domain if a device is added */
1621 dma_domain = find_protection_domain(devid);
1624 dma_domain = dma_ops_domain_alloc();
1627 dma_domain->target_dev = devid;
1629 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1630 list_add_tail(&dma_domain->list, &iommu_pd_list);
1631 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1634 case BUS_NOTIFY_DEL_DEVICE:
1636 iommu_uninit_device(dev);
1642 iommu_flush_device(dev);
1643 iommu_completion_wait(iommu);
1649 static struct notifier_block device_nb = {
1650 .notifier_call = device_change_notifier,
1653 void amd_iommu_init_notifier(void)
1655 bus_register_notifier(&pci_bus_type, &device_nb);
1658 /*****************************************************************************
1660 * The next functions belong to the dma_ops mapping/unmapping code.
1662 *****************************************************************************/
1665 * In the dma_ops path we only have the struct device. This function
1666 * finds the corresponding IOMMU, the protection domain and the
1667 * requestor id for a given device.
1668 * If the device is not yet associated with a domain this is also done
1671 static struct protection_domain *get_domain(struct device *dev)
1673 struct protection_domain *domain;
1674 struct dma_ops_domain *dma_dom;
1675 u16 devid = get_device_id(dev);
1677 if (!check_device(dev))
1678 return ERR_PTR(-EINVAL);
1680 domain = domain_for_device(dev);
1681 if (domain != NULL && !dma_ops_domain(domain))
1682 return ERR_PTR(-EBUSY);
1687 /* Device not bount yet - bind it */
1688 dma_dom = find_protection_domain(devid);
1690 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
1691 attach_device(dev, &dma_dom->domain);
1692 DUMP_printk("Using protection domain %d for device %s\n",
1693 dma_dom->domain.id, dev_name(dev));
1695 return &dma_dom->domain;
1698 static void update_device_table(struct protection_domain *domain)
1700 struct iommu_dev_data *dev_data;
1702 list_for_each_entry(dev_data, &domain->dev_list, list) {
1703 u16 devid = get_device_id(dev_data->dev);
1704 set_dte_entry(devid, domain);
1708 static void update_domain(struct protection_domain *domain)
1710 if (!domain->updated)
1713 update_device_table(domain);
1714 iommu_flush_domain_devices(domain);
1715 iommu_flush_tlb_pde(domain);
1717 domain->updated = false;
1721 * This function fetches the PTE for a given address in the aperture
1723 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
1724 unsigned long address)
1726 struct aperture_range *aperture;
1727 u64 *pte, *pte_page;
1729 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1733 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1735 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
1737 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
1739 pte += PM_LEVEL_INDEX(0, address);
1741 update_domain(&dom->domain);
1747 * This is the generic map function. It maps one 4kb page at paddr to
1748 * the given address in the DMA address space for the domain.
1750 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
1751 unsigned long address,
1757 WARN_ON(address > dom->aperture_size);
1761 pte = dma_ops_get_pte(dom, address);
1763 return DMA_ERROR_CODE;
1765 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1767 if (direction == DMA_TO_DEVICE)
1768 __pte |= IOMMU_PTE_IR;
1769 else if (direction == DMA_FROM_DEVICE)
1770 __pte |= IOMMU_PTE_IW;
1771 else if (direction == DMA_BIDIRECTIONAL)
1772 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1778 return (dma_addr_t)address;
1782 * The generic unmapping function for on page in the DMA address space.
1784 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
1785 unsigned long address)
1787 struct aperture_range *aperture;
1790 if (address >= dom->aperture_size)
1793 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
1797 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
1801 pte += PM_LEVEL_INDEX(0, address);
1809 * This function contains common code for mapping of a physically
1810 * contiguous memory region into DMA address space. It is used by all
1811 * mapping functions provided with this IOMMU driver.
1812 * Must be called with the domain lock held.
1814 static dma_addr_t __map_single(struct device *dev,
1815 struct dma_ops_domain *dma_dom,
1822 dma_addr_t offset = paddr & ~PAGE_MASK;
1823 dma_addr_t address, start, ret;
1825 unsigned long align_mask = 0;
1828 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1831 INC_STATS_COUNTER(total_map_requests);
1834 INC_STATS_COUNTER(cross_page);
1837 align_mask = (1UL << get_order(size)) - 1;
1840 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1842 if (unlikely(address == DMA_ERROR_CODE)) {
1844 * setting next_address here will let the address
1845 * allocator only scan the new allocated range in the
1846 * first run. This is a small optimization.
1848 dma_dom->next_address = dma_dom->aperture_size;
1850 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
1854 * aperture was successfully enlarged by 128 MB, try
1861 for (i = 0; i < pages; ++i) {
1862 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
1863 if (ret == DMA_ERROR_CODE)
1871 ADD_STATS_COUNTER(alloced_io_mem, size);
1873 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1874 iommu_flush_tlb(&dma_dom->domain);
1875 dma_dom->need_flush = false;
1876 } else if (unlikely(amd_iommu_np_cache))
1877 iommu_flush_pages(&dma_dom->domain, address, size);
1884 for (--i; i >= 0; --i) {
1886 dma_ops_domain_unmap(dma_dom, start);
1889 dma_ops_free_addresses(dma_dom, address, pages);
1891 return DMA_ERROR_CODE;
1895 * Does the reverse of the __map_single function. Must be called with
1896 * the domain lock held too
1898 static void __unmap_single(struct dma_ops_domain *dma_dom,
1899 dma_addr_t dma_addr,
1903 dma_addr_t flush_addr;
1904 dma_addr_t i, start;
1907 if ((dma_addr == DMA_ERROR_CODE) ||
1908 (dma_addr + size > dma_dom->aperture_size))
1911 flush_addr = dma_addr;
1912 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1913 dma_addr &= PAGE_MASK;
1916 for (i = 0; i < pages; ++i) {
1917 dma_ops_domain_unmap(dma_dom, start);
1921 SUB_STATS_COUNTER(alloced_io_mem, size);
1923 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1925 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1926 iommu_flush_pages(&dma_dom->domain, flush_addr, size);
1927 dma_dom->need_flush = false;
1932 * The exported map_single function for dma_ops.
1934 static dma_addr_t map_page(struct device *dev, struct page *page,
1935 unsigned long offset, size_t size,
1936 enum dma_data_direction dir,
1937 struct dma_attrs *attrs)
1939 unsigned long flags;
1940 struct protection_domain *domain;
1943 phys_addr_t paddr = page_to_phys(page) + offset;
1945 INC_STATS_COUNTER(cnt_map_single);
1947 domain = get_domain(dev);
1948 if (PTR_ERR(domain) == -EINVAL)
1949 return (dma_addr_t)paddr;
1950 else if (IS_ERR(domain))
1951 return DMA_ERROR_CODE;
1953 dma_mask = *dev->dma_mask;
1955 spin_lock_irqsave(&domain->lock, flags);
1957 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
1959 if (addr == DMA_ERROR_CODE)
1962 iommu_flush_complete(domain);
1965 spin_unlock_irqrestore(&domain->lock, flags);
1971 * The exported unmap_single function for dma_ops.
1973 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
1974 enum dma_data_direction dir, struct dma_attrs *attrs)
1976 unsigned long flags;
1977 struct protection_domain *domain;
1979 INC_STATS_COUNTER(cnt_unmap_single);
1981 domain = get_domain(dev);
1985 spin_lock_irqsave(&domain->lock, flags);
1987 __unmap_single(domain->priv, dma_addr, size, dir);
1989 iommu_flush_complete(domain);
1991 spin_unlock_irqrestore(&domain->lock, flags);
1995 * This is a special map_sg function which is used if we should map a
1996 * device which is not handled by an AMD IOMMU in the system.
1998 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1999 int nelems, int dir)
2001 struct scatterlist *s;
2004 for_each_sg(sglist, s, nelems, i) {
2005 s->dma_address = (dma_addr_t)sg_phys(s);
2006 s->dma_length = s->length;
2013 * The exported map_sg function for dma_ops (handles scatter-gather
2016 static int map_sg(struct device *dev, struct scatterlist *sglist,
2017 int nelems, enum dma_data_direction dir,
2018 struct dma_attrs *attrs)
2020 unsigned long flags;
2021 struct protection_domain *domain;
2023 struct scatterlist *s;
2025 int mapped_elems = 0;
2028 INC_STATS_COUNTER(cnt_map_sg);
2030 domain = get_domain(dev);
2031 if (PTR_ERR(domain) == -EINVAL)
2032 return map_sg_no_iommu(dev, sglist, nelems, dir);
2033 else if (IS_ERR(domain))
2036 dma_mask = *dev->dma_mask;
2038 spin_lock_irqsave(&domain->lock, flags);
2040 for_each_sg(sglist, s, nelems, i) {
2043 s->dma_address = __map_single(dev, domain->priv,
2044 paddr, s->length, dir, false,
2047 if (s->dma_address) {
2048 s->dma_length = s->length;
2054 iommu_flush_complete(domain);
2057 spin_unlock_irqrestore(&domain->lock, flags);
2059 return mapped_elems;
2061 for_each_sg(sglist, s, mapped_elems, i) {
2063 __unmap_single(domain->priv, s->dma_address,
2064 s->dma_length, dir);
2065 s->dma_address = s->dma_length = 0;
2074 * The exported map_sg function for dma_ops (handles scatter-gather
2077 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2078 int nelems, enum dma_data_direction dir,
2079 struct dma_attrs *attrs)
2081 unsigned long flags;
2082 struct protection_domain *domain;
2083 struct scatterlist *s;
2086 INC_STATS_COUNTER(cnt_unmap_sg);
2088 domain = get_domain(dev);
2092 spin_lock_irqsave(&domain->lock, flags);
2094 for_each_sg(sglist, s, nelems, i) {
2095 __unmap_single(domain->priv, s->dma_address,
2096 s->dma_length, dir);
2097 s->dma_address = s->dma_length = 0;
2100 iommu_flush_complete(domain);
2102 spin_unlock_irqrestore(&domain->lock, flags);
2106 * The exported alloc_coherent function for dma_ops.
2108 static void *alloc_coherent(struct device *dev, size_t size,
2109 dma_addr_t *dma_addr, gfp_t flag)
2111 unsigned long flags;
2113 struct protection_domain *domain;
2115 u64 dma_mask = dev->coherent_dma_mask;
2117 INC_STATS_COUNTER(cnt_alloc_coherent);
2119 domain = get_domain(dev);
2120 if (PTR_ERR(domain) == -EINVAL) {
2121 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2122 *dma_addr = __pa(virt_addr);
2124 } else if (IS_ERR(domain))
2127 dma_mask = dev->coherent_dma_mask;
2128 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2131 virt_addr = (void *)__get_free_pages(flag, get_order(size));
2135 paddr = virt_to_phys(virt_addr);
2138 dma_mask = *dev->dma_mask;
2140 spin_lock_irqsave(&domain->lock, flags);
2142 *dma_addr = __map_single(dev, domain->priv, paddr,
2143 size, DMA_BIDIRECTIONAL, true, dma_mask);
2145 if (*dma_addr == DMA_ERROR_CODE) {
2146 spin_unlock_irqrestore(&domain->lock, flags);
2150 iommu_flush_complete(domain);
2152 spin_unlock_irqrestore(&domain->lock, flags);
2158 free_pages((unsigned long)virt_addr, get_order(size));
2164 * The exported free_coherent function for dma_ops.
2166 static void free_coherent(struct device *dev, size_t size,
2167 void *virt_addr, dma_addr_t dma_addr)
2169 unsigned long flags;
2170 struct protection_domain *domain;
2172 INC_STATS_COUNTER(cnt_free_coherent);
2174 domain = get_domain(dev);
2178 spin_lock_irqsave(&domain->lock, flags);
2180 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2182 iommu_flush_complete(domain);
2184 spin_unlock_irqrestore(&domain->lock, flags);
2187 free_pages((unsigned long)virt_addr, get_order(size));
2191 * This function is called by the DMA layer to find out if we can handle a
2192 * particular device. It is part of the dma_ops.
2194 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2196 return check_device(dev);
2200 * The function for pre-allocating protection domains.
2202 * If the driver core informs the DMA layer if a driver grabs a device
2203 * we don't need to preallocate the protection domains anymore.
2204 * For now we have to.
2206 static void prealloc_protection_domains(void)
2208 struct pci_dev *dev = NULL;
2209 struct dma_ops_domain *dma_dom;
2212 for_each_pci_dev(dev) {
2214 /* Do we handle this device? */
2215 if (!check_device(&dev->dev))
2218 /* Is there already any domain for it? */
2219 if (domain_for_device(&dev->dev))
2222 devid = get_device_id(&dev->dev);
2224 dma_dom = dma_ops_domain_alloc();
2227 init_unity_mappings_for_device(dma_dom, devid);
2228 dma_dom->target_dev = devid;
2230 attach_device(&dev->dev, &dma_dom->domain);
2232 list_add_tail(&dma_dom->list, &iommu_pd_list);
2236 static struct dma_map_ops amd_iommu_dma_ops = {
2237 .alloc_coherent = alloc_coherent,
2238 .free_coherent = free_coherent,
2239 .map_page = map_page,
2240 .unmap_page = unmap_page,
2242 .unmap_sg = unmap_sg,
2243 .dma_supported = amd_iommu_dma_supported,
2247 * The function which clues the AMD IOMMU driver into dma_ops.
2250 void __init amd_iommu_init_api(void)
2252 register_iommu(&amd_iommu_ops);
2255 int __init amd_iommu_init_dma_ops(void)
2257 struct amd_iommu *iommu;
2261 * first allocate a default protection domain for every IOMMU we
2262 * found in the system. Devices not assigned to any other
2263 * protection domain will be assigned to the default one.
2265 for_each_iommu(iommu) {
2266 iommu->default_dom = dma_ops_domain_alloc();
2267 if (iommu->default_dom == NULL)
2269 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
2270 ret = iommu_init_unity_mappings(iommu);
2276 * Pre-allocate the protection domains for each device.
2278 prealloc_protection_domains();
2283 /* Make the driver finally visible to the drivers */
2284 dma_ops = &amd_iommu_dma_ops;
2286 amd_iommu_stats_init();
2292 for_each_iommu(iommu) {
2293 if (iommu->default_dom)
2294 dma_ops_domain_free(iommu->default_dom);
2300 /*****************************************************************************
2302 * The following functions belong to the exported interface of AMD IOMMU
2304 * This interface allows access to lower level functions of the IOMMU
2305 * like protection domain handling and assignement of devices to domains
2306 * which is not possible with the dma_ops interface.
2308 *****************************************************************************/
2310 static void cleanup_domain(struct protection_domain *domain)
2312 struct iommu_dev_data *dev_data, *next;
2313 unsigned long flags;
2315 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2317 list_for_each_entry_safe(dev_data, next, &domain->dev_list, list) {
2318 struct device *dev = dev_data->dev;
2320 __detach_device(dev);
2321 atomic_set(&dev_data->bind, 0);
2324 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2327 static void protection_domain_free(struct protection_domain *domain)
2332 del_domain_from_list(domain);
2335 domain_id_free(domain->id);
2340 static struct protection_domain *protection_domain_alloc(void)
2342 struct protection_domain *domain;
2344 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2348 spin_lock_init(&domain->lock);
2349 mutex_init(&domain->api_lock);
2350 domain->id = domain_id_alloc();
2353 INIT_LIST_HEAD(&domain->dev_list);
2355 add_domain_to_list(domain);
2365 static int amd_iommu_domain_init(struct iommu_domain *dom)
2367 struct protection_domain *domain;
2369 domain = protection_domain_alloc();
2373 domain->mode = PAGE_MODE_3_LEVEL;
2374 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2375 if (!domain->pt_root)
2383 protection_domain_free(domain);
2388 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
2390 struct protection_domain *domain = dom->priv;
2395 if (domain->dev_cnt > 0)
2396 cleanup_domain(domain);
2398 BUG_ON(domain->dev_cnt != 0);
2400 free_pagetable(domain);
2402 protection_domain_free(domain);
2407 static void amd_iommu_detach_device(struct iommu_domain *dom,
2410 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2411 struct amd_iommu *iommu;
2414 if (!check_device(dev))
2417 devid = get_device_id(dev);
2419 if (dev_data->domain != NULL)
2422 iommu = amd_iommu_rlookup_table[devid];
2426 iommu_flush_device(dev);
2427 iommu_completion_wait(iommu);
2430 static int amd_iommu_attach_device(struct iommu_domain *dom,
2433 struct protection_domain *domain = dom->priv;
2434 struct iommu_dev_data *dev_data;
2435 struct amd_iommu *iommu;
2439 if (!check_device(dev))
2442 dev_data = dev->archdata.iommu;
2444 devid = get_device_id(dev);
2446 iommu = amd_iommu_rlookup_table[devid];
2450 if (dev_data->domain)
2453 ret = attach_device(dev, domain);
2455 iommu_completion_wait(iommu);
2460 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2461 phys_addr_t paddr, int gfp_order, int iommu_prot)
2463 unsigned long page_size = 0x1000UL << gfp_order;
2464 struct protection_domain *domain = dom->priv;
2468 if (iommu_prot & IOMMU_READ)
2469 prot |= IOMMU_PROT_IR;
2470 if (iommu_prot & IOMMU_WRITE)
2471 prot |= IOMMU_PROT_IW;
2473 mutex_lock(&domain->api_lock);
2474 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
2475 mutex_unlock(&domain->api_lock);
2480 static int amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2483 struct protection_domain *domain = dom->priv;
2484 unsigned long page_size, unmap_size;
2486 page_size = 0x1000UL << gfp_order;
2488 mutex_lock(&domain->api_lock);
2489 unmap_size = iommu_unmap_page(domain, iova, page_size);
2490 mutex_unlock(&domain->api_lock);
2492 iommu_flush_tlb_pde(domain);
2494 return get_order(unmap_size);
2497 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2500 struct protection_domain *domain = dom->priv;
2501 unsigned long offset_mask;
2505 pte = fetch_pte(domain, iova);
2507 if (!pte || !IOMMU_PTE_PRESENT(*pte))
2510 if (PM_PTE_LEVEL(*pte) == 0)
2511 offset_mask = PAGE_SIZE - 1;
2513 offset_mask = PTE_PAGE_SIZE(*pte) - 1;
2515 __pte = *pte & PM_ADDR_MASK;
2516 paddr = (__pte & ~offset_mask) | (iova & offset_mask);
2521 static int amd_iommu_domain_has_cap(struct iommu_domain *domain,
2525 case IOMMU_CAP_CACHE_COHERENCY:
2532 static struct iommu_ops amd_iommu_ops = {
2533 .domain_init = amd_iommu_domain_init,
2534 .domain_destroy = amd_iommu_domain_destroy,
2535 .attach_dev = amd_iommu_attach_device,
2536 .detach_dev = amd_iommu_detach_device,
2537 .map = amd_iommu_map,
2538 .unmap = amd_iommu_unmap,
2539 .iova_to_phys = amd_iommu_iova_to_phys,
2540 .domain_has_cap = amd_iommu_domain_has_cap,
2543 /*****************************************************************************
2545 * The next functions do a basic initialization of IOMMU for pass through
2548 * In passthrough mode the IOMMU is initialized and enabled but not used for
2549 * DMA-API translation.
2551 *****************************************************************************/
2553 int __init amd_iommu_init_passthrough(void)
2555 struct amd_iommu *iommu;
2556 struct pci_dev *dev = NULL;
2559 /* allocate passthrough domain */
2560 pt_domain = protection_domain_alloc();
2564 pt_domain->mode |= PAGE_MODE_NONE;
2566 for_each_pci_dev(dev) {
2567 if (!check_device(&dev->dev))
2570 devid = get_device_id(&dev->dev);
2572 iommu = amd_iommu_rlookup_table[devid];
2576 attach_device(&dev->dev, pt_domain);
2579 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");