2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/gfp.h>
22 #include <linux/bitops.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/iommu-helper.h>
26 #ifdef CONFIG_IOMMU_API
27 #include <linux/iommu.h>
29 #include <asm/proto.h>
30 #include <asm/iommu.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37 #define EXIT_LOOP_COUNT 10000000
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock);
45 #ifdef CONFIG_IOMMU_API
46 static struct iommu_ops amd_iommu_ops;
50 * general struct to manage commands send to an IOMMU
56 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
57 struct unity_map_entry *e);
58 static struct dma_ops_domain *find_protection_domain(u16 devid);
61 #ifdef CONFIG_AMD_IOMMU_STATS
64 * Initialization code for statistics collection
67 static struct dentry *stats_dir;
68 static struct dentry *de_isolate;
69 static struct dentry *de_fflush;
71 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
73 if (stats_dir == NULL)
76 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
80 static void amd_iommu_stats_init(void)
82 stats_dir = debugfs_create_dir("amd-iommu", NULL);
83 if (stats_dir == NULL)
86 de_isolate = debugfs_create_bool("isolation", 0444, stats_dir,
87 (u32 *)&amd_iommu_isolate);
89 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
90 (u32 *)&amd_iommu_unmap_flush);
95 /* returns !0 if the IOMMU is caching non-present entries in its TLB */
96 static int iommu_has_npcache(struct amd_iommu *iommu)
98 return iommu->cap & (1UL << IOMMU_CAP_NPCACHE);
101 /****************************************************************************
103 * Interrupt handling functions
105 ****************************************************************************/
107 static void iommu_print_event(void *__evt)
110 int type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
111 int devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
112 int domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
113 int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
114 u64 address = (u64)(((u64)event[3]) << 32) | event[2];
116 printk(KERN_ERR "AMD IOMMU: Event logged [");
119 case EVENT_TYPE_ILL_DEV:
120 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
121 "address=0x%016llx flags=0x%04x]\n",
122 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
125 case EVENT_TYPE_IO_FAULT:
126 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
127 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
128 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
129 domid, address, flags);
131 case EVENT_TYPE_DEV_TAB_ERR:
132 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
133 "address=0x%016llx flags=0x%04x]\n",
134 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
137 case EVENT_TYPE_PAGE_TAB_ERR:
138 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
139 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
140 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
141 domid, address, flags);
143 case EVENT_TYPE_ILL_CMD:
144 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
146 case EVENT_TYPE_CMD_HARD_ERR:
147 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
148 "flags=0x%04x]\n", address, flags);
150 case EVENT_TYPE_IOTLB_INV_TO:
151 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
152 "address=0x%016llx]\n",
153 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
156 case EVENT_TYPE_INV_DEV_REQ:
157 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
158 "address=0x%016llx flags=0x%04x]\n",
159 PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
163 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
167 static void iommu_poll_events(struct amd_iommu *iommu)
172 spin_lock_irqsave(&iommu->lock, flags);
174 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
175 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
177 while (head != tail) {
178 iommu_print_event(iommu->evt_buf + head);
179 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
182 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
184 spin_unlock_irqrestore(&iommu->lock, flags);
187 irqreturn_t amd_iommu_int_handler(int irq, void *data)
189 struct amd_iommu *iommu;
191 list_for_each_entry(iommu, &amd_iommu_list, list)
192 iommu_poll_events(iommu);
197 /****************************************************************************
199 * IOMMU command queuing functions
201 ****************************************************************************/
204 * Writes the command to the IOMMUs command buffer and informs the
205 * hardware about the new command. Must be called with iommu->lock held.
207 static int __iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
212 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
213 target = iommu->cmd_buf + tail;
214 memcpy_toio(target, cmd, sizeof(*cmd));
215 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
216 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
219 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
225 * General queuing function for commands. Takes iommu->lock and calls
226 * __iommu_queue_command().
228 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
233 spin_lock_irqsave(&iommu->lock, flags);
234 ret = __iommu_queue_command(iommu, cmd);
236 iommu->need_sync = true;
237 spin_unlock_irqrestore(&iommu->lock, flags);
243 * This function waits until an IOMMU has completed a completion
246 static void __iommu_wait_for_completion(struct amd_iommu *iommu)
252 while (!ready && (i < EXIT_LOOP_COUNT)) {
254 /* wait for the bit to become one */
255 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
256 ready = status & MMIO_STATUS_COM_WAIT_INT_MASK;
259 /* set bit back to zero */
260 status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
261 writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
263 if (unlikely(i == EXIT_LOOP_COUNT))
264 panic("AMD IOMMU: Completion wait loop failed\n");
268 * This function queues a completion wait command into the command
271 static int __iommu_completion_wait(struct amd_iommu *iommu)
273 struct iommu_cmd cmd;
275 memset(&cmd, 0, sizeof(cmd));
276 cmd.data[0] = CMD_COMPL_WAIT_INT_MASK;
277 CMD_SET_TYPE(&cmd, CMD_COMPL_WAIT);
279 return __iommu_queue_command(iommu, &cmd);
283 * This function is called whenever we need to ensure that the IOMMU has
284 * completed execution of all commands we sent. It sends a
285 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
286 * us about that by writing a value to a physical address we pass with
289 static int iommu_completion_wait(struct amd_iommu *iommu)
294 spin_lock_irqsave(&iommu->lock, flags);
296 if (!iommu->need_sync)
299 ret = __iommu_completion_wait(iommu);
301 iommu->need_sync = false;
306 __iommu_wait_for_completion(iommu);
309 spin_unlock_irqrestore(&iommu->lock, flags);
315 * Command send function for invalidating a device table entry
317 static int iommu_queue_inv_dev_entry(struct amd_iommu *iommu, u16 devid)
319 struct iommu_cmd cmd;
322 BUG_ON(iommu == NULL);
324 memset(&cmd, 0, sizeof(cmd));
325 CMD_SET_TYPE(&cmd, CMD_INV_DEV_ENTRY);
328 ret = iommu_queue_command(iommu, &cmd);
333 static void __iommu_build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
334 u16 domid, int pde, int s)
336 memset(cmd, 0, sizeof(*cmd));
337 address &= PAGE_MASK;
338 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
339 cmd->data[1] |= domid;
340 cmd->data[2] = lower_32_bits(address);
341 cmd->data[3] = upper_32_bits(address);
342 if (s) /* size bit - we flush more than one 4kb page */
343 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
344 if (pde) /* PDE bit - we wan't flush everything not only the PTEs */
345 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
349 * Generic command send function for invalidaing TLB entries
351 static int iommu_queue_inv_iommu_pages(struct amd_iommu *iommu,
352 u64 address, u16 domid, int pde, int s)
354 struct iommu_cmd cmd;
357 __iommu_build_inv_iommu_pages(&cmd, address, domid, pde, s);
359 ret = iommu_queue_command(iommu, &cmd);
365 * TLB invalidation function which is called from the mapping functions.
366 * It invalidates a single PTE if the range to flush is within a single
367 * page. Otherwise it flushes the whole TLB of the IOMMU.
369 static int iommu_flush_pages(struct amd_iommu *iommu, u16 domid,
370 u64 address, size_t size)
373 unsigned pages = iommu_num_pages(address, size, PAGE_SIZE);
375 address &= PAGE_MASK;
379 * If we have to flush more than one page, flush all
380 * TLB entries for this domain
382 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
386 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, s);
391 /* Flush the whole IO/TLB for a given protection domain */
392 static void iommu_flush_tlb(struct amd_iommu *iommu, u16 domid)
394 u64 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
396 iommu_queue_inv_iommu_pages(iommu, address, domid, 0, 1);
399 #ifdef CONFIG_IOMMU_API
401 * This function is used to flush the IO/TLB for a given protection domain
402 * on every IOMMU in the system
404 static void iommu_flush_domain(u16 domid)
407 struct amd_iommu *iommu;
408 struct iommu_cmd cmd;
410 __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
413 list_for_each_entry(iommu, &amd_iommu_list, list) {
414 spin_lock_irqsave(&iommu->lock, flags);
415 __iommu_queue_command(iommu, &cmd);
416 __iommu_completion_wait(iommu);
417 __iommu_wait_for_completion(iommu);
418 spin_unlock_irqrestore(&iommu->lock, flags);
423 /****************************************************************************
425 * The functions below are used the create the page table mappings for
426 * unity mapped regions.
428 ****************************************************************************/
431 * Generic mapping functions. It maps a physical address into a DMA
432 * address space. It allocates the page table pages if necessary.
433 * In the future it can be extended to a generic mapping function
434 * supporting all features of AMD IOMMU page tables like level skipping
435 * and full 64 bit address spaces.
437 static int iommu_map_page(struct protection_domain *dom,
438 unsigned long bus_addr,
439 unsigned long phys_addr,
442 u64 __pte, *pte, *page;
444 bus_addr = PAGE_ALIGN(bus_addr);
445 phys_addr = PAGE_ALIGN(phys_addr);
447 /* only support 512GB address spaces for now */
448 if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
451 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
453 if (!IOMMU_PTE_PRESENT(*pte)) {
454 page = (u64 *)get_zeroed_page(GFP_KERNEL);
457 *pte = IOMMU_L2_PDE(virt_to_phys(page));
460 pte = IOMMU_PTE_PAGE(*pte);
461 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
463 if (!IOMMU_PTE_PRESENT(*pte)) {
464 page = (u64 *)get_zeroed_page(GFP_KERNEL);
467 *pte = IOMMU_L1_PDE(virt_to_phys(page));
470 pte = IOMMU_PTE_PAGE(*pte);
471 pte = &pte[IOMMU_PTE_L0_INDEX(bus_addr)];
473 if (IOMMU_PTE_PRESENT(*pte))
476 __pte = phys_addr | IOMMU_PTE_P;
477 if (prot & IOMMU_PROT_IR)
478 __pte |= IOMMU_PTE_IR;
479 if (prot & IOMMU_PROT_IW)
480 __pte |= IOMMU_PTE_IW;
487 #ifdef CONFIG_IOMMU_API
488 static void iommu_unmap_page(struct protection_domain *dom,
489 unsigned long bus_addr)
493 pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
495 if (!IOMMU_PTE_PRESENT(*pte))
498 pte = IOMMU_PTE_PAGE(*pte);
499 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
501 if (!IOMMU_PTE_PRESENT(*pte))
504 pte = IOMMU_PTE_PAGE(*pte);
505 pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
512 * This function checks if a specific unity mapping entry is needed for
513 * this specific IOMMU.
515 static int iommu_for_unity_map(struct amd_iommu *iommu,
516 struct unity_map_entry *entry)
520 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
521 bdf = amd_iommu_alias_table[i];
522 if (amd_iommu_rlookup_table[bdf] == iommu)
530 * Init the unity mappings for a specific IOMMU in the system
532 * Basically iterates over all unity mapping entries and applies them to
533 * the default domain DMA of that IOMMU if necessary.
535 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
537 struct unity_map_entry *entry;
540 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
541 if (!iommu_for_unity_map(iommu, entry))
543 ret = dma_ops_unity_map(iommu->default_dom, entry);
552 * This function actually applies the mapping to the page table of the
555 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
556 struct unity_map_entry *e)
561 for (addr = e->address_start; addr < e->address_end;
563 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
567 * if unity mapping is in aperture range mark the page
568 * as allocated in the aperture
570 if (addr < dma_dom->aperture_size)
571 __set_bit(addr >> PAGE_SHIFT, dma_dom->bitmap);
578 * Inits the unity mappings required for a specific device
580 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
583 struct unity_map_entry *e;
586 list_for_each_entry(e, &amd_iommu_unity_map, list) {
587 if (!(devid >= e->devid_start && devid <= e->devid_end))
589 ret = dma_ops_unity_map(dma_dom, e);
597 /****************************************************************************
599 * The next functions belong to the address allocator for the dma_ops
600 * interface functions. They work like the allocators in the other IOMMU
601 * drivers. Its basically a bitmap which marks the allocated pages in
602 * the aperture. Maybe it could be enhanced in the future to a more
603 * efficient allocator.
605 ****************************************************************************/
608 * The address allocator core function.
610 * called with domain->lock held
612 static unsigned long dma_ops_alloc_addresses(struct device *dev,
613 struct dma_ops_domain *dom,
615 unsigned long align_mask,
619 unsigned long address;
620 unsigned long boundary_size;
622 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
623 PAGE_SIZE) >> PAGE_SHIFT;
624 limit = iommu_device_max_index(dom->aperture_size >> PAGE_SHIFT, 0,
625 dma_mask >> PAGE_SHIFT);
627 if (dom->next_bit >= limit) {
629 dom->need_flush = true;
632 address = iommu_area_alloc(dom->bitmap, limit, dom->next_bit, pages,
633 0 , boundary_size, align_mask);
635 address = iommu_area_alloc(dom->bitmap, limit, 0, pages,
636 0, boundary_size, align_mask);
637 dom->need_flush = true;
640 if (likely(address != -1)) {
641 dom->next_bit = address + pages;
642 address <<= PAGE_SHIFT;
644 address = bad_dma_address;
646 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
652 * The address free function.
654 * called with domain->lock held
656 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
657 unsigned long address,
660 address >>= PAGE_SHIFT;
661 iommu_area_free(dom->bitmap, address, pages);
663 if (address >= dom->next_bit)
664 dom->need_flush = true;
667 /****************************************************************************
669 * The next functions belong to the domain allocation. A domain is
670 * allocated for every IOMMU as the default domain. If device isolation
671 * is enabled, every device get its own domain. The most important thing
672 * about domains is the page table mapping the DMA address space they
675 ****************************************************************************/
677 static u16 domain_id_alloc(void)
682 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
683 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
685 if (id > 0 && id < MAX_DOMAIN_ID)
686 __set_bit(id, amd_iommu_pd_alloc_bitmap);
689 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
694 #ifdef CONFIG_IOMMU_API
695 static void domain_id_free(int id)
699 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
700 if (id > 0 && id < MAX_DOMAIN_ID)
701 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
702 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
707 * Used to reserve address ranges in the aperture (e.g. for exclusion
710 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
711 unsigned long start_page,
714 unsigned int last_page = dom->aperture_size >> PAGE_SHIFT;
716 if (start_page + pages > last_page)
717 pages = last_page - start_page;
719 iommu_area_reserve(dom->bitmap, start_page, pages);
722 static void free_pagetable(struct protection_domain *domain)
727 p1 = domain->pt_root;
732 for (i = 0; i < 512; ++i) {
733 if (!IOMMU_PTE_PRESENT(p1[i]))
736 p2 = IOMMU_PTE_PAGE(p1[i]);
737 for (j = 0; j < 512; ++j) {
738 if (!IOMMU_PTE_PRESENT(p2[j]))
740 p3 = IOMMU_PTE_PAGE(p2[j]);
741 free_page((unsigned long)p3);
744 free_page((unsigned long)p2);
747 free_page((unsigned long)p1);
749 domain->pt_root = NULL;
753 * Free a domain, only used if something went wrong in the
754 * allocation path and we need to free an already allocated page table
756 static void dma_ops_domain_free(struct dma_ops_domain *dom)
761 free_pagetable(&dom->domain);
763 kfree(dom->pte_pages);
771 * Allocates a new protection domain usable for the dma_ops functions.
772 * It also intializes the page table and the address allocator data
773 * structures required for the dma_ops interface
775 static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu,
778 struct dma_ops_domain *dma_dom;
779 unsigned i, num_pte_pages;
784 * Currently the DMA aperture must be between 32 MB and 1GB in size
786 if ((order < 25) || (order > 30))
789 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
793 spin_lock_init(&dma_dom->domain.lock);
795 dma_dom->domain.id = domain_id_alloc();
796 if (dma_dom->domain.id == 0)
798 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
799 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
800 dma_dom->domain.flags = PD_DMA_OPS_MASK;
801 dma_dom->domain.priv = dma_dom;
802 if (!dma_dom->domain.pt_root)
804 dma_dom->aperture_size = (1ULL << order);
805 dma_dom->bitmap = kzalloc(dma_dom->aperture_size / (PAGE_SIZE * 8),
807 if (!dma_dom->bitmap)
810 * mark the first page as allocated so we never return 0 as
811 * a valid dma-address. So we can use 0 as error value
813 dma_dom->bitmap[0] = 1;
814 dma_dom->next_bit = 0;
816 dma_dom->need_flush = false;
817 dma_dom->target_dev = 0xffff;
819 /* Intialize the exclusion range if necessary */
820 if (iommu->exclusion_start &&
821 iommu->exclusion_start < dma_dom->aperture_size) {
822 unsigned long startpage = iommu->exclusion_start >> PAGE_SHIFT;
823 int pages = iommu_num_pages(iommu->exclusion_start,
824 iommu->exclusion_length,
826 dma_ops_reserve_addresses(dma_dom, startpage, pages);
830 * At the last step, build the page tables so we don't need to
831 * allocate page table pages in the dma_ops mapping/unmapping
834 num_pte_pages = dma_dom->aperture_size / (PAGE_SIZE * 512);
835 dma_dom->pte_pages = kzalloc(num_pte_pages * sizeof(void *),
837 if (!dma_dom->pte_pages)
840 l2_pde = (u64 *)get_zeroed_page(GFP_KERNEL);
844 dma_dom->domain.pt_root[0] = IOMMU_L2_PDE(virt_to_phys(l2_pde));
846 for (i = 0; i < num_pte_pages; ++i) {
847 dma_dom->pte_pages[i] = (u64 *)get_zeroed_page(GFP_KERNEL);
848 if (!dma_dom->pte_pages[i])
850 address = virt_to_phys(dma_dom->pte_pages[i]);
851 l2_pde[i] = IOMMU_L1_PDE(address);
857 dma_ops_domain_free(dma_dom);
863 * little helper function to check whether a given protection domain is a
866 static bool dma_ops_domain(struct protection_domain *domain)
868 return domain->flags & PD_DMA_OPS_MASK;
872 * Find out the protection domain structure for a given PCI device. This
873 * will give us the pointer to the page table root for example.
875 static struct protection_domain *domain_for_device(u16 devid)
877 struct protection_domain *dom;
880 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
881 dom = amd_iommu_pd_table[devid];
882 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
888 * If a device is not yet associated with a domain, this function does
889 * assigns it visible for the hardware
891 static void attach_device(struct amd_iommu *iommu,
892 struct protection_domain *domain,
896 u64 pte_root = virt_to_phys(domain->pt_root);
898 domain->dev_cnt += 1;
900 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
901 << DEV_ENTRY_MODE_SHIFT;
902 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
904 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
905 amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
906 amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
907 amd_iommu_dev_table[devid].data[2] = domain->id;
909 amd_iommu_pd_table[devid] = domain;
910 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
912 iommu_queue_inv_dev_entry(iommu, devid);
916 * Removes a device from a protection domain (unlocked)
918 static void __detach_device(struct protection_domain *domain, u16 devid)
922 spin_lock(&domain->lock);
924 /* remove domain from the lookup table */
925 amd_iommu_pd_table[devid] = NULL;
927 /* remove entry from the device table seen by the hardware */
928 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
929 amd_iommu_dev_table[devid].data[1] = 0;
930 amd_iommu_dev_table[devid].data[2] = 0;
932 /* decrease reference counter */
933 domain->dev_cnt -= 1;
936 spin_unlock(&domain->lock);
940 * Removes a device from a protection domain (with devtable_lock held)
942 static void detach_device(struct protection_domain *domain, u16 devid)
946 /* lock device table */
947 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
948 __detach_device(domain, devid);
949 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
952 static int device_change_notifier(struct notifier_block *nb,
953 unsigned long action, void *data)
955 struct device *dev = data;
956 struct pci_dev *pdev = to_pci_dev(dev);
957 u16 devid = calc_devid(pdev->bus->number, pdev->devfn);
958 struct protection_domain *domain;
959 struct dma_ops_domain *dma_domain;
960 struct amd_iommu *iommu;
961 int order = amd_iommu_aperture_order;
964 if (devid > amd_iommu_last_bdf)
967 devid = amd_iommu_alias_table[devid];
969 iommu = amd_iommu_rlookup_table[devid];
973 domain = domain_for_device(devid);
975 if (domain && !dma_ops_domain(domain))
976 WARN_ONCE(1, "AMD IOMMU WARNING: device %s already bound "
977 "to a non-dma-ops domain\n", dev_name(dev));
980 case BUS_NOTIFY_BOUND_DRIVER:
983 dma_domain = find_protection_domain(devid);
985 dma_domain = iommu->default_dom;
986 attach_device(iommu, &dma_domain->domain, devid);
987 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
988 "device %s\n", dma_domain->domain.id, dev_name(dev));
990 case BUS_NOTIFY_UNBIND_DRIVER:
993 detach_device(domain, devid);
995 case BUS_NOTIFY_ADD_DEVICE:
996 /* allocate a protection domain if a device is added */
997 dma_domain = find_protection_domain(devid);
1000 dma_domain = dma_ops_domain_alloc(iommu, order);
1003 dma_domain->target_dev = devid;
1005 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1006 list_add_tail(&dma_domain->list, &iommu_pd_list);
1007 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1014 iommu_queue_inv_dev_entry(iommu, devid);
1015 iommu_completion_wait(iommu);
1021 struct notifier_block device_nb = {
1022 .notifier_call = device_change_notifier,
1025 /*****************************************************************************
1027 * The next functions belong to the dma_ops mapping/unmapping code.
1029 *****************************************************************************/
1032 * This function checks if the driver got a valid device from the caller to
1033 * avoid dereferencing invalid pointers.
1035 static bool check_device(struct device *dev)
1037 if (!dev || !dev->dma_mask)
1044 * In this function the list of preallocated protection domains is traversed to
1045 * find the domain for a specific device
1047 static struct dma_ops_domain *find_protection_domain(u16 devid)
1049 struct dma_ops_domain *entry, *ret = NULL;
1050 unsigned long flags;
1052 if (list_empty(&iommu_pd_list))
1055 spin_lock_irqsave(&iommu_pd_list_lock, flags);
1057 list_for_each_entry(entry, &iommu_pd_list, list) {
1058 if (entry->target_dev == devid) {
1064 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
1070 * In the dma_ops path we only have the struct device. This function
1071 * finds the corresponding IOMMU, the protection domain and the
1072 * requestor id for a given device.
1073 * If the device is not yet associated with a domain this is also done
1076 static int get_device_resources(struct device *dev,
1077 struct amd_iommu **iommu,
1078 struct protection_domain **domain,
1081 struct dma_ops_domain *dma_dom;
1082 struct pci_dev *pcidev;
1089 if (dev->bus != &pci_bus_type)
1092 pcidev = to_pci_dev(dev);
1093 _bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1095 /* device not translated by any IOMMU in the system? */
1096 if (_bdf > amd_iommu_last_bdf)
1099 *bdf = amd_iommu_alias_table[_bdf];
1101 *iommu = amd_iommu_rlookup_table[*bdf];
1104 *domain = domain_for_device(*bdf);
1105 if (*domain == NULL) {
1106 dma_dom = find_protection_domain(*bdf);
1108 dma_dom = (*iommu)->default_dom;
1109 *domain = &dma_dom->domain;
1110 attach_device(*iommu, *domain, *bdf);
1111 printk(KERN_INFO "AMD IOMMU: Using protection domain %d for "
1112 "device %s\n", (*domain)->id, dev_name(dev));
1115 if (domain_for_device(_bdf) == NULL)
1116 attach_device(*iommu, *domain, _bdf);
1122 * This is the generic map function. It maps one 4kb page at paddr to
1123 * the given address in the DMA address space for the domain.
1125 static dma_addr_t dma_ops_domain_map(struct amd_iommu *iommu,
1126 struct dma_ops_domain *dom,
1127 unsigned long address,
1133 WARN_ON(address > dom->aperture_size);
1137 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1138 pte += IOMMU_PTE_L0_INDEX(address);
1140 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
1142 if (direction == DMA_TO_DEVICE)
1143 __pte |= IOMMU_PTE_IR;
1144 else if (direction == DMA_FROM_DEVICE)
1145 __pte |= IOMMU_PTE_IW;
1146 else if (direction == DMA_BIDIRECTIONAL)
1147 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
1153 return (dma_addr_t)address;
1157 * The generic unmapping function for on page in the DMA address space.
1159 static void dma_ops_domain_unmap(struct amd_iommu *iommu,
1160 struct dma_ops_domain *dom,
1161 unsigned long address)
1165 if (address >= dom->aperture_size)
1168 WARN_ON(address & ~PAGE_MASK || address >= dom->aperture_size);
1170 pte = dom->pte_pages[IOMMU_PTE_L1_INDEX(address)];
1171 pte += IOMMU_PTE_L0_INDEX(address);
1179 * This function contains common code for mapping of a physically
1180 * contiguous memory region into DMA address space. It is used by all
1181 * mapping functions provided with this IOMMU driver.
1182 * Must be called with the domain lock held.
1184 static dma_addr_t __map_single(struct device *dev,
1185 struct amd_iommu *iommu,
1186 struct dma_ops_domain *dma_dom,
1193 dma_addr_t offset = paddr & ~PAGE_MASK;
1194 dma_addr_t address, start;
1196 unsigned long align_mask = 0;
1199 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
1203 align_mask = (1UL << get_order(size)) - 1;
1205 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
1207 if (unlikely(address == bad_dma_address))
1211 for (i = 0; i < pages; ++i) {
1212 dma_ops_domain_map(iommu, dma_dom, start, paddr, dir);
1218 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
1219 iommu_flush_tlb(iommu, dma_dom->domain.id);
1220 dma_dom->need_flush = false;
1221 } else if (unlikely(iommu_has_npcache(iommu)))
1222 iommu_flush_pages(iommu, dma_dom->domain.id, address, size);
1229 * Does the reverse of the __map_single function. Must be called with
1230 * the domain lock held too
1232 static void __unmap_single(struct amd_iommu *iommu,
1233 struct dma_ops_domain *dma_dom,
1234 dma_addr_t dma_addr,
1238 dma_addr_t i, start;
1241 if ((dma_addr == bad_dma_address) ||
1242 (dma_addr + size > dma_dom->aperture_size))
1245 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
1246 dma_addr &= PAGE_MASK;
1249 for (i = 0; i < pages; ++i) {
1250 dma_ops_domain_unmap(iommu, dma_dom, start);
1254 dma_ops_free_addresses(dma_dom, dma_addr, pages);
1256 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
1257 iommu_flush_pages(iommu, dma_dom->domain.id, dma_addr, size);
1258 dma_dom->need_flush = false;
1263 * The exported map_single function for dma_ops.
1265 static dma_addr_t map_single(struct device *dev, phys_addr_t paddr,
1266 size_t size, int dir)
1268 unsigned long flags;
1269 struct amd_iommu *iommu;
1270 struct protection_domain *domain;
1275 if (!check_device(dev))
1276 return bad_dma_address;
1278 dma_mask = *dev->dma_mask;
1280 get_device_resources(dev, &iommu, &domain, &devid);
1282 if (iommu == NULL || domain == NULL)
1283 /* device not handled by any AMD IOMMU */
1284 return (dma_addr_t)paddr;
1286 if (!dma_ops_domain(domain))
1287 return bad_dma_address;
1289 spin_lock_irqsave(&domain->lock, flags);
1290 addr = __map_single(dev, iommu, domain->priv, paddr, size, dir, false,
1292 if (addr == bad_dma_address)
1295 iommu_completion_wait(iommu);
1298 spin_unlock_irqrestore(&domain->lock, flags);
1304 * The exported unmap_single function for dma_ops.
1306 static void unmap_single(struct device *dev, dma_addr_t dma_addr,
1307 size_t size, int dir)
1309 unsigned long flags;
1310 struct amd_iommu *iommu;
1311 struct protection_domain *domain;
1314 if (!check_device(dev) ||
1315 !get_device_resources(dev, &iommu, &domain, &devid))
1316 /* device not handled by any AMD IOMMU */
1319 if (!dma_ops_domain(domain))
1322 spin_lock_irqsave(&domain->lock, flags);
1324 __unmap_single(iommu, domain->priv, dma_addr, size, dir);
1326 iommu_completion_wait(iommu);
1328 spin_unlock_irqrestore(&domain->lock, flags);
1332 * This is a special map_sg function which is used if we should map a
1333 * device which is not handled by an AMD IOMMU in the system.
1335 static int map_sg_no_iommu(struct device *dev, struct scatterlist *sglist,
1336 int nelems, int dir)
1338 struct scatterlist *s;
1341 for_each_sg(sglist, s, nelems, i) {
1342 s->dma_address = (dma_addr_t)sg_phys(s);
1343 s->dma_length = s->length;
1350 * The exported map_sg function for dma_ops (handles scatter-gather
1353 static int map_sg(struct device *dev, struct scatterlist *sglist,
1354 int nelems, int dir)
1356 unsigned long flags;
1357 struct amd_iommu *iommu;
1358 struct protection_domain *domain;
1361 struct scatterlist *s;
1363 int mapped_elems = 0;
1366 if (!check_device(dev))
1369 dma_mask = *dev->dma_mask;
1371 get_device_resources(dev, &iommu, &domain, &devid);
1373 if (!iommu || !domain)
1374 return map_sg_no_iommu(dev, sglist, nelems, dir);
1376 if (!dma_ops_domain(domain))
1379 spin_lock_irqsave(&domain->lock, flags);
1381 for_each_sg(sglist, s, nelems, i) {
1384 s->dma_address = __map_single(dev, iommu, domain->priv,
1385 paddr, s->length, dir, false,
1388 if (s->dma_address) {
1389 s->dma_length = s->length;
1395 iommu_completion_wait(iommu);
1398 spin_unlock_irqrestore(&domain->lock, flags);
1400 return mapped_elems;
1402 for_each_sg(sglist, s, mapped_elems, i) {
1404 __unmap_single(iommu, domain->priv, s->dma_address,
1405 s->dma_length, dir);
1406 s->dma_address = s->dma_length = 0;
1415 * The exported map_sg function for dma_ops (handles scatter-gather
1418 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
1419 int nelems, int dir)
1421 unsigned long flags;
1422 struct amd_iommu *iommu;
1423 struct protection_domain *domain;
1424 struct scatterlist *s;
1428 if (!check_device(dev) ||
1429 !get_device_resources(dev, &iommu, &domain, &devid))
1432 if (!dma_ops_domain(domain))
1435 spin_lock_irqsave(&domain->lock, flags);
1437 for_each_sg(sglist, s, nelems, i) {
1438 __unmap_single(iommu, domain->priv, s->dma_address,
1439 s->dma_length, dir);
1440 s->dma_address = s->dma_length = 0;
1443 iommu_completion_wait(iommu);
1445 spin_unlock_irqrestore(&domain->lock, flags);
1449 * The exported alloc_coherent function for dma_ops.
1451 static void *alloc_coherent(struct device *dev, size_t size,
1452 dma_addr_t *dma_addr, gfp_t flag)
1454 unsigned long flags;
1456 struct amd_iommu *iommu;
1457 struct protection_domain *domain;
1460 u64 dma_mask = dev->coherent_dma_mask;
1462 if (!check_device(dev))
1465 if (!get_device_resources(dev, &iommu, &domain, &devid))
1466 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
1469 virt_addr = (void *)__get_free_pages(flag, get_order(size));
1473 paddr = virt_to_phys(virt_addr);
1475 if (!iommu || !domain) {
1476 *dma_addr = (dma_addr_t)paddr;
1480 if (!dma_ops_domain(domain))
1484 dma_mask = *dev->dma_mask;
1486 spin_lock_irqsave(&domain->lock, flags);
1488 *dma_addr = __map_single(dev, iommu, domain->priv, paddr,
1489 size, DMA_BIDIRECTIONAL, true, dma_mask);
1491 if (*dma_addr == bad_dma_address)
1494 iommu_completion_wait(iommu);
1496 spin_unlock_irqrestore(&domain->lock, flags);
1502 free_pages((unsigned long)virt_addr, get_order(size));
1508 * The exported free_coherent function for dma_ops.
1510 static void free_coherent(struct device *dev, size_t size,
1511 void *virt_addr, dma_addr_t dma_addr)
1513 unsigned long flags;
1514 struct amd_iommu *iommu;
1515 struct protection_domain *domain;
1518 if (!check_device(dev))
1521 get_device_resources(dev, &iommu, &domain, &devid);
1523 if (!iommu || !domain)
1526 if (!dma_ops_domain(domain))
1529 spin_lock_irqsave(&domain->lock, flags);
1531 __unmap_single(iommu, domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
1533 iommu_completion_wait(iommu);
1535 spin_unlock_irqrestore(&domain->lock, flags);
1538 free_pages((unsigned long)virt_addr, get_order(size));
1542 * This function is called by the DMA layer to find out if we can handle a
1543 * particular device. It is part of the dma_ops.
1545 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
1548 struct pci_dev *pcidev;
1550 /* No device or no PCI device */
1551 if (!dev || dev->bus != &pci_bus_type)
1554 pcidev = to_pci_dev(dev);
1556 bdf = calc_devid(pcidev->bus->number, pcidev->devfn);
1558 /* Out of our scope? */
1559 if (bdf > amd_iommu_last_bdf)
1566 * The function for pre-allocating protection domains.
1568 * If the driver core informs the DMA layer if a driver grabs a device
1569 * we don't need to preallocate the protection domains anymore.
1570 * For now we have to.
1572 void prealloc_protection_domains(void)
1574 struct pci_dev *dev = NULL;
1575 struct dma_ops_domain *dma_dom;
1576 struct amd_iommu *iommu;
1577 int order = amd_iommu_aperture_order;
1580 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
1581 devid = calc_devid(dev->bus->number, dev->devfn);
1582 if (devid > amd_iommu_last_bdf)
1584 devid = amd_iommu_alias_table[devid];
1585 if (domain_for_device(devid))
1587 iommu = amd_iommu_rlookup_table[devid];
1590 dma_dom = dma_ops_domain_alloc(iommu, order);
1593 init_unity_mappings_for_device(dma_dom, devid);
1594 dma_dom->target_dev = devid;
1596 list_add_tail(&dma_dom->list, &iommu_pd_list);
1600 static struct dma_mapping_ops amd_iommu_dma_ops = {
1601 .alloc_coherent = alloc_coherent,
1602 .free_coherent = free_coherent,
1603 .map_single = map_single,
1604 .unmap_single = unmap_single,
1606 .unmap_sg = unmap_sg,
1607 .dma_supported = amd_iommu_dma_supported,
1611 * The function which clues the AMD IOMMU driver into dma_ops.
1613 int __init amd_iommu_init_dma_ops(void)
1615 struct amd_iommu *iommu;
1616 int order = amd_iommu_aperture_order;
1620 * first allocate a default protection domain for every IOMMU we
1621 * found in the system. Devices not assigned to any other
1622 * protection domain will be assigned to the default one.
1624 list_for_each_entry(iommu, &amd_iommu_list, list) {
1625 iommu->default_dom = dma_ops_domain_alloc(iommu, order);
1626 if (iommu->default_dom == NULL)
1628 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
1629 ret = iommu_init_unity_mappings(iommu);
1635 * If device isolation is enabled, pre-allocate the protection
1636 * domains for each device.
1638 if (amd_iommu_isolate)
1639 prealloc_protection_domains();
1643 bad_dma_address = 0;
1644 #ifdef CONFIG_GART_IOMMU
1645 gart_iommu_aperture_disabled = 1;
1646 gart_iommu_aperture = 0;
1649 /* Make the driver finally visible to the drivers */
1650 dma_ops = &amd_iommu_dma_ops;
1652 #ifdef CONFIG_IOMMU_API
1653 register_iommu(&amd_iommu_ops);
1656 bus_register_notifier(&pci_bus_type, &device_nb);
1658 amd_iommu_stats_init();
1664 list_for_each_entry(iommu, &amd_iommu_list, list) {
1665 if (iommu->default_dom)
1666 dma_ops_domain_free(iommu->default_dom);
1672 /*****************************************************************************
1674 * The following functions belong to the exported interface of AMD IOMMU
1676 * This interface allows access to lower level functions of the IOMMU
1677 * like protection domain handling and assignement of devices to domains
1678 * which is not possible with the dma_ops interface.
1680 *****************************************************************************/
1682 #ifdef CONFIG_IOMMU_API
1684 static void cleanup_domain(struct protection_domain *domain)
1686 unsigned long flags;
1689 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1691 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1692 if (amd_iommu_pd_table[devid] == domain)
1693 __detach_device(domain, devid);
1695 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1698 static int amd_iommu_domain_init(struct iommu_domain *dom)
1700 struct protection_domain *domain;
1702 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1706 spin_lock_init(&domain->lock);
1707 domain->mode = PAGE_MODE_3_LEVEL;
1708 domain->id = domain_id_alloc();
1711 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1712 if (!domain->pt_root)
1725 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
1727 struct protection_domain *domain = dom->priv;
1732 if (domain->dev_cnt > 0)
1733 cleanup_domain(domain);
1735 BUG_ON(domain->dev_cnt != 0);
1737 free_pagetable(domain);
1739 domain_id_free(domain->id);
1746 static void amd_iommu_detach_device(struct iommu_domain *dom,
1749 struct protection_domain *domain = dom->priv;
1750 struct amd_iommu *iommu;
1751 struct pci_dev *pdev;
1754 if (dev->bus != &pci_bus_type)
1757 pdev = to_pci_dev(dev);
1759 devid = calc_devid(pdev->bus->number, pdev->devfn);
1762 detach_device(domain, devid);
1764 iommu = amd_iommu_rlookup_table[devid];
1768 iommu_queue_inv_dev_entry(iommu, devid);
1769 iommu_completion_wait(iommu);
1772 static int amd_iommu_attach_device(struct iommu_domain *dom,
1775 struct protection_domain *domain = dom->priv;
1776 struct protection_domain *old_domain;
1777 struct amd_iommu *iommu;
1778 struct pci_dev *pdev;
1781 if (dev->bus != &pci_bus_type)
1784 pdev = to_pci_dev(dev);
1786 devid = calc_devid(pdev->bus->number, pdev->devfn);
1788 if (devid >= amd_iommu_last_bdf ||
1789 devid != amd_iommu_alias_table[devid])
1792 iommu = amd_iommu_rlookup_table[devid];
1796 old_domain = domain_for_device(devid);
1800 attach_device(iommu, domain, devid);
1802 iommu_completion_wait(iommu);
1807 static int amd_iommu_map_range(struct iommu_domain *dom,
1808 unsigned long iova, phys_addr_t paddr,
1809 size_t size, int iommu_prot)
1811 struct protection_domain *domain = dom->priv;
1812 unsigned long i, npages = iommu_num_pages(paddr, size, PAGE_SIZE);
1816 if (iommu_prot & IOMMU_READ)
1817 prot |= IOMMU_PROT_IR;
1818 if (iommu_prot & IOMMU_WRITE)
1819 prot |= IOMMU_PROT_IW;
1824 for (i = 0; i < npages; ++i) {
1825 ret = iommu_map_page(domain, iova, paddr, prot);
1836 static void amd_iommu_unmap_range(struct iommu_domain *dom,
1837 unsigned long iova, size_t size)
1840 struct protection_domain *domain = dom->priv;
1841 unsigned long i, npages = iommu_num_pages(iova, size, PAGE_SIZE);
1845 for (i = 0; i < npages; ++i) {
1846 iommu_unmap_page(domain, iova);
1850 iommu_flush_domain(domain->id);
1853 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
1856 struct protection_domain *domain = dom->priv;
1857 unsigned long offset = iova & ~PAGE_MASK;
1861 pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
1863 if (!IOMMU_PTE_PRESENT(*pte))
1866 pte = IOMMU_PTE_PAGE(*pte);
1867 pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
1869 if (!IOMMU_PTE_PRESENT(*pte))
1872 pte = IOMMU_PTE_PAGE(*pte);
1873 pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
1875 if (!IOMMU_PTE_PRESENT(*pte))
1878 paddr = *pte & IOMMU_PAGE_MASK;
1884 static struct iommu_ops amd_iommu_ops = {
1885 .domain_init = amd_iommu_domain_init,
1886 .domain_destroy = amd_iommu_domain_destroy,
1887 .attach_dev = amd_iommu_attach_device,
1888 .detach_dev = amd_iommu_detach_device,
1889 .map = amd_iommu_map_range,
1890 .unmap = amd_iommu_unmap_range,
1891 .iova_to_phys = amd_iommu_iova_to_phys,