arch/x86/include/asm/x2apic.h

   1 /*
   2  * Common bits for X2APIC cluster/physical modes.
   3  */
   4
   5 #ifndef _ASM_X86_X2APIC_H
   6 #define _ASM_X86_X2APIC_H
   7
   8 #include <asm/apic.h>
   9 #include <asm/ipi.h>
  10 #include <linux/cpumask.h>
  11
  12 /*
  13  * Need to use more than cpu 0, because we need more vectors
  14  * when MSI-X are used.
  15  */
  16 static const struct cpumask *x2apic_target_cpus(void)
  17 {
  18         return cpu_online_mask;
  19 }
  20
  21 static int x2apic_apic_id_valid(int apicid)
  22 {
  23         return 1;
  24 }
  25
  26 static int x2apic_apic_id_registered(void)
  27 {
  28         return 1;
  29 }
  30
  31 /*
  32  * For now each logical cpu is in its own vector allocation domain.
  33  */
  34 static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
  35 {
  36         cpumask_clear(retmask);
  37         cpumask_set_cpu(cpu, retmask);
  38 }
  39
  40 static void
  41 __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest)
  42 {
  43         unsigned long cfg = __prepare_ICR(0, vector, dest);
  44         native_x2apic_icr_write(cfg, apicid);
  45 }
  46
  47 static unsigned int x2apic_get_apic_id(unsigned long id)
  48 {
  49         return id;
  50 }
  51
  52 static unsigned long x2apic_set_apic_id(unsigned int id)
  53 {
  54         return id;
  55 }
  56
  57 static int x2apic_phys_pkg_id(int initial_apicid, int index_msb)
  58 {
  59         return initial_apicid >> index_msb;
  60 }
  61
  62 static void x2apic_send_IPI_self(int vector)
  63 {
  64         apic_write(APIC_SELF_IPI, vector);
  65 }
  66
  67 #endif /* _ASM_X86_X2APIC_H */