arch/x86/include/asm/perf_event.h

   1 #ifndef _ASM_X86_PERF_EVENT_H
   2 #define _ASM_X86_PERF_EVENT_H
   3
   4 /*
   5  * Performance event hw details:
   6  */
   7
   8 #define X86_PMC_MAX_GENERIC                                     8
   9 #define X86_PMC_MAX_FIXED                                       3
  10
  11 #define X86_PMC_IDX_GENERIC                                     0
  12 #define X86_PMC_IDX_FIXED                                      32
  13 #define X86_PMC_IDX_MAX                                        64
  14
  15 #define MSR_ARCH_PERFMON_PERFCTR0                             0xc1
  16 #define MSR_ARCH_PERFMON_PERFCTR1                             0xc2
  17
  18 #define MSR_ARCH_PERFMON_EVENTSEL0                           0x186
  19 #define MSR_ARCH_PERFMON_EVENTSEL1                           0x187
  20
  21 #define ARCH_PERFMON_EVENTSEL0_ENABLE                     (1 << 22)
  22 #define ARCH_PERFMON_EVENTSEL_ANY                         (1 << 21)
  23 #define ARCH_PERFMON_EVENTSEL_INT                         (1 << 20)
  24 #define ARCH_PERFMON_EVENTSEL_OS                          (1 << 17)
  25 #define ARCH_PERFMON_EVENTSEL_USR                         (1 << 16)
  26
  27 /*
  28  * Includes eventsel and unit mask as well:
  29  */
  30 #define ARCH_PERFMON_EVENT_MASK                             0xffff
  31
  32 /*
  33  * filter mask to validate fixed counter events.
  34  * the following filters disqualify for fixed counters:
  35  *  - inv
  36  *  - edge
  37  *  - cnt-mask
  38  *  The other filters are supported by fixed counters.
  39  *  The any-thread option is supported starting with v3.
  40  */
  41 #define ARCH_PERFMON_EVENT_FILTER_MASK                  0xff840000
  42
  43 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL                 0x3c
  44 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK         (0x00 << 8)
  45 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX                  0
  46 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
  47                 (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
  48
  49 #define ARCH_PERFMON_BRANCH_MISSES_RETIRED                       6
  50
  51 /*
  52  * Intel "Architectural Performance Monitoring" CPUID
  53  * detection/enumeration details:
  54  */
  55 union cpuid10_eax {
  56         struct {
  57                 unsigned int version_id:8;
  58                 unsigned int num_events:8;
  59                 unsigned int bit_width:8;
  60                 unsigned int mask_length:8;
  61         } split;
  62         unsigned int full;
  63 };
  64
  65 union cpuid10_edx {
  66         struct {
  67                 unsigned int num_events_fixed:4;
  68                 unsigned int reserved:28;
  69         } split;
  70         unsigned int full;
  71 };
  72
  73
  74 /*
  75  * Fixed-purpose performance events:
  76  */
  77
  78 /*
  79  * All 3 fixed-mode PMCs are configured via this single MSR:
  80  */
  81 #define MSR_ARCH_PERFMON_FIXED_CTR_CTRL                 0x38d
  82
  83 /*
  84  * The counts are available in three separate MSRs:
  85  */
  86
  87 /* Instr_Retired.Any: */
  88 #define MSR_ARCH_PERFMON_FIXED_CTR0                     0x309
  89 #define X86_PMC_IDX_FIXED_INSTRUCTIONS                  (X86_PMC_IDX_FIXED + 0)
  90
  91 /* CPU_CLK_Unhalted.Core: */
  92 #define MSR_ARCH_PERFMON_FIXED_CTR1                     0x30a
  93 #define X86_PMC_IDX_FIXED_CPU_CYCLES                    (X86_PMC_IDX_FIXED + 1)
  94
  95 /* CPU_CLK_Unhalted.Ref: */
  96 #define MSR_ARCH_PERFMON_FIXED_CTR2                     0x30b
  97 #define X86_PMC_IDX_FIXED_BUS_CYCLES                    (X86_PMC_IDX_FIXED + 2)
  98
  99 /*
 100  * We model BTS tracing as another fixed-mode PMC.
 101  *
 102  * We choose a value in the middle of the fixed event range, since lower
 103  * values are used by actual fixed events and higher values are used
 104  * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
 105  */
 106 #define X86_PMC_IDX_FIXED_BTS                           (X86_PMC_IDX_FIXED + 16)
 107
 108
 109 #ifdef CONFIG_PERF_EVENTS
 110 extern void init_hw_perf_events(void);
 111 extern void perf_events_lapic_init(void);
 112
 113 #define PERF_EVENT_INDEX_OFFSET                 0
 114
 115 #else
 116 static inline void init_hw_perf_events(void)            { }
 117 static inline void perf_events_lapic_init(void) { }
 118 #endif
 119
 120 #endif /* _ASM_X86_PERF_EVENT_H */