2 * Low-Level PCI Access for i386 machines.
4 * (c) 1999 Martin Mares <mj@ucw.cz>
10 #define DBG(x...) printk(x)
15 #define PCI_PROBE_BIOS 0x0001
16 #define PCI_PROBE_CONF1 0x0002
17 #define PCI_PROBE_CONF2 0x0004
18 #define PCI_PROBE_MMCONF 0x0008
19 #define PCI_PROBE_MASK 0x000f
20 #define PCI_PROBE_NOEARLY 0x0010
22 #define PCI_NO_CHECKS 0x0400
23 #define PCI_USE_PIRQ_MASK 0x0800
24 #define PCI_ASSIGN_ROMS 0x1000
25 #define PCI_BIOS_IRQ_SCAN 0x2000
26 #define PCI_ASSIGN_ALL_BUSSES 0x4000
27 #define PCI_CAN_SKIP_ISA_ALIGN 0x8000
28 #define PCI_USE__CRS 0x10000
29 #define PCI_CHECK_ENABLE_AMD_MMCONF 0x20000
30 #define PCI_HAS_IO_ECS 0x40000
31 #define PCI_NOASSIGN_ROMS 0x80000
32 #define PCI_ROOT_NO_CRS 0x100000
33 #define PCI_NOASSIGN_BARS 0x200000
35 extern unsigned int pci_probe;
36 extern unsigned long pirq_table_addr;
38 enum pci_bf_sort_state {
47 extern unsigned int pcibios_max_latency;
49 void pcibios_resource_survey(void);
53 extern int pcibios_last_bus;
54 extern struct pci_bus *pci_root_bus;
55 extern struct pci_ops pci_root_ops;
57 void pcibios_scan_specific_bus(int busn);
62 u8 bus, devfn; /* Bus, device and function */
64 u8 link; /* IRQ line ID, chipset dependent,
66 u16 bitmap; /* Available IRQs */
67 } __attribute__((packed)) irq[4];
68 u8 slot; /* Slot number, 0=onboard */
70 } __attribute__((packed));
72 struct irq_routing_table {
73 u32 signature; /* PIRQ_SIGNATURE should be here */
74 u16 version; /* PIRQ_VERSION */
75 u16 size; /* Table size in bytes */
76 u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */
77 u16 exclusive_irqs; /* IRQs devoted exclusively to
79 u16 rtr_vendor, rtr_device; /* Vendor and device ID of
81 u32 miniport_data; /* Crap */
83 u8 checksum; /* Modulo 256 checksum must give 0 */
84 struct irq_info slots[0];
85 } __attribute__((packed));
87 extern unsigned int pcibios_irq_mask;
89 extern raw_spinlock_t pci_config_lock;
91 extern int (*pcibios_enable_irq)(struct pci_dev *dev);
92 extern void (*pcibios_disable_irq)(struct pci_dev *dev);
95 int (*read)(unsigned int domain, unsigned int bus, unsigned int devfn,
96 int reg, int len, u32 *val);
97 int (*write)(unsigned int domain, unsigned int bus, unsigned int devfn,
98 int reg, int len, u32 val);
101 extern struct pci_raw_ops *raw_pci_ops;
102 extern struct pci_raw_ops *raw_pci_ext_ops;
104 extern struct pci_raw_ops pci_direct_conf1;
105 extern bool port_cf9_safe;
107 /* arch_initcall level */
108 extern int pci_direct_probe(void);
109 extern void pci_direct_init(int type);
110 extern void pci_pcbios_init(void);
111 extern void __init dmi_check_pciprobe(void);
112 extern void __init dmi_check_skip_isa_align(void);
114 /* some common used subsys_initcalls */
115 extern int __init pci_acpi_init(void);
116 extern void __init pcibios_irq_init(void);
117 extern int __init pcibios_init(void);
118 extern int pci_legacy_init(void);
119 extern void pcibios_fixup_irqs(void);
123 /* "PCI MMCONFIG %04x [bus %02x-%02x]" */
124 #define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
126 struct pci_mmcfg_region {
127 struct list_head list;
134 char name[PCI_MMCFG_RESOURCE_NAME_LEN];
137 extern int __init pci_mmcfg_arch_init(void);
138 extern void __init pci_mmcfg_arch_free(void);
139 extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
141 extern struct list_head pci_mmcfg_list;
143 #define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20)
146 * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
147 * on their northbrige except through the * %eax register. As such, you MUST
148 * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
149 * accessor functions.
150 * In fact just use pci_config_*, nothing else please.
152 static inline unsigned char mmio_config_readb(void __iomem *pos)
155 asm volatile("movb (%1),%%al" : "=a" (val) : "r" (pos));
159 static inline unsigned short mmio_config_readw(void __iomem *pos)
162 asm volatile("movw (%1),%%ax" : "=a" (val) : "r" (pos));
166 static inline unsigned int mmio_config_readl(void __iomem *pos)
169 asm volatile("movl (%1),%%eax" : "=a" (val) : "r" (pos));
173 static inline void mmio_config_writeb(void __iomem *pos, u8 val)
175 asm volatile("movb %%al,(%1)" : : "a" (val), "r" (pos) : "memory");
178 static inline void mmio_config_writew(void __iomem *pos, u16 val)
180 asm volatile("movw %%ax,(%1)" : : "a" (val), "r" (pos) : "memory");
183 static inline void mmio_config_writel(void __iomem *pos, u32 val)
185 asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
190 # define x86_default_pci_init pci_acpi_init
192 # define x86_default_pci_init pci_legacy_init
194 # define x86_default_pci_init_irq pcibios_irq_init
195 # define x86_default_pci_fixup_irqs pcibios_fixup_irqs
197 # define x86_default_pci_init NULL
198 # define x86_default_pci_init_irq NULL
199 # define x86_default_pci_fixup_irqs NULL