1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2014 Google, Inc
5 * Memory Type Range Regsters - these are used to tell the CPU whether
6 * memory is cacheable and if so the cache write mode to use.
8 * These can speed up booting. See the mtrr command.
10 * Reference: Intel Architecture Software Developer's Manual, Volume 3:
15 * Note that any console output (e.g. debug()) in this file will likely fail
16 * since the MTRR registers are sometimes in flux.
22 #include <asm/cache.h>
28 DECLARE_GLOBAL_DATA_PTR;
30 /* Prepare to adjust MTRRs */
31 void mtrr_open(struct mtrr_state *state, bool do_caches)
33 if (!gd->arch.has_mtrr)
37 state->enable_cache = dcache_status();
39 if (state->enable_cache)
42 state->deftype = native_read_msr(MTRR_DEF_TYPE_MSR);
43 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype & ~MTRR_DEF_TYPE_EN);
46 /* Clean up after adjusting MTRRs, and enable them */
47 void mtrr_close(struct mtrr_state *state, bool do_caches)
49 if (!gd->arch.has_mtrr)
52 wrmsrl(MTRR_DEF_TYPE_MSR, state->deftype | MTRR_DEF_TYPE_EN);
53 if (do_caches && state->enable_cache)
57 static void set_var_mtrr(uint reg, uint type, uint64_t start, uint64_t size)
61 wrmsrl(MTRR_PHYS_BASE_MSR(reg), start | type);
63 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
64 wrmsrl(MTRR_PHYS_MASK_MSR(reg), mask | MTRR_PHYS_MASK_VALID);
67 void mtrr_read_all(struct mtrr_info *info)
71 for (i = 0; i < MTRR_COUNT; i++) {
72 info->mtrr[i].base = native_read_msr(MTRR_PHYS_BASE_MSR(i));
73 info->mtrr[i].mask = native_read_msr(MTRR_PHYS_MASK_MSR(i));
77 void mtrr_write_all(struct mtrr_info *info)
79 struct mtrr_state state;
82 for (i = 0; i < MTRR_COUNT; i++) {
83 mtrr_open(&state, true);
84 wrmsrl(MTRR_PHYS_BASE_MSR(i), info->mtrr[i].base);
85 wrmsrl(MTRR_PHYS_MASK_MSR(i), info->mtrr[i].mask);
86 mtrr_close(&state, true);
90 static void write_mtrrs(void *arg)
92 struct mtrr_info *info = arg;
97 static void read_mtrrs(void *arg)
99 struct mtrr_info *info = arg;
105 * mtrr_copy_to_aps() - Copy the MTRRs from the boot CPU to other CPUs
107 * @return 0 on success, -ve on failure
109 static int mtrr_copy_to_aps(void)
111 struct mtrr_info info;
114 ret = mp_run_on_cpus(MP_SELECT_BSP, read_mtrrs, &info);
118 return log_msg_ret("bsp", ret);
120 ret = mp_run_on_cpus(MP_SELECT_APS, write_mtrrs, &info);
122 return log_msg_ret("bsp", ret);
127 int mtrr_commit(bool do_caches)
129 struct mtrr_request *req = gd->arch.mtrr_req;
130 struct mtrr_state state;
134 debug("%s: enabled=%d, count=%d\n", __func__, gd->arch.has_mtrr,
135 gd->arch.mtrr_req_count);
136 if (!gd->arch.has_mtrr)
140 mtrr_open(&state, do_caches);
141 debug("open done\n");
142 for (i = 0; i < gd->arch.mtrr_req_count; i++, req++)
143 set_var_mtrr(i, req->type, req->start, req->size);
145 /* Clear the ones that are unused */
147 for (; i < MTRR_COUNT; i++)
148 wrmsrl(MTRR_PHYS_MASK_MSR(i), 0);
150 mtrr_close(&state, do_caches);
151 debug("mtrr done\n");
153 if (gd->flags & GD_FLG_RELOC) {
154 ret = mtrr_copy_to_aps();
156 return log_msg_ret("copy", ret);
162 int mtrr_add_request(int type, uint64_t start, uint64_t size)
164 struct mtrr_request *req;
167 debug("%s: count=%d\n", __func__, gd->arch.mtrr_req_count);
168 if (!gd->arch.has_mtrr)
171 if (gd->arch.mtrr_req_count == MAX_MTRR_REQUESTS)
173 req = &gd->arch.mtrr_req[gd->arch.mtrr_req_count++];
177 debug("%d: type=%d, %08llx %08llx\n", gd->arch.mtrr_req_count - 1,
178 req->type, req->start, req->size);
179 mask = ~(req->size - 1);
180 mask &= (1ULL << CONFIG_CPU_ADDR_BITS) - 1;
181 mask |= MTRR_PHYS_MASK_VALID;
182 debug(" %016llx %016llx\n", req->start | req->type, mask);
187 static int get_var_mtrr_count(void)
189 return msr_read(MSR_MTRR_CAP_MSR).lo & MSR_MTRR_CAP_VCNT;
192 static int get_free_var_mtrr(void)
198 vcnt = get_var_mtrr_count();
200 /* Identify the first var mtrr which is not valid */
201 for (i = 0; i < vcnt; i++) {
202 maskm = msr_read(MTRR_PHYS_MASK_MSR(i));
203 if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0)
207 /* No free var mtrr */
211 int mtrr_set_next_var(uint type, uint64_t start, uint64_t size)
215 mtrr = get_free_var_mtrr();
219 set_var_mtrr(mtrr, type, start, size);
220 debug("MTRR %x: start=%x, size=%x\n", mtrr, (uint)start, (uint)size);