1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014 Google, Inc
5 * Graeme Russ, graeme.russ@gmail.com.
7 * Some portions from coreboot src/mainboard/google/link/romstage.c
8 * and src/cpu/intel/model_206ax/bootblock.c
9 * Copyright (C) 2007-2010 coresystems GmbH
10 * Copyright (C) 2011 Google Inc.
22 #include <asm/cpu_common.h>
23 #include <asm/intel_regs.h>
25 #include <asm/lapic.h>
26 #include <asm/lpc_common.h>
27 #include <asm/microcode.h>
32 #include <asm/processor.h>
33 #include <asm/arch/model_206ax.h>
34 #include <asm/arch/pch.h>
35 #include <asm/arch/sandybridge.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 static int set_flex_ratio_to_tdp_nominal(void)
41 /* Minimum CPU revision for configurable TDP support */
42 if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
45 return cpu_set_flex_ratio_to_tdp_nominal();
48 int arch_cpu_init(void)
50 post_code(POST_CPU_INIT);
52 return x86_cpu_init_f();
55 int arch_cpu_init_dm(void)
57 struct pci_controller *hose;
58 struct udevice *bus, *dev;
62 ret = uclass_get_device(UCLASS_PCI, 0, &bus);
67 hose = dev_get_uclass_priv(bus);
69 /* TODO(sjg@chromium.org): Get rid of gd->hose */
72 ret = uclass_first_device_err(UCLASS_LPC, &dev);
77 * We should do as little as possible before the serial console is
78 * up. Perhaps this should move to later. Our next lot of init
79 * happens in checkcpu() when we have a console
81 ret = set_flex_ratio_to_tdp_nominal();
88 #define PCH_EHCI0_TEMP_BAR0 0xe8000000
89 #define PCH_EHCI1_TEMP_BAR0 0xe8000400
90 #define PCH_XHCI_TEMP_BAR0 0xe8001000
93 * Setup USB controller MMIO BAR to prevent the reference code from
94 * resetting the controller.
96 * The BAR will be re-assigned during device enumeration so these are only
99 * This is used to speed up the resume path.
101 static void enable_usb_bar(struct udevice *bus)
103 pci_dev_t usb0 = PCH_EHCI1_DEV;
104 pci_dev_t usb1 = PCH_EHCI2_DEV;
105 pci_dev_t usb3 = PCH_XHCI_DEV;
108 /* USB Controller 1 */
109 pci_bus_write_config(bus, usb0, PCI_BASE_ADDRESS_0,
110 PCH_EHCI0_TEMP_BAR0, PCI_SIZE_32);
111 pci_bus_read_config(bus, usb0, PCI_COMMAND, &cmd, PCI_SIZE_32);
112 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
113 pci_bus_write_config(bus, usb0, PCI_COMMAND, cmd, PCI_SIZE_32);
115 /* USB Controller 2 */
116 pci_bus_write_config(bus, usb1, PCI_BASE_ADDRESS_0,
117 PCH_EHCI1_TEMP_BAR0, PCI_SIZE_32);
118 pci_bus_read_config(bus, usb1, PCI_COMMAND, &cmd, PCI_SIZE_32);
119 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
120 pci_bus_write_config(bus, usb1, PCI_COMMAND, cmd, PCI_SIZE_32);
122 /* USB3 Controller 1 */
123 pci_bus_write_config(bus, usb3, PCI_BASE_ADDRESS_0,
124 PCH_XHCI_TEMP_BAR0, PCI_SIZE_32);
125 pci_bus_read_config(bus, usb3, PCI_COMMAND, &cmd, PCI_SIZE_32);
126 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
127 pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32);
132 enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
133 struct udevice *dev, *lpc;
138 /* TODO: cmos_post_init() */
139 if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) {
140 debug("soft reset detected\n");
141 boot_mode = PEI_BOOT_SOFT_RESET;
143 /* System is not happy after keyboard reset... */
144 debug("Issuing CF9 warm reset\n");
148 ret = cpu_common_init();
150 debug("%s: cpu_common_init() failed\n", __func__);
154 /* Check PM1_STS[15] to see if we are waking from Sx */
155 pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
157 /* Read PM1_CNT[12:10] to determine which Sx state */
158 pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
160 if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
161 debug("Resume from S3 detected, but disabled.\n");
164 * TODO: An indication of life might be possible here (e.g.
168 post_code(POST_EARLY_INIT);
170 /* Enable SPD ROMs and DDR-III DRAM */
171 ret = uclass_first_device_err(UCLASS_I2C, &dev);
173 debug("%s: Failed to get I2C (ret=%d)\n", __func__, ret);
177 /* Prepare USB controller early in S3 resume */
178 if (boot_mode == PEI_BOOT_RESUME) {
179 uclass_first_device(UCLASS_LPC, &lpc);
180 enable_usb_bar(pci_get_controller(lpc->parent));
183 gd->arch.pei_boot_mode = boot_mode;
188 int print_cpuinfo(void)
190 char processor_name[CPU_MAX_NAME_LEN];
193 /* Print processor name */
194 name = cpu_get_name(processor_name);
195 printf("CPU: %s\n", name);
197 post_code(POST_CPU_INFO);
202 void board_debug_uart_init(void)
204 /* This enables the debug UART */
205 pci_x86_write_config(PCH_LPC_DEV, LPC_EN, COMA_LPC_EN, PCI_SIZE_16);