2 * Copyright 2010 Tilera Corporation. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation, version 2.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
11 * NON INFRINGEMENT. See the GNU General Public License for
15 #ifndef _ASM_TILE_IO_H
16 #define _ASM_TILE_IO_H
18 #include <linux/kernel.h>
19 #include <linux/bug.h>
22 #define IO_SPACE_LIMIT 0xfffffffful
25 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
28 #define xlate_dev_mem_ptr(p) __va(p)
31 * Convert a virtual cached pointer to an uncached pointer.
33 #define xlate_dev_kmem_ptr(p) p
36 * Change "struct page" to physical address.
38 #define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
41 * Some places try to pass in an loff_t for PHYSADDR (?!), so we cast it to
42 * long before casting it to a pointer to avoid compiler warnings.
45 extern void __iomem *ioremap(resource_size_t offset, unsigned long size);
46 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size,
48 extern void iounmap(volatile void __iomem *addr);
50 #define ioremap(physaddr, size) ((void __iomem *)(unsigned long)(physaddr))
51 #define iounmap(addr) ((void)0)
54 #define ioremap_nocache(physaddr, size) ioremap(physaddr, size)
55 #define ioremap_wc(physaddr, size) ioremap(physaddr, size)
56 #define ioremap_writethrough(physaddr, size) ioremap(physaddr, size)
57 #define ioremap_fullcache(physaddr, size) ioremap(physaddr, size)
61 /* Conversion between virtual and physical mappings. */
62 #define mm_ptov(addr) ((void *)phys_to_virt(addr))
63 #define mm_vtop(addr) ((unsigned long)virt_to_phys(addr))
68 * We use inline assembly to guarantee that the compiler does not
69 * split an access into multiple byte-sized accesses as it might
70 * sometimes do if a register data structure is marked "packed".
71 * Obviously on tile we can't tolerate such an access being
72 * actually unaligned, but we want to avoid the case where the
73 * compiler conservatively would generate multiple accesses even
74 * for an aligned read or write.
77 static inline u8 __raw_readb(const volatile void __iomem *addr)
79 return *(const volatile u8 __force *)addr;
82 static inline u16 __raw_readw(const volatile void __iomem *addr)
85 asm volatile("ld2u %0, %1" : "=r" (ret) : "r" (addr));
87 return le16_to_cpu(ret);
90 static inline u32 __raw_readl(const volatile void __iomem *addr)
93 /* Sign-extend to conform to u32 ABI sign-extension convention. */
94 asm volatile("ld4s %0, %1" : "=r" (ret) : "r" (addr));
96 return le32_to_cpu(ret);
99 static inline u64 __raw_readq(const volatile void __iomem *addr)
102 asm volatile("ld %0, %1" : "=r" (ret) : "r" (addr));
104 return le64_to_cpu(ret);
107 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
109 *(volatile u8 __force *)addr = val;
112 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
114 asm volatile("st2 %0, %1" :: "r" (addr), "r" (cpu_to_le16(val)));
117 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
119 asm volatile("st4 %0, %1" :: "r" (addr), "r" (cpu_to_le32(val)));
122 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
124 asm volatile("st %0, %1" :: "r" (addr), "r" (cpu_to_le64(val)));
128 * The on-chip I/O hardware on tilegx is configured with VA=PA for the
129 * kernel's PA range. The low-level APIs and field names use "va" and
130 * "void *" nomenclature, to be consistent with the general notion
131 * that the addresses in question are virtualizable, but in the kernel
132 * context we are actually manipulating PA values. (In other contexts,
133 * e.g. access from user space, we do in fact use real virtual addresses
134 * in the va fields.) To allow readers of the code to understand what's
135 * happening, we direct their attention to this comment by using the
136 * following two functions that just duplicate __va() and __pa().
138 typedef unsigned long tile_io_addr_t;
139 static inline tile_io_addr_t va_to_tile_io_addr(void *va)
141 BUILD_BUG_ON(sizeof(phys_addr_t) != sizeof(tile_io_addr_t));
144 static inline void *tile_io_addr_to_va(tile_io_addr_t tile_io_addr)
146 return __va(tile_io_addr);
149 #else /* CHIP_HAS_MMIO() */
153 extern u8 _tile_readb(unsigned long addr);
154 extern u16 _tile_readw(unsigned long addr);
155 extern u32 _tile_readl(unsigned long addr);
156 extern u64 _tile_readq(unsigned long addr);
157 extern void _tile_writeb(u8 val, unsigned long addr);
158 extern void _tile_writew(u16 val, unsigned long addr);
159 extern void _tile_writel(u32 val, unsigned long addr);
160 extern void _tile_writeq(u64 val, unsigned long addr);
162 #define __raw_readb(addr) _tile_readb((unsigned long)addr)
163 #define __raw_readw(addr) _tile_readw((unsigned long)addr)
164 #define __raw_readl(addr) _tile_readl((unsigned long)addr)
165 #define __raw_readq(addr) _tile_readq((unsigned long)addr)
166 #define __raw_writeb(val, addr) _tile_writeb(val, (unsigned long)addr)
167 #define __raw_writew(val, addr) _tile_writew(val, (unsigned long)addr)
168 #define __raw_writel(val, addr) _tile_writel(val, (unsigned long)addr)
169 #define __raw_writeq(val, addr) _tile_writeq(val, (unsigned long)addr)
171 #else /* CONFIG_PCI */
174 * The tilepro architecture does not support IOMEM unless PCI is enabled.
175 * Unfortunately we can't yet simply not declare these methods,
176 * since some generic code that compiles into the kernel, but
177 * we never run, uses them unconditionally.
180 static inline int iomem_panic(void)
182 panic("readb/writeb and friends do not exist on tile without PCI");
186 static inline u8 readb(unsigned long addr)
188 return iomem_panic();
191 static inline u16 _readw(unsigned long addr)
193 return iomem_panic();
196 static inline u32 readl(unsigned long addr)
198 return iomem_panic();
201 static inline u64 readq(unsigned long addr)
203 return iomem_panic();
206 static inline void writeb(u8 val, unsigned long addr)
211 static inline void writew(u16 val, unsigned long addr)
216 static inline void writel(u32 val, unsigned long addr)
221 static inline void writeq(u64 val, unsigned long addr)
226 #endif /* CONFIG_PCI */
228 #endif /* CHIP_HAS_MMIO() */
230 #define readb __raw_readb
231 #define readw __raw_readw
232 #define readl __raw_readl
233 #define readq __raw_readq
234 #define writeb __raw_writeb
235 #define writew __raw_writew
236 #define writel __raw_writel
237 #define writeq __raw_writeq
239 #define readb_relaxed readb
240 #define readw_relaxed readw
241 #define readl_relaxed readl
242 #define readq_relaxed readq
244 #define ioread8 readb
245 #define ioread16 readw
246 #define ioread32 readl
247 #define ioread64 readq
248 #define iowrite8 writeb
249 #define iowrite16 writew
250 #define iowrite32 writel
251 #define iowrite64 writeq
253 static inline void memset_io(void *dst, int val, size_t len)
256 BUG_ON((unsigned long)dst & 0x3);
257 val = (val & 0xff) * 0x01010101;
258 for (x = 0; x < len; x += 4)
259 writel(val, dst + x);
262 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
266 BUG_ON((unsigned long)src & 0x3);
267 for (x = 0; x < len; x += 4)
268 *(u32 *)(dst + x) = readl(src + x);
271 static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
275 BUG_ON((unsigned long)dst & 0x3);
276 for (x = 0; x < len; x += 4)
277 writel(*(u32 *)(src + x), dst + x);
281 * The Tile architecture does not support IOPORT, even with PCI.
282 * Unfortunately we can't yet simply not declare these methods,
283 * since some generic code that compiles into the kernel, but
284 * we never run, uses them unconditionally.
287 static inline long ioport_panic(void)
289 panic("inb/outb and friends do not exist on tile");
293 static inline void __iomem *ioport_map(unsigned long port, unsigned int len)
295 pr_info("ioport_map: mapping IO resources is unsupported on tile.\n");
299 static inline void ioport_unmap(void __iomem *addr)
304 static inline u8 inb(unsigned long addr)
306 return ioport_panic();
309 static inline u16 inw(unsigned long addr)
311 return ioport_panic();
314 static inline u32 inl(unsigned long addr)
316 return ioport_panic();
319 static inline void outb(u8 b, unsigned long addr)
324 static inline void outw(u16 b, unsigned long addr)
329 static inline void outl(u32 b, unsigned long addr)
334 #define inb_p(addr) inb(addr)
335 #define inw_p(addr) inw(addr)
336 #define inl_p(addr) inl(addr)
337 #define outb_p(x, addr) outb((x), (addr))
338 #define outw_p(x, addr) outw((x), (addr))
339 #define outl_p(x, addr) outl((x), (addr))
341 static inline void insb(unsigned long addr, void *buffer, int count)
346 static inline void insw(unsigned long addr, void *buffer, int count)
351 static inline void insl(unsigned long addr, void *buffer, int count)
356 static inline void outsb(unsigned long addr, const void *buffer, int count)
361 static inline void outsw(unsigned long addr, const void *buffer, int count)
366 static inline void outsl(unsigned long addr, const void *buffer, int count)
371 #define ioread16be(addr) be16_to_cpu(ioread16(addr))
372 #define ioread32be(addr) be32_to_cpu(ioread32(addr))
373 #define iowrite16be(v, addr) iowrite16(be16_to_cpu(v), (addr))
374 #define iowrite32be(v, addr) iowrite32(be32_to_cpu(v), (addr))
376 #define ioread8_rep(p, dst, count) \
377 insb((unsigned long) (p), (dst), (count))
378 #define ioread16_rep(p, dst, count) \
379 insw((unsigned long) (p), (dst), (count))
380 #define ioread32_rep(p, dst, count) \
381 insl((unsigned long) (p), (dst), (count))
383 #define iowrite8_rep(p, src, count) \
384 outsb((unsigned long) (p), (src), (count))
385 #define iowrite16_rep(p, src, count) \
386 outsw((unsigned long) (p), (src), (count))
387 #define iowrite32_rep(p, src, count) \
388 outsl((unsigned long) (p), (src), (count))
390 #define virt_to_bus virt_to_phys
391 #define bus_to_virt phys_to_virt
393 #endif /* _ASM_TILE_IO_H */