arch/sparc64/mm/init.c

   1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/slab.h>
  17 #include <linux/initrd.h>
  18 #include <linux/swap.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/poison.h>
  21 #include <linux/fs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/kprobes.h>
  24 #include <linux/cache.h>
  25 #include <linux/sort.h>
  26 #include <linux/percpu.h>
  27 #include <linux/lmb.h>
  28 #include <linux/mmzone.h>
  29
  30 #include <asm/head.h>
  31 #include <asm/system.h>
  32 #include <asm/page.h>
  33 #include <asm/pgalloc.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/oplib.h>
  36 #include <asm/iommu.h>
  37 #include <asm/io.h>
  38 #include <asm/uaccess.h>
  39 #include <asm/mmu_context.h>
  40 #include <asm/tlbflush.h>
  41 #include <asm/dma.h>
  42 #include <asm/starfire.h>
  43 #include <asm/tlb.h>
  44 #include <asm/spitfire.h>
  45 #include <asm/sections.h>
  46 #include <asm/tsb.h>
  47 #include <asm/hypervisor.h>
  48 #include <asm/prom.h>
  49 #include <asm/sstate.h>
  50 #include <asm/mdesc.h>
  51 #include <asm/cpudata.h>
  52
  53 #define MAX_PHYS_ADDRESS        (1UL << 42UL)
  54 #define KPTE_BITMAP_CHUNK_SZ    (256UL * 1024UL * 1024UL)
  55 #define KPTE_BITMAP_BYTES       \
  56         ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
  57
  58 unsigned long kern_linear_pte_xor[2] __read_mostly;
  59
  60 /* A bitmap, one bit for every 256MB of physical memory.  If the bit
  61  * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
  62  * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
  63  */
  64 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
  65
  66 #ifndef CONFIG_DEBUG_PAGEALLOC
  67 /* A special kernel TSB for 4MB and 256MB linear mappings.
  68  * Space is allocated for this right after the trap table
  69  * in arch/sparc64/kernel/head.S
  70  */
  71 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
  72 #endif
  73
  74 #define MAX_BANKS       32
  75
  76 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
  77 static int pavail_ents __initdata;
  78
  79 static int cmp_p64(const void *a, const void *b)
  80 {
  81         const struct linux_prom64_registers *x = a, *y = b;
  82
  83         if (x->phys_addr > y->phys_addr)
  84                 return 1;
  85         if (x->phys_addr < y->phys_addr)
  86                 return -1;
  87         return 0;
  88 }
  89
  90 static void __init read_obp_memory(const char *property,
  91                                    struct linux_prom64_registers *regs,
  92                                    int *num_ents)
  93 {
  94         int node = prom_finddevice("/memory");
  95         int prop_size = prom_getproplen(node, property);
  96         int ents, ret, i;
  97
  98         ents = prop_size / sizeof(struct linux_prom64_registers);
  99         if (ents > MAX_BANKS) {
 100                 prom_printf("The machine has more %s property entries than "
 101                             "this kernel can support (%d).\n",
 102                             property, MAX_BANKS);
 103                 prom_halt();
 104         }
 105
 106         ret = prom_getproperty(node, property, (char *) regs, prop_size);
 107         if (ret == -1) {
 108                 prom_printf("Couldn't get %s property from /memory.\n");
 109                 prom_halt();
 110         }
 111
 112         /* Sanitize what we got from the firmware, by page aligning
 113          * everything.
 114          */
 115         for (i = 0; i < ents; i++) {
 116                 unsigned long base, size;
 117
 118                 base = regs[i].phys_addr;
 119                 size = regs[i].reg_size;
 120
 121                 size &= PAGE_MASK;
 122                 if (base & ~PAGE_MASK) {
 123                         unsigned long new_base = PAGE_ALIGN(base);
 124
 125                         size -= new_base - base;
 126                         if ((long) size < 0L)
 127                                 size = 0UL;
 128                         base = new_base;
 129                 }
 130                 if (size == 0UL) {
 131                         /* If it is empty, simply get rid of it.
 132                          * This simplifies the logic of the other
 133                          * functions that process these arrays.
 134                          */
 135                         memmove(&regs[i], &regs[i + 1],
 136                                 (ents - i - 1) * sizeof(regs[0]));
 137                         i--;
 138                         ents--;
 139                         continue;
 140                 }
 141                 regs[i].phys_addr = base;
 142                 regs[i].reg_size = size;
 143         }
 144
 145         *num_ents = ents;
 146
 147         sort(regs, ents, sizeof(struct linux_prom64_registers),
 148              cmp_p64, NULL);
 149 }
 150
 151 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
 152
 153 /* Kernel physical address base and size in bytes.  */
 154 unsigned long kern_base __read_mostly;
 155 unsigned long kern_size __read_mostly;
 156
 157 /* Initial ramdisk setup */
 158 extern unsigned long sparc_ramdisk_image64;
 159 extern unsigned int sparc_ramdisk_image;
 160 extern unsigned int sparc_ramdisk_size;
 161
 162 struct page *mem_map_zero __read_mostly;
 163 EXPORT_SYMBOL(mem_map_zero);
 164
 165 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 166
 167 unsigned long sparc64_kern_pri_context __read_mostly;
 168 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 169 unsigned long sparc64_kern_sec_context __read_mostly;
 170
 171 int num_kernel_image_mappings;
 172
 173 #ifdef CONFIG_DEBUG_DCFLUSH
 174 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 175 #ifdef CONFIG_SMP
 176 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 177 #endif
 178 #endif
 179
 180 inline void flush_dcache_page_impl(struct page *page)
 181 {
 182         BUG_ON(tlb_type == hypervisor);
 183 #ifdef CONFIG_DEBUG_DCFLUSH
 184         atomic_inc(&dcpage_flushes);
 185 #endif
 186
 187 #ifdef DCACHE_ALIASING_POSSIBLE
 188         __flush_dcache_page(page_address(page),
 189                             ((tlb_type == spitfire) &&
 190                              page_mapping(page) != NULL));
 191 #else
 192         if (page_mapping(page) != NULL &&
 193             tlb_type == spitfire)
 194                 __flush_icache_page(__pa(page_address(page)));
 195 #endif
 196 }
 197
 198 #define PG_dcache_dirty         PG_arch_1
 199 #define PG_dcache_cpu_shift     32UL
 200 #define PG_dcache_cpu_mask      \
 201         ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
 202
 203 #define dcache_dirty_cpu(page) \
 204         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 205
 206 static inline void set_dcache_dirty(struct page *page, int this_cpu)
 207 {
 208         unsigned long mask = this_cpu;
 209         unsigned long non_cpu_bits;
 210
 211         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 212         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 213
 214         __asm__ __volatile__("1:\n\t"
 215                              "ldx       [%2], %%g7\n\t"
 216                              "and       %%g7, %1, %%g1\n\t"
 217                              "or        %%g1, %0, %%g1\n\t"
 218                              "casx      [%2], %%g7, %%g1\n\t"
 219                              "cmp       %%g7, %%g1\n\t"
 220                              "membar    #StoreLoad | #StoreStore\n\t"
 221                              "bne,pn    %%xcc, 1b\n\t"
 222                              " nop"
 223                              : /* no outputs */
 224                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 225                              : "g1", "g7");
 226 }
 227
 228 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 229 {
 230         unsigned long mask = (1UL << PG_dcache_dirty);
 231
 232         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 233                              "1:\n\t"
 234                              "ldx       [%2], %%g7\n\t"
 235                              "srlx      %%g7, %4, %%g1\n\t"
 236                              "and       %%g1, %3, %%g1\n\t"
 237                              "cmp       %%g1, %0\n\t"
 238                              "bne,pn    %%icc, 2f\n\t"
 239                              " andn     %%g7, %1, %%g1\n\t"
 240                              "casx      [%2], %%g7, %%g1\n\t"
 241                              "cmp       %%g7, %%g1\n\t"
 242                              "membar    #StoreLoad | #StoreStore\n\t"
 243                              "bne,pn    %%xcc, 1b\n\t"
 244                              " nop\n"
 245                              "2:"
 246                              : /* no outputs */
 247                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 248                                "i" (PG_dcache_cpu_mask),
 249                                "i" (PG_dcache_cpu_shift)
 250                              : "g1", "g7");
 251 }
 252
 253 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
 254 {
 255         unsigned long tsb_addr = (unsigned long) ent;
 256
 257         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
 258                 tsb_addr = __pa(tsb_addr);
 259
 260         __tsb_insert(tsb_addr, tag, pte);
 261 }
 262
 263 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
 264 unsigned long _PAGE_SZBITS __read_mostly;
 265
 266 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 267 {
 268         struct mm_struct *mm;
 269         struct tsb *tsb;
 270         unsigned long tag, flags;
 271         unsigned long tsb_index, tsb_hash_shift;
 272
 273         if (tlb_type != hypervisor) {
 274                 unsigned long pfn = pte_pfn(pte);
 275                 unsigned long pg_flags;
 276                 struct page *page;
 277
 278                 if (pfn_valid(pfn) &&
 279                     (page = pfn_to_page(pfn), page_mapping(page)) &&
 280                     ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
 281                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 282                                    PG_dcache_cpu_mask);
 283                         int this_cpu = get_cpu();
 284
 285                         /* This is just to optimize away some function calls
 286                          * in the SMP case.
 287                          */
 288                         if (cpu == this_cpu)
 289                                 flush_dcache_page_impl(page);
 290                         else
 291                                 smp_flush_dcache_page_impl(page, cpu);
 292
 293                         clear_dcache_dirty_cpu(page, cpu);
 294
 295                         put_cpu();
 296                 }
 297         }
 298
 299         mm = vma->vm_mm;
 300
 301         tsb_index = MM_TSB_BASE;
 302         tsb_hash_shift = PAGE_SHIFT;
 303
 304         spin_lock_irqsave(&mm->context.lock, flags);
 305
 306 #ifdef CONFIG_HUGETLB_PAGE
 307         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
 308                 if ((tlb_type == hypervisor &&
 309                      (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
 310                     (tlb_type != hypervisor &&
 311                      (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
 312                         tsb_index = MM_TSB_HUGE;
 313                         tsb_hash_shift = HPAGE_SHIFT;
 314                 }
 315         }
 316 #endif
 317
 318         tsb = mm->context.tsb_block[tsb_index].tsb;
 319         tsb += ((address >> tsb_hash_shift) &
 320                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
 321         tag = (address >> 22UL);
 322         tsb_insert(tsb, tag, pte_val(pte));
 323
 324         spin_unlock_irqrestore(&mm->context.lock, flags);
 325 }
 326
 327 void flush_dcache_page(struct page *page)
 328 {
 329         struct address_space *mapping;
 330         int this_cpu;
 331
 332         if (tlb_type == hypervisor)
 333                 return;
 334
 335         /* Do not bother with the expensive D-cache flush if it
 336          * is merely the zero page.  The 'bigcore' testcase in GDB
 337          * causes this case to run millions of times.
 338          */
 339         if (page == ZERO_PAGE(0))
 340                 return;
 341
 342         this_cpu = get_cpu();
 343
 344         mapping = page_mapping(page);
 345         if (mapping && !mapping_mapped(mapping)) {
 346                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 347                 if (dirty) {
 348                         int dirty_cpu = dcache_dirty_cpu(page);
 349
 350                         if (dirty_cpu == this_cpu)
 351                                 goto out;
 352                         smp_flush_dcache_page_impl(page, dirty_cpu);
 353                 }
 354                 set_dcache_dirty(page, this_cpu);
 355         } else {
 356                 /* We could delay the flush for the !page_mapping
 357                  * case too.  But that case is for exec env/arg
 358                  * pages and those are %99 certainly going to get
 359                  * faulted into the tlb (and thus flushed) anyways.
 360                  */
 361                 flush_dcache_page_impl(page);
 362         }
 363
 364 out:
 365         put_cpu();
 366 }
 367
 368 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 369 {
 370         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
 371         if (tlb_type == spitfire) {
 372                 unsigned long kaddr;
 373
 374                 /* This code only runs on Spitfire cpus so this is
 375                  * why we can assume _PAGE_PADDR_4U.
 376                  */
 377                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
 378                         unsigned long paddr, mask = _PAGE_PADDR_4U;
 379
 380                         if (kaddr >= PAGE_OFFSET)
 381                                 paddr = kaddr & mask;
 382                         else {
 383                                 pgd_t *pgdp = pgd_offset_k(kaddr);
 384                                 pud_t *pudp = pud_offset(pgdp, kaddr);
 385                                 pmd_t *pmdp = pmd_offset(pudp, kaddr);
 386                                 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
 387
 388                                 paddr = pte_val(*ptep) & mask;
 389                         }
 390                         __flush_icache_page(paddr);
 391                 }
 392         }
 393 }
 394
 395 void show_mem(void)
 396 {
 397         unsigned long total = 0, reserved = 0;
 398         unsigned long shared = 0, cached = 0;
 399         pg_data_t *pgdat;
 400
 401         printk(KERN_INFO "Mem-info:\n");
 402         show_free_areas();
 403         printk(KERN_INFO "Free swap:       %6ldkB\n",
 404                nr_swap_pages << (PAGE_SHIFT-10));
 405         for_each_online_pgdat(pgdat) {
 406                 unsigned long i, flags;
 407
 408                 pgdat_resize_lock(pgdat, &flags);
 409                 for (i = 0; i < pgdat->node_spanned_pages; i++) {
 410                         struct page *page = pgdat_page_nr(pgdat, i);
 411                         total++;
 412                         if (PageReserved(page))
 413                                 reserved++;
 414                         else if (PageSwapCache(page))
 415                                 cached++;
 416                         else if (page_count(page))
 417                                 shared += page_count(page) - 1;
 418                 }
 419                 pgdat_resize_unlock(pgdat, &flags);
 420         }
 421
 422         printk(KERN_INFO "%lu pages of RAM\n", total);
 423         printk(KERN_INFO "%lu reserved pages\n", reserved);
 424         printk(KERN_INFO "%lu pages shared\n", shared);
 425         printk(KERN_INFO "%lu pages swap cached\n", cached);
 426
 427         printk(KERN_INFO "%lu pages dirty\n",
 428                global_page_state(NR_FILE_DIRTY));
 429         printk(KERN_INFO "%lu pages writeback\n",
 430                global_page_state(NR_WRITEBACK));
 431         printk(KERN_INFO "%lu pages mapped\n",
 432                global_page_state(NR_FILE_MAPPED));
 433         printk(KERN_INFO "%lu pages slab\n",
 434                 global_page_state(NR_SLAB_RECLAIMABLE) +
 435                 global_page_state(NR_SLAB_UNRECLAIMABLE));
 436         printk(KERN_INFO "%lu pages pagetables\n",
 437                global_page_state(NR_PAGETABLE));
 438 }
 439
 440 void mmu_info(struct seq_file *m)
 441 {
 442         if (tlb_type == cheetah)
 443                 seq_printf(m, "MMU Type\t: Cheetah\n");
 444         else if (tlb_type == cheetah_plus)
 445                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 446         else if (tlb_type == spitfire)
 447                 seq_printf(m, "MMU Type\t: Spitfire\n");
 448         else if (tlb_type == hypervisor)
 449                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
 450         else
 451                 seq_printf(m, "MMU Type\t: ???\n");
 452
 453 #ifdef CONFIG_DEBUG_DCFLUSH
 454         seq_printf(m, "DCPageFlushes\t: %d\n",
 455                    atomic_read(&dcpage_flushes));
 456 #ifdef CONFIG_SMP
 457         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 458                    atomic_read(&dcpage_flushes_xcall));
 459 #endif /* CONFIG_SMP */
 460 #endif /* CONFIG_DEBUG_DCFLUSH */
 461 }
 462
 463 struct linux_prom_translation {
 464         unsigned long virt;
 465         unsigned long size;
 466         unsigned long data;
 467 };
 468
 469 /* Exported for kernel TLB miss handling in ktlb.S */
 470 struct linux_prom_translation prom_trans[512] __read_mostly;
 471 unsigned int prom_trans_ents __read_mostly;
 472
 473 /* Exported for SMP bootup purposes. */
 474 unsigned long kern_locked_tte_data;
 475
 476 /* The obp translations are saved based on 8k pagesize, since obp can
 477  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 478  * HI_OBP_ADDRESS range are handled in ktlb.S.
 479  */
 480 static inline int in_obp_range(unsigned long vaddr)
 481 {
 482         return (vaddr >= LOW_OBP_ADDRESS &&
 483                 vaddr < HI_OBP_ADDRESS);
 484 }
 485
 486 static int cmp_ptrans(const void *a, const void *b)
 487 {
 488         const struct linux_prom_translation *x = a, *y = b;
 489
 490         if (x->virt > y->virt)
 491                 return 1;
 492         if (x->virt < y->virt)
 493                 return -1;
 494         return 0;
 495 }
 496
 497 /* Read OBP translations property into 'prom_trans[]'.  */
 498 static void __init read_obp_translations(void)
 499 {
 500         int n, node, ents, first, last, i;
 501
 502         node = prom_finddevice("/virtual-memory");
 503         n = prom_getproplen(node, "translations");
 504         if (unlikely(n == 0 || n == -1)) {
 505                 prom_printf("prom_mappings: Couldn't get size.\n");
 506                 prom_halt();
 507         }
 508         if (unlikely(n > sizeof(prom_trans))) {
 509                 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
 510                 prom_halt();
 511         }
 512
 513         if ((n = prom_getproperty(node, "translations",
 514                                   (char *)&prom_trans[0],
 515                                   sizeof(prom_trans))) == -1) {
 516                 prom_printf("prom_mappings: Couldn't get property.\n");
 517                 prom_halt();
 518         }
 519
 520         n = n / sizeof(struct linux_prom_translation);
 521
 522         ents = n;
 523
 524         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
 525              cmp_ptrans, NULL);
 526
 527         /* Now kick out all the non-OBP entries.  */
 528         for (i = 0; i < ents; i++) {
 529                 if (in_obp_range(prom_trans[i].virt))
 530                         break;
 531         }
 532         first = i;
 533         for (; i < ents; i++) {
 534                 if (!in_obp_range(prom_trans[i].virt))
 535                         break;
 536         }
 537         last = i;
 538
 539         for (i = 0; i < (last - first); i++) {
 540                 struct linux_prom_translation *src = &prom_trans[i + first];
 541                 struct linux_prom_translation *dest = &prom_trans[i];
 542
 543                 *dest = *src;
 544         }
 545         for (; i < ents; i++) {
 546                 struct linux_prom_translation *dest = &prom_trans[i];
 547                 dest->virt = dest->size = dest->data = 0x0UL;
 548         }
 549
 550         prom_trans_ents = last - first;
 551
 552         if (tlb_type == spitfire) {
 553                 /* Clear diag TTE bits. */
 554                 for (i = 0; i < prom_trans_ents; i++)
 555                         prom_trans[i].data &= ~0x0003fe0000000000UL;
 556         }
 557 }
 558
 559 static void __init hypervisor_tlb_lock(unsigned long vaddr,
 560                                        unsigned long pte,
 561                                        unsigned long mmu)
 562 {
 563         unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
 564
 565         if (ret != 0) {
 566                 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
 567                             "errors with %lx\n", vaddr, 0, pte, mmu, ret);
 568                 prom_halt();
 569         }
 570 }
 571
 572 static unsigned long kern_large_tte(unsigned long paddr);
 573
 574 static void __init remap_kernel(void)
 575 {
 576         unsigned long phys_page, tte_vaddr, tte_data;
 577         int i, tlb_ent = sparc64_highest_locked_tlbent();
 578
 579         tte_vaddr = (unsigned long) KERNBASE;
 580         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
 581         tte_data = kern_large_tte(phys_page);
 582
 583         kern_locked_tte_data = tte_data;
 584
 585         /* Now lock us into the TLBs via Hypervisor or OBP. */
 586         if (tlb_type == hypervisor) {
 587                 for (i = 0; i < num_kernel_image_mappings; i++) {
 588                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
 589                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
 590                         tte_vaddr += 0x400000;
 591                         tte_data += 0x400000;
 592                 }
 593         } else {
 594                 for (i = 0; i < num_kernel_image_mappings; i++) {
 595                         prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
 596                         prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
 597                         tte_vaddr += 0x400000;
 598                         tte_data += 0x400000;
 599                 }
 600                 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
 601         }
 602         if (tlb_type == cheetah_plus) {
 603                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 604                                             CTX_CHEETAH_PLUS_NUC);
 605                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 606                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 607         }
 608 }
 609
 610
 611 static void __init inherit_prom_mappings(void)
 612 {
 613         read_obp_translations();
 614
 615         /* Now fixup OBP's idea about where we really are mapped. */
 616         printk("Remapping the kernel... ");
 617         remap_kernel();
 618         printk("done.\n");
 619 }
 620
 621 void prom_world(int enter)
 622 {
 623         if (!enter)
 624                 set_fs((mm_segment_t) { get_thread_current_ds() });
 625
 626         __asm__ __volatile__("flushw");
 627 }
 628
 629 void __flush_dcache_range(unsigned long start, unsigned long end)
 630 {
 631         unsigned long va;
 632
 633         if (tlb_type == spitfire) {
 634                 int n = 0;
 635
 636                 for (va = start; va < end; va += 32) {
 637                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 638                         if (++n >= 512)
 639                                 break;
 640                 }
 641         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 642                 start = __pa(start);
 643                 end = __pa(end);
 644                 for (va = start; va < end; va += 32)
 645                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 646                                              "membar #Sync"
 647                                              : /* no outputs */
 648                                              : "r" (va),
 649                                                "i" (ASI_DCACHE_INVALIDATE));
 650         }
 651 }
 652
 653 /* get_new_mmu_context() uses "cache + 1".  */
 654 DEFINE_SPINLOCK(ctx_alloc_lock);
 655 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
 656 #define MAX_CTX_NR      (1UL << CTX_NR_BITS)
 657 #define CTX_BMAP_SLOTS  BITS_TO_LONGS(MAX_CTX_NR)
 658 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
 659
 660 /* Caller does TLB context flushing on local CPU if necessary.
 661  * The caller also ensures that CTX_VALID(mm->context) is false.
 662  *
 663  * We must be careful about boundary cases so that we never
 664  * let the user have CTX 0 (nucleus) or we ever use a CTX
 665  * version of zero (and thus NO_CONTEXT would not be caught
 666  * by version mis-match tests in mmu_context.h).
 667  *
 668  * Always invoked with interrupts disabled.
 669  */
 670 void get_new_mmu_context(struct mm_struct *mm)
 671 {
 672         unsigned long ctx, new_ctx;
 673         unsigned long orig_pgsz_bits;
 674         unsigned long flags;
 675         int new_version;
 676
 677         spin_lock_irqsave(&ctx_alloc_lock, flags);
 678         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 679         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 680         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
 681         new_version = 0;
 682         if (new_ctx >= (1 << CTX_NR_BITS)) {
 683                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 684                 if (new_ctx >= ctx) {
 685                         int i;
 686                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
 687                                 CTX_FIRST_VERSION;
 688                         if (new_ctx == 1)
 689                                 new_ctx = CTX_FIRST_VERSION;
 690
 691                         /* Don't call memset, for 16 entries that's just
 692                          * plain silly...
 693                          */
 694                         mmu_context_bmap[0] = 3;
 695                         mmu_context_bmap[1] = 0;
 696                         mmu_context_bmap[2] = 0;
 697                         mmu_context_bmap[3] = 0;
 698                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
 699                                 mmu_context_bmap[i + 0] = 0;
 700                                 mmu_context_bmap[i + 1] = 0;
 701                                 mmu_context_bmap[i + 2] = 0;
 702                                 mmu_context_bmap[i + 3] = 0;
 703                         }
 704                         new_version = 1;
 705                         goto out;
 706                 }
 707         }
 708         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 709         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
 710 out:
 711         tlb_context_cache = new_ctx;
 712         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
 713         spin_unlock_irqrestore(&ctx_alloc_lock, flags);
 714
 715         if (unlikely(new_version))
 716                 smp_new_mmu_context_version();
 717 }
 718
 719 static int numa_enabled = 1;
 720 static int numa_debug;
 721
 722 static int __init early_numa(char *p)
 723 {
 724         if (!p)
 725                 return 0;
 726
 727         if (strstr(p, "off"))
 728                 numa_enabled = 0;
 729
 730         if (strstr(p, "debug"))
 731                 numa_debug = 1;
 732
 733         return 0;
 734 }
 735 early_param("numa", early_numa);
 736
 737 #define numadbg(f, a...) \
 738 do {    if (numa_debug) \
 739                 printk(KERN_INFO f, ## a); \
 740 } while (0)
 741
 742 static void __init find_ramdisk(unsigned long phys_base)
 743 {
 744 #ifdef CONFIG_BLK_DEV_INITRD
 745         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
 746                 unsigned long ramdisk_image;
 747
 748                 /* Older versions of the bootloader only supported a
 749                  * 32-bit physical address for the ramdisk image
 750                  * location, stored at sparc_ramdisk_image.  Newer
 751                  * SILO versions set sparc_ramdisk_image to zero and
 752                  * provide a full 64-bit physical address at
 753                  * sparc_ramdisk_image64.
 754                  */
 755                 ramdisk_image = sparc_ramdisk_image;
 756                 if (!ramdisk_image)
 757                         ramdisk_image = sparc_ramdisk_image64;
 758
 759                 /* Another bootloader quirk.  The bootloader normalizes
 760                  * the physical address to KERNBASE, so we have to
 761                  * factor that back out and add in the lowest valid
 762                  * physical page address to get the true physical address.
 763                  */
 764                 ramdisk_image -= KERNBASE;
 765                 ramdisk_image += phys_base;
 766
 767                 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
 768                         ramdisk_image, sparc_ramdisk_size);
 769
 770                 initrd_start = ramdisk_image;
 771                 initrd_end = ramdisk_image + sparc_ramdisk_size;
 772
 773                 lmb_reserve(initrd_start, initrd_end);
 774
 775                 initrd_start += PAGE_OFFSET;
 776                 initrd_end += PAGE_OFFSET;
 777         }
 778 #endif
 779 }
 780
 781 struct node_mem_mask {
 782         unsigned long mask;
 783         unsigned long val;
 784         unsigned long bootmem_paddr;
 785 };
 786 static struct node_mem_mask node_masks[MAX_NUMNODES];
 787 static int num_node_masks;
 788
 789 int numa_cpu_lookup_table[NR_CPUS];
 790 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
 791
 792 #ifdef CONFIG_NEED_MULTIPLE_NODES
 793 static bootmem_data_t plat_node_bdata[MAX_NUMNODES];
 794
 795 struct mdesc_mblock {
 796         u64     base;
 797         u64     size;
 798         u64     offset; /* RA-to-PA */
 799 };
 800 static struct mdesc_mblock *mblocks;
 801 static int num_mblocks;
 802
 803 static unsigned long ra_to_pa(unsigned long addr)
 804 {
 805         int i;
 806
 807         for (i = 0; i < num_mblocks; i++) {
 808                 struct mdesc_mblock *m = &mblocks[i];
 809
 810                 if (addr >= m->base &&
 811                     addr < (m->base + m->size)) {
 812                         addr += m->offset;
 813                         break;
 814                 }
 815         }
 816         return addr;
 817 }
 818
 819 static int find_node(unsigned long addr)
 820 {
 821         int i;
 822
 823         addr = ra_to_pa(addr);
 824         for (i = 0; i < num_node_masks; i++) {
 825                 struct node_mem_mask *p = &node_masks[i];
 826
 827                 if ((addr & p->mask) == p->val)
 828                         return i;
 829         }
 830         return -1;
 831 }
 832
 833 static unsigned long nid_range(unsigned long start, unsigned long end,
 834                                int *nid)
 835 {
 836         *nid = find_node(start);
 837         start += PAGE_SIZE;
 838         while (start < end) {
 839                 int n = find_node(start);
 840
 841                 if (n != *nid)
 842                         break;
 843                 start += PAGE_SIZE;
 844         }
 845
 846         return start;
 847 }
 848 #else
 849 static unsigned long nid_range(unsigned long start, unsigned long end,
 850                                int *nid)
 851 {
 852         *nid = 0;
 853         return end;
 854 }
 855 #endif
 856
 857 /* This must be invoked after performing all of the necessary
 858  * add_active_range() calls for 'nid'.  We need to be able to get
 859  * correct data from get_pfn_range_for_nid().
 860  */
 861 static void __init allocate_node_data(int nid)
 862 {
 863         unsigned long paddr, num_pages, start_pfn, end_pfn;
 864         struct pglist_data *p;
 865
 866 #ifdef CONFIG_NEED_MULTIPLE_NODES
 867         paddr = lmb_alloc_nid(sizeof(struct pglist_data),
 868                               SMP_CACHE_BYTES, nid, nid_range);
 869         if (!paddr) {
 870                 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
 871                 prom_halt();
 872         }
 873         NODE_DATA(nid) = __va(paddr);
 874         memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
 875
 876         NODE_DATA(nid)->bdata = &plat_node_bdata[nid];
 877 #endif
 878
 879         p = NODE_DATA(nid);
 880
 881         get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
 882         p->node_start_pfn = start_pfn;
 883         p->node_spanned_pages = end_pfn - start_pfn;
 884
 885         if (p->node_spanned_pages) {
 886                 num_pages = bootmem_bootmap_pages(p->node_spanned_pages);
 887
 888                 paddr = lmb_alloc_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid,
 889                                       nid_range);
 890                 if (!paddr) {
 891                         prom_printf("Cannot allocate bootmap for nid[%d]\n",
 892                                   nid);
 893                         prom_halt();
 894                 }
 895                 node_masks[nid].bootmem_paddr = paddr;
 896         }
 897 }
 898
 899 static void init_node_masks_nonnuma(void)
 900 {
 901         int i;
 902
 903         numadbg("Initializing tables for non-numa.\n");
 904
 905         node_masks[0].mask = node_masks[0].val = 0;
 906         num_node_masks = 1;
 907
 908         for (i = 0; i < NR_CPUS; i++)
 909                 numa_cpu_lookup_table[i] = 0;
 910
 911         numa_cpumask_lookup_table[0] = CPU_MASK_ALL;
 912 }
 913
 914 #ifdef CONFIG_NEED_MULTIPLE_NODES
 915 struct pglist_data *node_data[MAX_NUMNODES];
 916
 917 EXPORT_SYMBOL(numa_cpu_lookup_table);
 918 EXPORT_SYMBOL(numa_cpumask_lookup_table);
 919 EXPORT_SYMBOL(node_data);
 920
 921 struct mdesc_mlgroup {
 922         u64     node;
 923         u64     latency;
 924         u64     match;
 925         u64     mask;
 926 };
 927 static struct mdesc_mlgroup *mlgroups;
 928 static int num_mlgroups;
 929
 930 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
 931                                    u32 cfg_handle)
 932 {
 933         u64 arc;
 934
 935         mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
 936                 u64 target = mdesc_arc_target(md, arc);
 937                 const u64 *val;
 938
 939                 val = mdesc_get_property(md, target,
 940                                          "cfg-handle", NULL);
 941                 if (val && *val == cfg_handle)
 942                         return 0;
 943         }
 944         return -ENODEV;
 945 }
 946
 947 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
 948                                     u32 cfg_handle)
 949 {
 950         u64 arc, candidate, best_latency = ~(u64)0;
 951
 952         candidate = MDESC_NODE_NULL;
 953         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
 954                 u64 target = mdesc_arc_target(md, arc);
 955                 const char *name = mdesc_node_name(md, target);
 956                 const u64 *val;
 957
 958                 if (strcmp(name, "pio-latency-group"))
 959                         continue;
 960
 961                 val = mdesc_get_property(md, target, "latency", NULL);
 962                 if (!val)
 963                         continue;
 964
 965                 if (*val < best_latency) {
 966                         candidate = target;
 967                         best_latency = *val;
 968                 }
 969         }
 970
 971         if (candidate == MDESC_NODE_NULL)
 972                 return -ENODEV;
 973
 974         return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
 975 }
 976
 977 int of_node_to_nid(struct device_node *dp)
 978 {
 979         const struct linux_prom64_registers *regs;
 980         struct mdesc_handle *md;
 981         u32 cfg_handle;
 982         int count, nid;
 983         u64 grp;
 984
 985         if (!mlgroups)
 986                 return -1;
 987
 988         regs = of_get_property(dp, "reg", NULL);
 989         if (!regs)
 990                 return -1;
 991
 992         cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
 993
 994         md = mdesc_grab();
 995
 996         count = 0;
 997         nid = -1;
 998         mdesc_for_each_node_by_name(md, grp, "group") {
 999                 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1000                         nid = count;
1001                         break;
1002                 }
1003                 count++;
1004         }
1005
1006         mdesc_release(md);
1007
1008         return nid;
1009 }
1010
1011 static void add_node_ranges(void)
1012 {
1013         int i;
1014
1015         for (i = 0; i < lmb.memory.cnt; i++) {
1016                 unsigned long size = lmb_size_bytes(&lmb.memory, i);
1017                 unsigned long start, end;
1018
1019                 start = lmb.memory.region[i].base;
1020                 end = start + size;
1021                 while (start < end) {
1022                         unsigned long this_end;
1023                         int nid;
1024
1025                         this_end = nid_range(start, end, &nid);
1026
1027                         numadbg("Adding active range nid[%d] "
1028                                 "start[%lx] end[%lx]\n",
1029                                 nid, start, this_end);
1030
1031                         add_active_range(nid,
1032                                          start >> PAGE_SHIFT,
1033                                          this_end >> PAGE_SHIFT);
1034
1035                         start = this_end;
1036                 }
1037         }
1038 }
1039
1040 static int __init grab_mlgroups(struct mdesc_handle *md)
1041 {
1042         unsigned long paddr;
1043         int count = 0;
1044         u64 node;
1045
1046         mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1047                 count++;
1048         if (!count)
1049                 return -ENOENT;
1050
1051         paddr = lmb_alloc(count * sizeof(struct mdesc_mlgroup),
1052                           SMP_CACHE_BYTES);
1053         if (!paddr)
1054                 return -ENOMEM;
1055
1056         mlgroups = __va(paddr);
1057         num_mlgroups = count;
1058
1059         count = 0;
1060         mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1061                 struct mdesc_mlgroup *m = &mlgroups[count++];
1062                 const u64 *val;
1063
1064                 m->node = node;
1065
1066                 val = mdesc_get_property(md, node, "latency", NULL);
1067                 m->latency = *val;
1068                 val = mdesc_get_property(md, node, "address-match", NULL);
1069                 m->match = *val;
1070                 val = mdesc_get_property(md, node, "address-mask", NULL);
1071                 m->mask = *val;
1072
1073                 numadbg("MLGROUP[%d]: node[%lx] latency[%lx] "
1074                         "match[%lx] mask[%lx]\n",
1075                         count - 1, m->node, m->latency, m->match, m->mask);
1076         }
1077
1078         return 0;
1079 }
1080
1081 static int __init grab_mblocks(struct mdesc_handle *md)
1082 {
1083         unsigned long paddr;
1084         int count = 0;
1085         u64 node;
1086
1087         mdesc_for_each_node_by_name(md, node, "mblock")
1088                 count++;
1089         if (!count)
1090                 return -ENOENT;
1091
1092         paddr = lmb_alloc(count * sizeof(struct mdesc_mblock),
1093                           SMP_CACHE_BYTES);
1094         if (!paddr)
1095                 return -ENOMEM;
1096
1097         mblocks = __va(paddr);
1098         num_mblocks = count;
1099
1100         count = 0;
1101         mdesc_for_each_node_by_name(md, node, "mblock") {
1102                 struct mdesc_mblock *m = &mblocks[count++];
1103                 const u64 *val;
1104
1105                 val = mdesc_get_property(md, node, "base", NULL);
1106                 m->base = *val;
1107                 val = mdesc_get_property(md, node, "size", NULL);
1108                 m->size = *val;
1109                 val = mdesc_get_property(md, node,
1110                                          "address-congruence-offset", NULL);
1111                 m->offset = *val;
1112
1113                 numadbg("MBLOCK[%d]: base[%lx] size[%lx] offset[%lx]\n",
1114                         count - 1, m->base, m->size, m->offset);
1115         }
1116
1117         return 0;
1118 }
1119
1120 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1121                                                u64 grp, cpumask_t *mask)
1122 {
1123         u64 arc;
1124
1125         cpus_clear(*mask);
1126
1127         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1128                 u64 target = mdesc_arc_target(md, arc);
1129                 const char *name = mdesc_node_name(md, target);
1130                 const u64 *id;
1131
1132                 if (strcmp(name, "cpu"))
1133                         continue;
1134                 id = mdesc_get_property(md, target, "id", NULL);
1135                 if (*id < NR_CPUS)
1136                         cpu_set(*id, *mask);
1137         }
1138 }
1139
1140 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1141 {
1142         int i;
1143
1144         for (i = 0; i < num_mlgroups; i++) {
1145                 struct mdesc_mlgroup *m = &mlgroups[i];
1146                 if (m->node == node)
1147                         return m;
1148         }
1149         return NULL;
1150 }
1151
1152 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1153                                       int index)
1154 {
1155         struct mdesc_mlgroup *candidate = NULL;
1156         u64 arc, best_latency = ~(u64)0;
1157         struct node_mem_mask *n;
1158
1159         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1160                 u64 target = mdesc_arc_target(md, arc);
1161                 struct mdesc_mlgroup *m = find_mlgroup(target);
1162                 if (!m)
1163                         continue;
1164                 if (m->latency < best_latency) {
1165                         candidate = m;
1166                         best_latency = m->latency;
1167                 }
1168         }
1169         if (!candidate)
1170                 return -ENOENT;
1171
1172         if (num_node_masks != index) {
1173                 printk(KERN_ERR "Inconsistent NUMA state, "
1174                        "index[%d] != num_node_masks[%d]\n",
1175                        index, num_node_masks);
1176                 return -EINVAL;
1177         }
1178
1179         n = &node_masks[num_node_masks++];
1180
1181         n->mask = candidate->mask;
1182         n->val = candidate->match;
1183
1184         numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%lx])\n",
1185                 index, n->mask, n->val, candidate->latency);
1186
1187         return 0;
1188 }
1189
1190 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1191                                          int index)
1192 {
1193         cpumask_t mask;
1194         int cpu;
1195
1196         numa_parse_mdesc_group_cpus(md, grp, &mask);
1197
1198         for_each_cpu_mask(cpu, mask)
1199                 numa_cpu_lookup_table[cpu] = index;
1200         numa_cpumask_lookup_table[index] = mask;
1201
1202         if (numa_debug) {
1203                 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1204                 for_each_cpu_mask(cpu, mask)
1205                         printk("%d ", cpu);
1206                 printk("]\n");
1207         }
1208
1209         return numa_attach_mlgroup(md, grp, index);
1210 }
1211
1212 static int __init numa_parse_mdesc(void)
1213 {
1214         struct mdesc_handle *md = mdesc_grab();
1215         int i, err, count;
1216         u64 node;
1217
1218         node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1219         if (node == MDESC_NODE_NULL) {
1220                 mdesc_release(md);
1221                 return -ENOENT;
1222         }
1223
1224         err = grab_mblocks(md);
1225         if (err < 0)
1226                 goto out;
1227
1228         err = grab_mlgroups(md);
1229         if (err < 0)
1230                 goto out;
1231
1232         count = 0;
1233         mdesc_for_each_node_by_name(md, node, "group") {
1234                 err = numa_parse_mdesc_group(md, node, count);
1235                 if (err < 0)
1236                         break;
1237                 count++;
1238         }
1239
1240         add_node_ranges();
1241
1242         for (i = 0; i < num_node_masks; i++) {
1243                 allocate_node_data(i);
1244                 node_set_online(i);
1245         }
1246
1247         err = 0;
1248 out:
1249         mdesc_release(md);
1250         return err;
1251 }
1252
1253 static int __init numa_parse_sun4u(void)
1254 {
1255         return -1;
1256 }
1257
1258 static int __init bootmem_init_numa(void)
1259 {
1260         int err = -1;
1261
1262         numadbg("bootmem_init_numa()\n");
1263
1264         if (numa_enabled) {
1265                 if (tlb_type == hypervisor)
1266                         err = numa_parse_mdesc();
1267                 else
1268                         err = numa_parse_sun4u();
1269         }
1270         return err;
1271 }
1272
1273 #else
1274
1275 static int bootmem_init_numa(void)
1276 {
1277         return -1;
1278 }
1279
1280 #endif
1281
1282 static void __init bootmem_init_nonnuma(void)
1283 {
1284         unsigned long top_of_ram = lmb_end_of_DRAM();
1285         unsigned long total_ram = lmb_phys_mem_size();
1286         unsigned int i;
1287
1288         numadbg("bootmem_init_nonnuma()\n");
1289
1290         printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1291                top_of_ram, total_ram);
1292         printk(KERN_INFO "Memory hole size: %ldMB\n",
1293                (top_of_ram - total_ram) >> 20);
1294
1295         init_node_masks_nonnuma();
1296
1297         for (i = 0; i < lmb.memory.cnt; i++) {
1298                 unsigned long size = lmb_size_bytes(&lmb.memory, i);
1299                 unsigned long start_pfn, end_pfn;
1300
1301                 if (!size)
1302                         continue;
1303
1304                 start_pfn = lmb.memory.region[i].base >> PAGE_SHIFT;
1305                 end_pfn = start_pfn + lmb_size_pages(&lmb.memory, i);
1306                 add_active_range(0, start_pfn, end_pfn);
1307         }
1308
1309         allocate_node_data(0);
1310
1311         node_set_online(0);
1312 }
1313
1314 static void __init reserve_range_in_node(int nid, unsigned long start,
1315                                          unsigned long end)
1316 {
1317         numadbg("    reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n",
1318                 nid, start, end);
1319         while (start < end) {
1320                 unsigned long this_end;
1321                 int n;
1322
1323                 this_end = nid_range(start, end, &n);
1324                 if (n == nid) {
1325                         numadbg("      MATCH reserving range [%lx:%lx]\n",
1326                                 start, this_end);
1327                         reserve_bootmem_node(NODE_DATA(nid), start,
1328                                              (this_end - start), BOOTMEM_DEFAULT);
1329                 } else
1330                         numadbg("      NO MATCH, advancing start to %lx\n",
1331                                 this_end);
1332
1333                 start = this_end;
1334         }
1335 }
1336
1337 static void __init trim_reserved_in_node(int nid)
1338 {
1339         int i;
1340
1341         numadbg("  trim_reserved_in_node(%d)\n", nid);
1342
1343         for (i = 0; i < lmb.reserved.cnt; i++) {
1344                 unsigned long start = lmb.reserved.region[i].base;
1345                 unsigned long size = lmb_size_bytes(&lmb.reserved, i);
1346                 unsigned long end = start + size;
1347
1348                 reserve_range_in_node(nid, start, end);
1349         }
1350 }
1351
1352 static void __init bootmem_init_one_node(int nid)
1353 {
1354         struct pglist_data *p;
1355
1356         numadbg("bootmem_init_one_node(%d)\n", nid);
1357
1358         p = NODE_DATA(nid);
1359
1360         if (p->node_spanned_pages) {
1361                 unsigned long paddr = node_masks[nid].bootmem_paddr;
1362                 unsigned long end_pfn;
1363
1364                 end_pfn = p->node_start_pfn + p->node_spanned_pages;
1365
1366                 numadbg("  init_bootmem_node(%d, %lx, %lx, %lx)\n",
1367                         nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn);
1368
1369                 init_bootmem_node(p, paddr >> PAGE_SHIFT,
1370                                   p->node_start_pfn, end_pfn);
1371
1372                 numadbg("  free_bootmem_with_active_regions(%d, %lx)\n",
1373                         nid, end_pfn);
1374                 free_bootmem_with_active_regions(nid, end_pfn);
1375
1376                 trim_reserved_in_node(nid);
1377
1378                 numadbg("  sparse_memory_present_with_active_regions(%d)\n",
1379                         nid);
1380                 sparse_memory_present_with_active_regions(nid);
1381         }
1382 }
1383
1384 static unsigned long __init bootmem_init(unsigned long phys_base)
1385 {
1386         unsigned long end_pfn;
1387         int nid;
1388
1389         end_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT;
1390         max_pfn = max_low_pfn = end_pfn;
1391         min_low_pfn = (phys_base >> PAGE_SHIFT);
1392
1393         if (bootmem_init_numa() < 0)
1394                 bootmem_init_nonnuma();
1395
1396         /* XXX cpu notifier XXX */
1397
1398         for_each_online_node(nid)
1399                 bootmem_init_one_node(nid);
1400
1401         sparse_init();
1402
1403         return end_pfn;
1404 }
1405
1406 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1407 static int pall_ents __initdata;
1408
1409 #ifdef CONFIG_DEBUG_PAGEALLOC
1410 static unsigned long __ref kernel_map_range(unsigned long pstart,
1411                                             unsigned long pend, pgprot_t prot)
1412 {
1413         unsigned long vstart = PAGE_OFFSET + pstart;
1414         unsigned long vend = PAGE_OFFSET + pend;
1415         unsigned long alloc_bytes = 0UL;
1416
1417         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1418                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1419                             vstart, vend);
1420                 prom_halt();
1421         }
1422
1423         while (vstart < vend) {
1424                 unsigned long this_end, paddr = __pa(vstart);
1425                 pgd_t *pgd = pgd_offset_k(vstart);
1426                 pud_t *pud;
1427                 pmd_t *pmd;
1428                 pte_t *pte;
1429
1430                 pud = pud_offset(pgd, vstart);
1431                 if (pud_none(*pud)) {
1432                         pmd_t *new;
1433
1434                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1435                         alloc_bytes += PAGE_SIZE;
1436                         pud_populate(&init_mm, pud, new);
1437                 }
1438
1439                 pmd = pmd_offset(pud, vstart);
1440                 if (!pmd_present(*pmd)) {
1441                         pte_t *new;
1442
1443                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1444                         alloc_bytes += PAGE_SIZE;
1445                         pmd_populate_kernel(&init_mm, pmd, new);
1446                 }
1447
1448                 pte = pte_offset_kernel(pmd, vstart);
1449                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1450                 if (this_end > vend)
1451                         this_end = vend;
1452
1453                 while (vstart < this_end) {
1454                         pte_val(*pte) = (paddr | pgprot_val(prot));
1455
1456                         vstart += PAGE_SIZE;
1457                         paddr += PAGE_SIZE;
1458                         pte++;
1459                 }
1460         }
1461
1462         return alloc_bytes;
1463 }
1464
1465 extern unsigned int kvmap_linear_patch[1];
1466 #endif /* CONFIG_DEBUG_PAGEALLOC */
1467
1468 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1469 {
1470         const unsigned long shift_256MB = 28;
1471         const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1472         const unsigned long size_256MB = (1UL << shift_256MB);
1473
1474         while (start < end) {
1475                 long remains;
1476
1477                 remains = end - start;
1478                 if (remains < size_256MB)
1479                         break;
1480
1481                 if (start & mask_256MB) {
1482                         start = (start + size_256MB) & ~mask_256MB;
1483                         continue;
1484                 }
1485
1486                 while (remains >= size_256MB) {
1487                         unsigned long index = start >> shift_256MB;
1488
1489                         __set_bit(index, kpte_linear_bitmap);
1490
1491                         start += size_256MB;
1492                         remains -= size_256MB;
1493                 }
1494         }
1495 }
1496
1497 static void __init init_kpte_bitmap(void)
1498 {
1499         unsigned long i;
1500
1501         for (i = 0; i < pall_ents; i++) {
1502                 unsigned long phys_start, phys_end;
1503
1504                 phys_start = pall[i].phys_addr;
1505                 phys_end = phys_start + pall[i].reg_size;
1506
1507                 mark_kpte_bitmap(phys_start, phys_end);
1508         }
1509 }
1510
1511 static void __init kernel_physical_mapping_init(void)
1512 {
1513 #ifdef CONFIG_DEBUG_PAGEALLOC
1514         unsigned long i, mem_alloced = 0UL;
1515
1516         for (i = 0; i < pall_ents; i++) {
1517                 unsigned long phys_start, phys_end;
1518
1519                 phys_start = pall[i].phys_addr;
1520                 phys_end = phys_start + pall[i].reg_size;
1521
1522                 mem_alloced += kernel_map_range(phys_start, phys_end,
1523                                                 PAGE_KERNEL);
1524         }
1525
1526         printk("Allocated %ld bytes for kernel page tables.\n",
1527                mem_alloced);
1528
1529         kvmap_linear_patch[0] = 0x01000000; /* nop */
1530         flushi(&kvmap_linear_patch[0]);
1531
1532         __flush_tlb_all();
1533 #endif
1534 }
1535
1536 #ifdef CONFIG_DEBUG_PAGEALLOC
1537 void kernel_map_pages(struct page *page, int numpages, int enable)
1538 {
1539         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1540         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1541
1542         kernel_map_range(phys_start, phys_end,
1543                          (enable ? PAGE_KERNEL : __pgprot(0)));
1544
1545         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1546                                PAGE_OFFSET + phys_end);
1547
1548         /* we should perform an IPI and flush all tlbs,
1549          * but that can deadlock->flush only current cpu.
1550          */
1551         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1552                                  PAGE_OFFSET + phys_end);
1553 }
1554 #endif
1555
1556 unsigned long __init find_ecache_flush_span(unsigned long size)
1557 {
1558         int i;
1559
1560         for (i = 0; i < pavail_ents; i++) {
1561                 if (pavail[i].reg_size >= size)
1562                         return pavail[i].phys_addr;
1563         }
1564
1565         return ~0UL;
1566 }
1567
1568 static void __init tsb_phys_patch(void)
1569 {
1570         struct tsb_ldquad_phys_patch_entry *pquad;
1571         struct tsb_phys_patch_entry *p;
1572
1573         pquad = &__tsb_ldquad_phys_patch;
1574         while (pquad < &__tsb_ldquad_phys_patch_end) {
1575                 unsigned long addr = pquad->addr;
1576
1577                 if (tlb_type == hypervisor)
1578                         *(unsigned int *) addr = pquad->sun4v_insn;
1579                 else
1580                         *(unsigned int *) addr = pquad->sun4u_insn;
1581                 wmb();
1582                 __asm__ __volatile__("flush     %0"
1583                                      : /* no outputs */
1584                                      : "r" (addr));
1585
1586                 pquad++;
1587         }
1588
1589         p = &__tsb_phys_patch;
1590         while (p < &__tsb_phys_patch_end) {
1591                 unsigned long addr = p->addr;
1592
1593                 *(unsigned int *) addr = p->insn;
1594                 wmb();
1595                 __asm__ __volatile__("flush     %0"
1596                                      : /* no outputs */
1597                                      : "r" (addr));
1598
1599                 p++;
1600         }
1601 }
1602
1603 /* Don't mark as init, we give this to the Hypervisor.  */
1604 #ifndef CONFIG_DEBUG_PAGEALLOC
1605 #define NUM_KTSB_DESCR  2
1606 #else
1607 #define NUM_KTSB_DESCR  1
1608 #endif
1609 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1610 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1611
1612 static void __init sun4v_ktsb_init(void)
1613 {
1614         unsigned long ktsb_pa;
1615
1616         /* First KTSB for PAGE_SIZE mappings.  */
1617         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1618
1619         switch (PAGE_SIZE) {
1620         case 8 * 1024:
1621         default:
1622                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1623                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1624                 break;
1625
1626         case 64 * 1024:
1627                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1628                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1629                 break;
1630
1631         case 512 * 1024:
1632                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1633                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1634                 break;
1635
1636         case 4 * 1024 * 1024:
1637                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1638                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1639                 break;
1640         };
1641
1642         ktsb_descr[0].assoc = 1;
1643         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1644         ktsb_descr[0].ctx_idx = 0;
1645         ktsb_descr[0].tsb_base = ktsb_pa;
1646         ktsb_descr[0].resv = 0;
1647
1648 #ifndef CONFIG_DEBUG_PAGEALLOC
1649         /* Second KTSB for 4MB/256MB mappings.  */
1650         ktsb_pa = (kern_base +
1651                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1652
1653         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1654         ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1655                                    HV_PGSZ_MASK_256MB);
1656         ktsb_descr[1].assoc = 1;
1657         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1658         ktsb_descr[1].ctx_idx = 0;
1659         ktsb_descr[1].tsb_base = ktsb_pa;
1660         ktsb_descr[1].resv = 0;
1661 #endif
1662 }
1663
1664 void __cpuinit sun4v_ktsb_register(void)
1665 {
1666         unsigned long pa, ret;
1667
1668         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1669
1670         ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1671         if (ret != 0) {
1672                 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1673                             "errors with %lx\n", pa, ret);
1674                 prom_halt();
1675         }
1676 }
1677
1678 /* paging_init() sets up the page tables */
1679
1680 extern void central_probe(void);
1681
1682 static unsigned long last_valid_pfn;
1683 pgd_t swapper_pg_dir[2048];
1684
1685 static void sun4u_pgprot_init(void);
1686 static void sun4v_pgprot_init(void);
1687
1688 /* Dummy function */
1689 void __init setup_per_cpu_areas(void)
1690 {
1691 }
1692
1693 void __init paging_init(void)
1694 {
1695         unsigned long end_pfn, shift, phys_base;
1696         unsigned long real_end, i;
1697
1698         /* These build time checkes make sure that the dcache_dirty_cpu()
1699          * page->flags usage will work.
1700          *
1701          * When a page gets marked as dcache-dirty, we store the
1702          * cpu number starting at bit 32 in the page->flags.  Also,
1703          * functions like clear_dcache_dirty_cpu use the cpu mask
1704          * in 13-bit signed-immediate instruction fields.
1705          */
1706
1707         /*
1708          * Page flags must not reach into upper 32 bits that are used
1709          * for the cpu number
1710          */
1711         BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1712
1713         /*
1714          * The bit fields placed in the high range must not reach below
1715          * the 32 bit boundary. Otherwise we cannot place the cpu field
1716          * at the 32 bit boundary.
1717          */
1718         BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1719                 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1720
1721         BUILD_BUG_ON(NR_CPUS > 4096);
1722
1723         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1724         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1725
1726         sstate_booting();
1727
1728         /* Invalidate both kernel TSBs.  */
1729         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1730 #ifndef CONFIG_DEBUG_PAGEALLOC
1731         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1732 #endif
1733
1734         if (tlb_type == hypervisor)
1735                 sun4v_pgprot_init();
1736         else
1737                 sun4u_pgprot_init();
1738
1739         if (tlb_type == cheetah_plus ||
1740             tlb_type == hypervisor)
1741                 tsb_phys_patch();
1742
1743         if (tlb_type == hypervisor) {
1744                 sun4v_patch_tlb_handlers();
1745                 sun4v_ktsb_init();
1746         }
1747
1748         lmb_init();
1749
1750         /* Find available physical memory... */
1751         read_obp_memory("available", &pavail[0], &pavail_ents);
1752
1753         phys_base = 0xffffffffffffffffUL;
1754         for (i = 0; i < pavail_ents; i++) {
1755                 phys_base = min(phys_base, pavail[i].phys_addr);
1756                 lmb_add(pavail[i].phys_addr, pavail[i].reg_size);
1757         }
1758
1759         lmb_reserve(kern_base, kern_size);
1760
1761         find_ramdisk(phys_base);
1762
1763         if (cmdline_memory_size)
1764                 lmb_enforce_memory_limit(phys_base + cmdline_memory_size);
1765
1766         lmb_analyze();
1767         lmb_dump_all();
1768
1769         set_bit(0, mmu_context_bmap);
1770
1771         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1772
1773         real_end = (unsigned long)_end;
1774         num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1775         printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1776                num_kernel_image_mappings);
1777
1778         /* Set kernel pgd to upper alias so physical page computations
1779          * work.
1780          */
1781         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1782
1783         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1784
1785         /* Now can init the kernel/bad page tables. */
1786         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1787                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1788
1789         inherit_prom_mappings();
1790
1791         read_obp_memory("reg", &pall[0], &pall_ents);
1792
1793         init_kpte_bitmap();
1794
1795         /* Ok, we can use our TLB miss and window trap handlers safely.  */
1796         setup_tba();
1797
1798         __flush_tlb_all();
1799
1800         if (tlb_type == hypervisor)
1801                 sun4v_ktsb_register();
1802
1803         /* We must setup the per-cpu areas before we pull in the
1804          * PROM and the MDESC.  The code there fills in cpu and
1805          * other information into per-cpu data structures.
1806          */
1807         real_setup_per_cpu_areas();
1808
1809         prom_build_devicetree();
1810
1811         if (tlb_type == hypervisor)
1812                 sun4v_mdesc_init();
1813
1814         /* Setup bootmem... */
1815         last_valid_pfn = end_pfn = bootmem_init(phys_base);
1816
1817 #ifndef CONFIG_NEED_MULTIPLE_NODES
1818         max_mapnr = last_valid_pfn;
1819 #endif
1820         kernel_physical_mapping_init();
1821
1822         {
1823                 unsigned long max_zone_pfns[MAX_NR_ZONES];
1824
1825                 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1826
1827                 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1828
1829                 free_area_init_nodes(max_zone_pfns);
1830         }
1831
1832         printk("Booting Linux...\n");
1833
1834         central_probe();
1835         cpu_probe();
1836 }
1837
1838 int __init page_in_phys_avail(unsigned long paddr)
1839 {
1840         int i;
1841
1842         paddr &= PAGE_MASK;
1843
1844         for (i = 0; i < pavail_ents; i++) {
1845                 unsigned long start, end;
1846
1847                 start = pavail[i].phys_addr;
1848                 end = start + pavail[i].reg_size;
1849
1850                 if (paddr >= start && paddr < end)
1851                         return 1;
1852         }
1853         if (paddr >= kern_base && paddr < (kern_base + kern_size))
1854                 return 1;
1855 #ifdef CONFIG_BLK_DEV_INITRD
1856         if (paddr >= __pa(initrd_start) &&
1857             paddr < __pa(PAGE_ALIGN(initrd_end)))
1858                 return 1;
1859 #endif
1860
1861         return 0;
1862 }
1863
1864 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1865 static int pavail_rescan_ents __initdata;
1866
1867 /* Certain OBP calls, such as fetching "available" properties, can
1868  * claim physical memory.  So, along with initializing the valid
1869  * address bitmap, what we do here is refetch the physical available
1870  * memory list again, and make sure it provides at least as much
1871  * memory as 'pavail' does.
1872  */
1873 static void setup_valid_addr_bitmap_from_pavail(void)
1874 {
1875         int i;
1876
1877         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1878
1879         for (i = 0; i < pavail_ents; i++) {
1880                 unsigned long old_start, old_end;
1881
1882                 old_start = pavail[i].phys_addr;
1883                 old_end = old_start + pavail[i].reg_size;
1884                 while (old_start < old_end) {
1885                         int n;
1886
1887                         for (n = 0; n < pavail_rescan_ents; n++) {
1888                                 unsigned long new_start, new_end;
1889
1890                                 new_start = pavail_rescan[n].phys_addr;
1891                                 new_end = new_start +
1892                                         pavail_rescan[n].reg_size;
1893
1894                                 if (new_start <= old_start &&
1895                                     new_end >= (old_start + PAGE_SIZE)) {
1896                                         set_bit(old_start >> 22,
1897                                                 sparc64_valid_addr_bitmap);
1898                                         goto do_next_page;
1899                                 }
1900                         }
1901
1902                         prom_printf("mem_init: Lost memory in pavail\n");
1903                         prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
1904                                     pavail[i].phys_addr,
1905                                     pavail[i].reg_size);
1906                         prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
1907                                     pavail_rescan[i].phys_addr,
1908                                     pavail_rescan[i].reg_size);
1909                         prom_printf("mem_init: Cannot continue, aborting.\n");
1910                         prom_halt();
1911
1912                 do_next_page:
1913                         old_start += PAGE_SIZE;
1914                 }
1915         }
1916 }
1917
1918 void __init mem_init(void)
1919 {
1920         unsigned long codepages, datapages, initpages;
1921         unsigned long addr, last;
1922         int i;
1923
1924         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1925         i += 1;
1926         sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1927         if (sparc64_valid_addr_bitmap == NULL) {
1928                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1929                 prom_halt();
1930         }
1931         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1932
1933         addr = PAGE_OFFSET + kern_base;
1934         last = PAGE_ALIGN(kern_size) + addr;
1935         while (addr < last) {
1936                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1937                 addr += PAGE_SIZE;
1938         }
1939
1940         setup_valid_addr_bitmap_from_pavail();
1941
1942         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1943
1944 #ifdef CONFIG_NEED_MULTIPLE_NODES
1945         for_each_online_node(i) {
1946                 if (NODE_DATA(i)->node_spanned_pages != 0) {
1947                         totalram_pages +=
1948                                 free_all_bootmem_node(NODE_DATA(i));
1949                 }
1950         }
1951 #else
1952         totalram_pages = free_all_bootmem();
1953 #endif
1954
1955         /* We subtract one to account for the mem_map_zero page
1956          * allocated below.
1957          */
1958         totalram_pages -= 1;
1959         num_physpages = totalram_pages;
1960
1961         /*
1962          * Set up the zero page, mark it reserved, so that page count
1963          * is not manipulated when freeing the page from user ptes.
1964          */
1965         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1966         if (mem_map_zero == NULL) {
1967                 prom_printf("paging_init: Cannot alloc zero page.\n");
1968                 prom_halt();
1969         }
1970         SetPageReserved(mem_map_zero);
1971
1972         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1973         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1974         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1975         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1976         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1977         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1978
1979         printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1980                nr_free_pages() << (PAGE_SHIFT-10),
1981                codepages << (PAGE_SHIFT-10),
1982                datapages << (PAGE_SHIFT-10),
1983                initpages << (PAGE_SHIFT-10),
1984                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1985
1986         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1987                 cheetah_ecache_flush_init();
1988 }
1989
1990 void free_initmem(void)
1991 {
1992         unsigned long addr, initend;
1993
1994         /*
1995          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1996          */
1997         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1998         initend = (unsigned long)(__init_end) & PAGE_MASK;
1999         for (; addr < initend; addr += PAGE_SIZE) {
2000                 unsigned long page;
2001                 struct page *p;
2002
2003                 page = (addr +
2004                         ((unsigned long) __va(kern_base)) -
2005                         ((unsigned long) KERNBASE));
2006                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2007                 p = virt_to_page(page);
2008
2009                 ClearPageReserved(p);
2010                 init_page_count(p);
2011                 __free_page(p);
2012                 num_physpages++;
2013                 totalram_pages++;
2014         }
2015 }
2016
2017 #ifdef CONFIG_BLK_DEV_INITRD
2018 void free_initrd_mem(unsigned long start, unsigned long end)
2019 {
2020         if (start < end)
2021                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
2022         for (; start < end; start += PAGE_SIZE) {
2023                 struct page *p = virt_to_page(start);
2024
2025                 ClearPageReserved(p);
2026                 init_page_count(p);
2027                 __free_page(p);
2028                 num_physpages++;
2029                 totalram_pages++;
2030         }
2031 }
2032 #endif
2033
2034 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
2035 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
2036 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2037 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2038 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2039 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2040
2041 pgprot_t PAGE_KERNEL __read_mostly;
2042 EXPORT_SYMBOL(PAGE_KERNEL);
2043
2044 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2045 pgprot_t PAGE_COPY __read_mostly;
2046
2047 pgprot_t PAGE_SHARED __read_mostly;
2048 EXPORT_SYMBOL(PAGE_SHARED);
2049
2050 pgprot_t PAGE_EXEC __read_mostly;
2051 unsigned long pg_iobits __read_mostly;
2052
2053 unsigned long _PAGE_IE __read_mostly;
2054 EXPORT_SYMBOL(_PAGE_IE);
2055
2056 unsigned long _PAGE_E __read_mostly;
2057 EXPORT_SYMBOL(_PAGE_E);
2058
2059 unsigned long _PAGE_CACHE __read_mostly;
2060 EXPORT_SYMBOL(_PAGE_CACHE);
2061
2062 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2063
2064 #define VMEMMAP_CHUNK_SHIFT     22
2065 #define VMEMMAP_CHUNK           (1UL << VMEMMAP_CHUNK_SHIFT)
2066 #define VMEMMAP_CHUNK_MASK      ~(VMEMMAP_CHUNK - 1UL)
2067 #define VMEMMAP_ALIGN(x)        (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
2068
2069 #define VMEMMAP_SIZE    ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
2070                           sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT)
2071 unsigned long vmemmap_table[VMEMMAP_SIZE];
2072
2073 int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
2074 {
2075         unsigned long vstart = (unsigned long) start;
2076         unsigned long vend = (unsigned long) (start + nr);
2077         unsigned long phys_start = (vstart - VMEMMAP_BASE);
2078         unsigned long phys_end = (vend - VMEMMAP_BASE);
2079         unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2080         unsigned long end = VMEMMAP_ALIGN(phys_end);
2081         unsigned long pte_base;
2082
2083         pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2084                     _PAGE_CP_4U | _PAGE_CV_4U |
2085                     _PAGE_P_4U | _PAGE_W_4U);
2086         if (tlb_type == hypervisor)
2087                 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2088                             _PAGE_CP_4V | _PAGE_CV_4V |
2089                             _PAGE_P_4V | _PAGE_W_4V);
2090
2091         for (; addr < end; addr += VMEMMAP_CHUNK) {
2092                 unsigned long *vmem_pp =
2093                         vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2094                 void *block;
2095
2096                 if (!(*vmem_pp & _PAGE_VALID)) {
2097                         block = vmemmap_alloc_block(1UL << 22, node);
2098                         if (!block)
2099                                 return -ENOMEM;
2100
2101                         *vmem_pp = pte_base | __pa(block);
2102
2103                         printk(KERN_INFO "[%p-%p] page_structs=%lu "
2104                                "node=%d entry=%lu/%lu\n", start, block, nr,
2105                                node,
2106                                addr >> VMEMMAP_CHUNK_SHIFT,
2107                                VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT);
2108                 }
2109         }
2110         return 0;
2111 }
2112 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2113
2114 static void prot_init_common(unsigned long page_none,
2115                              unsigned long page_shared,
2116                              unsigned long page_copy,
2117                              unsigned long page_readonly,
2118                              unsigned long page_exec_bit)
2119 {
2120         PAGE_COPY = __pgprot(page_copy);
2121         PAGE_SHARED = __pgprot(page_shared);
2122
2123         protection_map[0x0] = __pgprot(page_none);
2124         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2125         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2126         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2127         protection_map[0x4] = __pgprot(page_readonly);
2128         protection_map[0x5] = __pgprot(page_readonly);
2129         protection_map[0x6] = __pgprot(page_copy);
2130         protection_map[0x7] = __pgprot(page_copy);
2131         protection_map[0x8] = __pgprot(page_none);
2132         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2133         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2134         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2135         protection_map[0xc] = __pgprot(page_readonly);
2136         protection_map[0xd] = __pgprot(page_readonly);
2137         protection_map[0xe] = __pgprot(page_shared);
2138         protection_map[0xf] = __pgprot(page_shared);
2139 }
2140
2141 static void __init sun4u_pgprot_init(void)
2142 {
2143         unsigned long page_none, page_shared, page_copy, page_readonly;
2144         unsigned long page_exec_bit;
2145
2146         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2147                                 _PAGE_CACHE_4U | _PAGE_P_4U |
2148                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2149                                 _PAGE_EXEC_4U);
2150         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2151                                        _PAGE_CACHE_4U | _PAGE_P_4U |
2152                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2153                                        _PAGE_EXEC_4U | _PAGE_L_4U);
2154         PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
2155
2156         _PAGE_IE = _PAGE_IE_4U;
2157         _PAGE_E = _PAGE_E_4U;
2158         _PAGE_CACHE = _PAGE_CACHE_4U;
2159
2160         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2161                      __ACCESS_BITS_4U | _PAGE_E_4U);
2162
2163 #ifdef CONFIG_DEBUG_PAGEALLOC
2164         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
2165                 0xfffff80000000000;
2166 #else
2167         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2168                 0xfffff80000000000;
2169 #endif
2170         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2171                                    _PAGE_P_4U | _PAGE_W_4U);
2172
2173         /* XXX Should use 256MB on Panther. XXX */
2174         kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2175
2176         _PAGE_SZBITS = _PAGE_SZBITS_4U;
2177         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2178                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2179                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2180
2181
2182         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2183         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2184                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2185         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2186                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2187         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2188                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2189
2190         page_exec_bit = _PAGE_EXEC_4U;
2191
2192         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2193                          page_exec_bit);
2194 }
2195
2196 static void __init sun4v_pgprot_init(void)
2197 {
2198         unsigned long page_none, page_shared, page_copy, page_readonly;
2199         unsigned long page_exec_bit;
2200
2201         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2202                                 _PAGE_CACHE_4V | _PAGE_P_4V |
2203                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2204                                 _PAGE_EXEC_4V);
2205         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2206         PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
2207
2208         _PAGE_IE = _PAGE_IE_4V;
2209         _PAGE_E = _PAGE_E_4V;
2210         _PAGE_CACHE = _PAGE_CACHE_4V;
2211
2212 #ifdef CONFIG_DEBUG_PAGEALLOC
2213         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2214                 0xfffff80000000000;
2215 #else
2216         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2217                 0xfffff80000000000;
2218 #endif
2219         kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2220                                    _PAGE_P_4V | _PAGE_W_4V);
2221
2222 #ifdef CONFIG_DEBUG_PAGEALLOC
2223         kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2224                 0xfffff80000000000;
2225 #else
2226         kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2227                 0xfffff80000000000;
2228 #endif
2229         kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2230                                    _PAGE_P_4V | _PAGE_W_4V);
2231
2232         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2233                      __ACCESS_BITS_4V | _PAGE_E_4V);
2234
2235         _PAGE_SZBITS = _PAGE_SZBITS_4V;
2236         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2237                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2238                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2239                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2240
2241         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2242         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2243                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2244         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2245                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2246         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2247                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2248
2249         page_exec_bit = _PAGE_EXEC_4V;
2250
2251         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2252                          page_exec_bit);
2253 }
2254
2255 unsigned long pte_sz_bits(unsigned long sz)
2256 {
2257         if (tlb_type == hypervisor) {
2258                 switch (sz) {
2259                 case 8 * 1024:
2260                 default:
2261                         return _PAGE_SZ8K_4V;
2262                 case 64 * 1024:
2263                         return _PAGE_SZ64K_4V;
2264                 case 512 * 1024:
2265                         return _PAGE_SZ512K_4V;
2266                 case 4 * 1024 * 1024:
2267                         return _PAGE_SZ4MB_4V;
2268                 };
2269         } else {
2270                 switch (sz) {
2271                 case 8 * 1024:
2272                 default:
2273                         return _PAGE_SZ8K_4U;
2274                 case 64 * 1024:
2275                         return _PAGE_SZ64K_4U;
2276                 case 512 * 1024:
2277                         return _PAGE_SZ512K_4U;
2278                 case 4 * 1024 * 1024:
2279                         return _PAGE_SZ4MB_4U;
2280                 };
2281         }
2282 }
2283
2284 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2285 {
2286         pte_t pte;
2287
2288         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2289         pte_val(pte) |= (((unsigned long)space) << 32);
2290         pte_val(pte) |= pte_sz_bits(page_size);
2291
2292         return pte;
2293 }
2294
2295 static unsigned long kern_large_tte(unsigned long paddr)
2296 {
2297         unsigned long val;
2298
2299         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2300                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2301                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2302         if (tlb_type == hypervisor)
2303                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2304                        _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2305                        _PAGE_EXEC_4V | _PAGE_W_4V);
2306
2307         return val | paddr;
2308 }
2309
2310 /* If not locked, zap it. */
2311 void __flush_tlb_all(void)
2312 {
2313         unsigned long pstate;
2314         int i;
2315
2316         __asm__ __volatile__("flushw\n\t"
2317                              "rdpr      %%pstate, %0\n\t"
2318                              "wrpr      %0, %1, %%pstate"
2319                              : "=r" (pstate)
2320                              : "i" (PSTATE_IE));
2321         if (tlb_type == hypervisor) {
2322                 sun4v_mmu_demap_all();
2323         } else if (tlb_type == spitfire) {
2324                 for (i = 0; i < 64; i++) {
2325                         /* Spitfire Errata #32 workaround */
2326                         /* NOTE: Always runs on spitfire, so no
2327                          *       cheetah+ page size encodings.
2328                          */
2329                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2330                                              "flush     %%g6"
2331                                              : /* No outputs */
2332                                              : "r" (0),
2333                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2334
2335                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2336                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2337                                                      "membar #Sync"
2338                                                      : /* no outputs */
2339                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2340                                 spitfire_put_dtlb_data(i, 0x0UL);
2341                         }
2342
2343                         /* Spitfire Errata #32 workaround */
2344                         /* NOTE: Always runs on spitfire, so no
2345                          *       cheetah+ page size encodings.
2346                          */
2347                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2348                                              "flush     %%g6"
2349                                              : /* No outputs */
2350                                              : "r" (0),
2351                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2352
2353                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2354                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2355                                                      "membar #Sync"
2356                                                      : /* no outputs */
2357                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2358                                 spitfire_put_itlb_data(i, 0x0UL);
2359                         }
2360                 }
2361         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2362                 cheetah_flush_dtlb_all();
2363                 cheetah_flush_itlb_all();
2364         }
2365         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
2366                              : : "r" (pstate));
2367 }