1 /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/sched.h>
11 #include <linux/string.h>
12 #include <linux/init.h>
13 #include <linux/bootmem.h>
15 #include <linux/hugetlb.h>
16 #include <linux/slab.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
28 #include <asm/system.h>
30 #include <asm/pgalloc.h>
31 #include <asm/pgtable.h>
32 #include <asm/oplib.h>
33 #include <asm/iommu.h>
35 #include <asm/uaccess.h>
36 #include <asm/mmu_context.h>
37 #include <asm/tlbflush.h>
39 #include <asm/starfire.h>
41 #include <asm/spitfire.h>
42 #include <asm/sections.h>
44 #include <asm/hypervisor.h>
47 extern void device_scan(void);
49 #define MAX_PHYS_ADDRESS (1UL << 42UL)
50 #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
51 #define KPTE_BITMAP_BYTES \
52 ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8)
54 unsigned long kern_linear_pte_xor[2] __read_mostly;
56 /* A bitmap, one bit for every 256MB of physical memory. If the bit
57 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
58 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
60 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
62 #ifndef CONFIG_DEBUG_PAGEALLOC
63 /* A special kernel TSB for 4MB and 256MB linear mappings. */
64 struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
69 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
70 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
71 static int pavail_ents __initdata;
72 static int pavail_rescan_ents __initdata;
74 static int cmp_p64(const void *a, const void *b)
76 const struct linux_prom64_registers *x = a, *y = b;
78 if (x->phys_addr > y->phys_addr)
80 if (x->phys_addr < y->phys_addr)
85 static void __init read_obp_memory(const char *property,
86 struct linux_prom64_registers *regs,
89 int node = prom_finddevice("/memory");
90 int prop_size = prom_getproplen(node, property);
93 ents = prop_size / sizeof(struct linux_prom64_registers);
94 if (ents > MAX_BANKS) {
95 prom_printf("The machine has more %s property entries than "
96 "this kernel can support (%d).\n",
101 ret = prom_getproperty(node, property, (char *) regs, prop_size);
103 prom_printf("Couldn't get %s property from /memory.\n");
107 /* Sanitize what we got from the firmware, by page aligning
110 for (i = 0; i < ents; i++) {
111 unsigned long base, size;
113 base = regs[i].phys_addr;
114 size = regs[i].reg_size;
117 if (base & ~PAGE_MASK) {
118 unsigned long new_base = PAGE_ALIGN(base);
120 size -= new_base - base;
121 if ((long) size < 0L)
126 /* If it is empty, simply get rid of it.
127 * This simplifies the logic of the other
128 * functions that process these arrays.
130 memmove(®s[i], ®s[i + 1],
131 (ents - i - 1) * sizeof(regs[0]));
136 regs[i].phys_addr = base;
137 regs[i].reg_size = size;
142 sort(regs, ents, sizeof(struct linux_prom64_registers),
146 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
148 /* Kernel physical address base and size in bytes. */
149 unsigned long kern_base __read_mostly;
150 unsigned long kern_size __read_mostly;
152 /* get_new_mmu_context() uses "cache + 1". */
153 DEFINE_SPINLOCK(ctx_alloc_lock);
154 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
155 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
156 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
158 /* Initial ramdisk setup */
159 extern unsigned long sparc_ramdisk_image64;
160 extern unsigned int sparc_ramdisk_image;
161 extern unsigned int sparc_ramdisk_size;
163 struct page *mem_map_zero __read_mostly;
165 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
167 unsigned long sparc64_kern_pri_context __read_mostly;
168 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
169 unsigned long sparc64_kern_sec_context __read_mostly;
173 struct kmem_cache *pgtable_cache __read_mostly;
175 static void zero_ctor(void *addr, struct kmem_cache *cache, unsigned long flags)
180 extern void tsb_cache_init(void);
182 void pgtable_cache_init(void)
184 pgtable_cache = kmem_cache_create("pgtable_cache",
185 PAGE_SIZE, PAGE_SIZE,
187 SLAB_MUST_HWCACHE_ALIGN,
190 if (!pgtable_cache) {
191 prom_printf("Could not create pgtable_cache\n");
197 #ifdef CONFIG_DEBUG_DCFLUSH
198 atomic_t dcpage_flushes = ATOMIC_INIT(0);
200 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
204 inline void flush_dcache_page_impl(struct page *page)
206 BUG_ON(tlb_type == hypervisor);
207 #ifdef CONFIG_DEBUG_DCFLUSH
208 atomic_inc(&dcpage_flushes);
211 #ifdef DCACHE_ALIASING_POSSIBLE
212 __flush_dcache_page(page_address(page),
213 ((tlb_type == spitfire) &&
214 page_mapping(page) != NULL));
216 if (page_mapping(page) != NULL &&
217 tlb_type == spitfire)
218 __flush_icache_page(__pa(page_address(page)));
222 #define PG_dcache_dirty PG_arch_1
223 #define PG_dcache_cpu_shift 24UL
224 #define PG_dcache_cpu_mask (256UL - 1UL)
227 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
230 #define dcache_dirty_cpu(page) \
231 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
233 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
235 unsigned long mask = this_cpu;
236 unsigned long non_cpu_bits;
238 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
239 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
241 __asm__ __volatile__("1:\n\t"
243 "and %%g7, %1, %%g1\n\t"
244 "or %%g1, %0, %%g1\n\t"
245 "casx [%2], %%g7, %%g1\n\t"
247 "membar #StoreLoad | #StoreStore\n\t"
248 "bne,pn %%xcc, 1b\n\t"
251 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
255 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
257 unsigned long mask = (1UL << PG_dcache_dirty);
259 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
262 "srlx %%g7, %4, %%g1\n\t"
263 "and %%g1, %3, %%g1\n\t"
265 "bne,pn %%icc, 2f\n\t"
266 " andn %%g7, %1, %%g1\n\t"
267 "casx [%2], %%g7, %%g1\n\t"
269 "membar #StoreLoad | #StoreStore\n\t"
270 "bne,pn %%xcc, 1b\n\t"
274 : "r" (cpu), "r" (mask), "r" (&page->flags),
275 "i" (PG_dcache_cpu_mask),
276 "i" (PG_dcache_cpu_shift)
280 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
282 unsigned long tsb_addr = (unsigned long) ent;
284 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
285 tsb_addr = __pa(tsb_addr);
287 __tsb_insert(tsb_addr, tag, pte);
290 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
291 unsigned long _PAGE_SZBITS __read_mostly;
293 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
295 struct mm_struct *mm;
297 unsigned long tag, flags;
298 unsigned long tsb_index, tsb_hash_shift;
300 if (tlb_type != hypervisor) {
301 unsigned long pfn = pte_pfn(pte);
302 unsigned long pg_flags;
305 if (pfn_valid(pfn) &&
306 (page = pfn_to_page(pfn), page_mapping(page)) &&
307 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
308 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
310 int this_cpu = get_cpu();
312 /* This is just to optimize away some function calls
316 flush_dcache_page_impl(page);
318 smp_flush_dcache_page_impl(page, cpu);
320 clear_dcache_dirty_cpu(page, cpu);
328 tsb_index = MM_TSB_BASE;
329 tsb_hash_shift = PAGE_SHIFT;
331 spin_lock_irqsave(&mm->context.lock, flags);
333 #ifdef CONFIG_HUGETLB_PAGE
334 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
335 if ((tlb_type == hypervisor &&
336 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
337 (tlb_type != hypervisor &&
338 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
339 tsb_index = MM_TSB_HUGE;
340 tsb_hash_shift = HPAGE_SHIFT;
345 tsb = mm->context.tsb_block[tsb_index].tsb;
346 tsb += ((address >> tsb_hash_shift) &
347 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
348 tag = (address >> 22UL);
349 tsb_insert(tsb, tag, pte_val(pte));
351 spin_unlock_irqrestore(&mm->context.lock, flags);
354 void flush_dcache_page(struct page *page)
356 struct address_space *mapping;
359 if (tlb_type == hypervisor)
362 /* Do not bother with the expensive D-cache flush if it
363 * is merely the zero page. The 'bigcore' testcase in GDB
364 * causes this case to run millions of times.
366 if (page == ZERO_PAGE(0))
369 this_cpu = get_cpu();
371 mapping = page_mapping(page);
372 if (mapping && !mapping_mapped(mapping)) {
373 int dirty = test_bit(PG_dcache_dirty, &page->flags);
375 int dirty_cpu = dcache_dirty_cpu(page);
377 if (dirty_cpu == this_cpu)
379 smp_flush_dcache_page_impl(page, dirty_cpu);
381 set_dcache_dirty(page, this_cpu);
383 /* We could delay the flush for the !page_mapping
384 * case too. But that case is for exec env/arg
385 * pages and those are %99 certainly going to get
386 * faulted into the tlb (and thus flushed) anyways.
388 flush_dcache_page_impl(page);
395 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
397 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
398 if (tlb_type == spitfire) {
401 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
402 __flush_icache_page(__get_phys(kaddr));
408 printk("Mem-info:\n");
410 printk("Free swap: %6ldkB\n",
411 nr_swap_pages << (PAGE_SHIFT-10));
412 printk("%ld pages of RAM\n", num_physpages);
413 printk("%lu free pages\n", nr_free_pages());
416 void mmu_info(struct seq_file *m)
418 if (tlb_type == cheetah)
419 seq_printf(m, "MMU Type\t: Cheetah\n");
420 else if (tlb_type == cheetah_plus)
421 seq_printf(m, "MMU Type\t: Cheetah+\n");
422 else if (tlb_type == spitfire)
423 seq_printf(m, "MMU Type\t: Spitfire\n");
424 else if (tlb_type == hypervisor)
425 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
427 seq_printf(m, "MMU Type\t: ???\n");
429 #ifdef CONFIG_DEBUG_DCFLUSH
430 seq_printf(m, "DCPageFlushes\t: %d\n",
431 atomic_read(&dcpage_flushes));
433 seq_printf(m, "DCPageFlushesXC\t: %d\n",
434 atomic_read(&dcpage_flushes_xcall));
435 #endif /* CONFIG_SMP */
436 #endif /* CONFIG_DEBUG_DCFLUSH */
439 struct linux_prom_translation {
445 /* Exported for kernel TLB miss handling in ktlb.S */
446 struct linux_prom_translation prom_trans[512] __read_mostly;
447 unsigned int prom_trans_ents __read_mostly;
449 /* Exported for SMP bootup purposes. */
450 unsigned long kern_locked_tte_data;
452 /* The obp translations are saved based on 8k pagesize, since obp can
453 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
454 * HI_OBP_ADDRESS range are handled in ktlb.S.
456 static inline int in_obp_range(unsigned long vaddr)
458 return (vaddr >= LOW_OBP_ADDRESS &&
459 vaddr < HI_OBP_ADDRESS);
462 static int cmp_ptrans(const void *a, const void *b)
464 const struct linux_prom_translation *x = a, *y = b;
466 if (x->virt > y->virt)
468 if (x->virt < y->virt)
473 /* Read OBP translations property into 'prom_trans[]'. */
474 static void __init read_obp_translations(void)
476 int n, node, ents, first, last, i;
478 node = prom_finddevice("/virtual-memory");
479 n = prom_getproplen(node, "translations");
480 if (unlikely(n == 0 || n == -1)) {
481 prom_printf("prom_mappings: Couldn't get size.\n");
484 if (unlikely(n > sizeof(prom_trans))) {
485 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
489 if ((n = prom_getproperty(node, "translations",
490 (char *)&prom_trans[0],
491 sizeof(prom_trans))) == -1) {
492 prom_printf("prom_mappings: Couldn't get property.\n");
496 n = n / sizeof(struct linux_prom_translation);
500 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
503 /* Now kick out all the non-OBP entries. */
504 for (i = 0; i < ents; i++) {
505 if (in_obp_range(prom_trans[i].virt))
509 for (; i < ents; i++) {
510 if (!in_obp_range(prom_trans[i].virt))
515 for (i = 0; i < (last - first); i++) {
516 struct linux_prom_translation *src = &prom_trans[i + first];
517 struct linux_prom_translation *dest = &prom_trans[i];
521 for (; i < ents; i++) {
522 struct linux_prom_translation *dest = &prom_trans[i];
523 dest->virt = dest->size = dest->data = 0x0UL;
526 prom_trans_ents = last - first;
528 if (tlb_type == spitfire) {
529 /* Clear diag TTE bits. */
530 for (i = 0; i < prom_trans_ents; i++)
531 prom_trans[i].data &= ~0x0003fe0000000000UL;
535 static void __init hypervisor_tlb_lock(unsigned long vaddr,
539 register unsigned long func asm("%o5");
540 register unsigned long arg0 asm("%o0");
541 register unsigned long arg1 asm("%o1");
542 register unsigned long arg2 asm("%o2");
543 register unsigned long arg3 asm("%o3");
545 func = HV_FAST_MMU_MAP_PERM_ADDR;
550 __asm__ __volatile__("ta 0x80"
551 : "=&r" (func), "=&r" (arg0),
552 "=&r" (arg1), "=&r" (arg2),
554 : "0" (func), "1" (arg0), "2" (arg1),
555 "3" (arg2), "4" (arg3));
557 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
558 "errors with %lx\n", vaddr, 0, pte, mmu, arg0);
563 static unsigned long kern_large_tte(unsigned long paddr);
565 static void __init remap_kernel(void)
567 unsigned long phys_page, tte_vaddr, tte_data;
568 int tlb_ent = sparc64_highest_locked_tlbent();
570 tte_vaddr = (unsigned long) KERNBASE;
571 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
572 tte_data = kern_large_tte(phys_page);
574 kern_locked_tte_data = tte_data;
576 /* Now lock us into the TLBs via Hypervisor or OBP. */
577 if (tlb_type == hypervisor) {
578 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
579 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
581 tte_vaddr += 0x400000;
582 tte_data += 0x400000;
583 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
584 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
587 prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
588 prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
591 prom_dtlb_load(tlb_ent,
593 tte_vaddr + 0x400000);
594 prom_itlb_load(tlb_ent,
596 tte_vaddr + 0x400000);
598 sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
600 if (tlb_type == cheetah_plus) {
601 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
602 CTX_CHEETAH_PLUS_NUC);
603 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
604 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
609 static void __init inherit_prom_mappings(void)
611 read_obp_translations();
613 /* Now fixup OBP's idea about where we really are mapped. */
614 prom_printf("Remapping the kernel... ");
616 prom_printf("done.\n");
619 void prom_world(int enter)
622 set_fs((mm_segment_t) { get_thread_current_ds() });
624 __asm__ __volatile__("flushw");
627 #ifdef DCACHE_ALIASING_POSSIBLE
628 void __flush_dcache_range(unsigned long start, unsigned long end)
632 if (tlb_type == spitfire) {
635 for (va = start; va < end; va += 32) {
636 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
640 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
643 for (va = start; va < end; va += 32)
644 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
648 "i" (ASI_DCACHE_INVALIDATE));
651 #endif /* DCACHE_ALIASING_POSSIBLE */
653 /* Caller does TLB context flushing on local CPU if necessary.
654 * The caller also ensures that CTX_VALID(mm->context) is false.
656 * We must be careful about boundary cases so that we never
657 * let the user have CTX 0 (nucleus) or we ever use a CTX
658 * version of zero (and thus NO_CONTEXT would not be caught
659 * by version mis-match tests in mmu_context.h).
661 * Always invoked with interrupts disabled.
663 void get_new_mmu_context(struct mm_struct *mm)
665 unsigned long ctx, new_ctx;
666 unsigned long orig_pgsz_bits;
670 spin_lock_irqsave(&ctx_alloc_lock, flags);
671 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
672 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
673 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
675 if (new_ctx >= (1 << CTX_NR_BITS)) {
676 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
677 if (new_ctx >= ctx) {
679 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
682 new_ctx = CTX_FIRST_VERSION;
684 /* Don't call memset, for 16 entries that's just
687 mmu_context_bmap[0] = 3;
688 mmu_context_bmap[1] = 0;
689 mmu_context_bmap[2] = 0;
690 mmu_context_bmap[3] = 0;
691 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
692 mmu_context_bmap[i + 0] = 0;
693 mmu_context_bmap[i + 1] = 0;
694 mmu_context_bmap[i + 2] = 0;
695 mmu_context_bmap[i + 3] = 0;
701 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
702 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
704 tlb_context_cache = new_ctx;
705 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
706 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
708 if (unlikely(new_version))
709 smp_new_mmu_context_version();
712 void sparc_ultra_dump_itlb(void)
716 if (tlb_type == spitfire) {
717 printk ("Contents of itlb: ");
718 for (slot = 0; slot < 14; slot++) printk (" ");
719 printk ("%2x:%016lx,%016lx\n",
721 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
722 for (slot = 1; slot < 64; slot+=3) {
723 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
725 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
727 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
729 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
731 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
732 printk ("Contents of itlb0:\n");
733 for (slot = 0; slot < 16; slot+=2) {
734 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
736 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
738 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
740 printk ("Contents of itlb2:\n");
741 for (slot = 0; slot < 128; slot+=2) {
742 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
744 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
746 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
751 void sparc_ultra_dump_dtlb(void)
755 if (tlb_type == spitfire) {
756 printk ("Contents of dtlb: ");
757 for (slot = 0; slot < 14; slot++) printk (" ");
758 printk ("%2x:%016lx,%016lx\n", 0,
759 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
760 for (slot = 1; slot < 64; slot+=3) {
761 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
763 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
765 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
767 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
769 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
770 printk ("Contents of dtlb0:\n");
771 for (slot = 0; slot < 16; slot+=2) {
772 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
774 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
776 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
778 printk ("Contents of dtlb2:\n");
779 for (slot = 0; slot < 512; slot+=2) {
780 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
782 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
784 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
786 if (tlb_type == cheetah_plus) {
787 printk ("Contents of dtlb3:\n");
788 for (slot = 0; slot < 512; slot+=2) {
789 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
791 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
793 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
799 extern unsigned long cmdline_memory_size;
801 /* Find a free area for the bootmem map, avoiding the kernel image
802 * and the initial ramdisk.
804 static unsigned long __init choose_bootmap_pfn(unsigned long start_pfn,
805 unsigned long end_pfn)
807 unsigned long avoid_start, avoid_end, bootmap_size;
810 bootmap_size = ((end_pfn - start_pfn) + 7) / 8;
811 bootmap_size = ALIGN(bootmap_size, sizeof(long));
813 avoid_start = avoid_end = 0;
814 #ifdef CONFIG_BLK_DEV_INITRD
815 avoid_start = initrd_start;
816 avoid_end = PAGE_ALIGN(initrd_end);
819 #ifdef CONFIG_DEBUG_BOOTMEM
820 prom_printf("choose_bootmap_pfn: kern[%lx:%lx] avoid[%lx:%lx]\n",
821 kern_base, PAGE_ALIGN(kern_base + kern_size),
822 avoid_start, avoid_end);
824 for (i = 0; i < pavail_ents; i++) {
825 unsigned long start, end;
827 start = pavail[i].phys_addr;
828 end = start + pavail[i].reg_size;
830 while (start < end) {
831 if (start >= kern_base &&
832 start < PAGE_ALIGN(kern_base + kern_size)) {
833 start = PAGE_ALIGN(kern_base + kern_size);
836 if (start >= avoid_start && start < avoid_end) {
841 if ((end - start) < bootmap_size)
844 if (start < kern_base &&
845 (start + bootmap_size) > kern_base) {
846 start = PAGE_ALIGN(kern_base + kern_size);
850 if (start < avoid_start &&
851 (start + bootmap_size) > avoid_start) {
856 /* OK, it doesn't overlap anything, use it. */
857 #ifdef CONFIG_DEBUG_BOOTMEM
858 prom_printf("choose_bootmap_pfn: Using %lx [%lx]\n",
859 start >> PAGE_SHIFT, start);
861 return start >> PAGE_SHIFT;
865 prom_printf("Cannot find free area for bootmap, aborting.\n");
869 static void __init trim_pavail(unsigned long *cur_size_p,
870 unsigned long *end_of_phys_p)
872 unsigned long to_trim = *cur_size_p - cmdline_memory_size;
873 unsigned long avoid_start, avoid_end;
876 to_trim = PAGE_ALIGN(to_trim);
878 avoid_start = avoid_end = 0;
879 #ifdef CONFIG_BLK_DEV_INITRD
880 avoid_start = initrd_start;
881 avoid_end = PAGE_ALIGN(initrd_end);
884 /* Trim some pavail[] entries in order to satisfy the
885 * requested "mem=xxx" kernel command line specification.
887 * We must not trim off the kernel image area nor the
888 * initial ramdisk range (if any). Also, we must not trim
889 * any pavail[] entry down to zero in order to preserve
890 * the invariant that all pavail[] entries have a non-zero
891 * size which is assumed by all of the code in here.
893 for (i = 0; i < pavail_ents; i++) {
894 unsigned long start, end, kern_end;
895 unsigned long trim_low, trim_high, n;
897 kern_end = PAGE_ALIGN(kern_base + kern_size);
899 trim_low = start = pavail[i].phys_addr;
900 trim_high = end = start + pavail[i].reg_size;
902 if (kern_base >= start &&
904 trim_low = kern_base;
908 if (kern_end >= start &&
910 trim_high = kern_end;
913 avoid_start >= start &&
915 if (trim_low > avoid_start)
916 trim_low = avoid_start;
917 if (avoid_end >= end)
921 avoid_end >= start &&
923 if (trim_high < avoid_end)
924 trim_high = avoid_end;
927 if (trim_high <= trim_low)
930 if (trim_low == start && trim_high == end) {
931 /* Whole chunk is available for trimming.
932 * Trim all except one page, in order to keep
935 n = (end - start) - PAGE_SIZE;
940 pavail[i].phys_addr += n;
941 pavail[i].reg_size -= n;
945 n = (trim_low - start);
950 pavail[i].phys_addr += n;
951 pavail[i].reg_size -= n;
959 pavail[i].reg_size -= n;
971 for (i = 0; i < pavail_ents; i++) {
972 *end_of_phys_p = pavail[i].phys_addr +
974 *cur_size_p += pavail[i].reg_size;
978 static unsigned long __init bootmem_init(unsigned long *pages_avail,
979 unsigned long phys_base)
981 unsigned long bootmap_size, end_pfn;
982 unsigned long end_of_phys_memory = 0UL;
983 unsigned long bootmap_pfn, bytes_avail, size;
986 #ifdef CONFIG_DEBUG_BOOTMEM
987 prom_printf("bootmem_init: Scan pavail, ");
991 for (i = 0; i < pavail_ents; i++) {
992 end_of_phys_memory = pavail[i].phys_addr +
994 bytes_avail += pavail[i].reg_size;
997 /* Determine the location of the initial ramdisk before trying
998 * to honor the "mem=xxx" command line argument. We must know
999 * where the kernel image and the ramdisk image are so that we
1000 * do not trim those two areas from the physical memory map.
1003 #ifdef CONFIG_BLK_DEV_INITRD
1004 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1005 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
1006 unsigned long ramdisk_image = sparc_ramdisk_image ?
1007 sparc_ramdisk_image : sparc_ramdisk_image64;
1008 ramdisk_image -= KERNBASE;
1009 initrd_start = ramdisk_image + phys_base;
1010 initrd_end = initrd_start + sparc_ramdisk_size;
1011 if (initrd_end > end_of_phys_memory) {
1012 printk(KERN_CRIT "initrd extends beyond end of memory "
1013 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1014 initrd_end, end_of_phys_memory);
1021 if (cmdline_memory_size &&
1022 bytes_avail > cmdline_memory_size)
1023 trim_pavail(&bytes_avail,
1024 &end_of_phys_memory);
1026 *pages_avail = bytes_avail >> PAGE_SHIFT;
1028 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1030 /* Initialize the boot-time allocator. */
1031 max_pfn = max_low_pfn = end_pfn;
1032 min_low_pfn = (phys_base >> PAGE_SHIFT);
1034 bootmap_pfn = choose_bootmap_pfn(min_low_pfn, end_pfn);
1036 #ifdef CONFIG_DEBUG_BOOTMEM
1037 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1038 min_low_pfn, bootmap_pfn, max_low_pfn);
1040 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn,
1041 min_low_pfn, end_pfn);
1043 /* Now register the available physical memory with the
1046 for (i = 0; i < pavail_ents; i++) {
1047 #ifdef CONFIG_DEBUG_BOOTMEM
1048 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
1049 i, pavail[i].phys_addr, pavail[i].reg_size);
1051 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
1054 #ifdef CONFIG_BLK_DEV_INITRD
1056 size = initrd_end - initrd_start;
1058 /* Resert the initrd image area. */
1059 #ifdef CONFIG_DEBUG_BOOTMEM
1060 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1061 initrd_start, initrd_end);
1063 reserve_bootmem(initrd_start, size);
1064 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1066 initrd_start += PAGE_OFFSET;
1067 initrd_end += PAGE_OFFSET;
1070 /* Reserve the kernel text/data/bss. */
1071 #ifdef CONFIG_DEBUG_BOOTMEM
1072 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1074 reserve_bootmem(kern_base, kern_size);
1075 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1077 /* Reserve the bootmem map. We do not account for it
1078 * in pages_avail because we will release that memory
1079 * in free_all_bootmem.
1081 size = bootmap_size;
1082 #ifdef CONFIG_DEBUG_BOOTMEM
1083 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1084 (bootmap_pfn << PAGE_SHIFT), size);
1086 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1087 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1089 for (i = 0; i < pavail_ents; i++) {
1090 unsigned long start_pfn, end_pfn;
1092 start_pfn = pavail[i].phys_addr >> PAGE_SHIFT;
1093 end_pfn = (start_pfn + (pavail[i].reg_size >> PAGE_SHIFT));
1094 #ifdef CONFIG_DEBUG_BOOTMEM
1095 prom_printf("memory_present(0, %lx, %lx)\n",
1096 start_pfn, end_pfn);
1098 memory_present(0, start_pfn, end_pfn);
1106 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1107 static int pall_ents __initdata;
1109 #ifdef CONFIG_DEBUG_PAGEALLOC
1110 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1112 unsigned long vstart = PAGE_OFFSET + pstart;
1113 unsigned long vend = PAGE_OFFSET + pend;
1114 unsigned long alloc_bytes = 0UL;
1116 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1117 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1122 while (vstart < vend) {
1123 unsigned long this_end, paddr = __pa(vstart);
1124 pgd_t *pgd = pgd_offset_k(vstart);
1129 pud = pud_offset(pgd, vstart);
1130 if (pud_none(*pud)) {
1133 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1134 alloc_bytes += PAGE_SIZE;
1135 pud_populate(&init_mm, pud, new);
1138 pmd = pmd_offset(pud, vstart);
1139 if (!pmd_present(*pmd)) {
1142 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1143 alloc_bytes += PAGE_SIZE;
1144 pmd_populate_kernel(&init_mm, pmd, new);
1147 pte = pte_offset_kernel(pmd, vstart);
1148 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1149 if (this_end > vend)
1152 while (vstart < this_end) {
1153 pte_val(*pte) = (paddr | pgprot_val(prot));
1155 vstart += PAGE_SIZE;
1164 extern unsigned int kvmap_linear_patch[1];
1165 #endif /* CONFIG_DEBUG_PAGEALLOC */
1167 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1169 const unsigned long shift_256MB = 28;
1170 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1171 const unsigned long size_256MB = (1UL << shift_256MB);
1173 while (start < end) {
1176 remains = end - start;
1177 if (remains < size_256MB)
1180 if (start & mask_256MB) {
1181 start = (start + size_256MB) & ~mask_256MB;
1185 while (remains >= size_256MB) {
1186 unsigned long index = start >> shift_256MB;
1188 __set_bit(index, kpte_linear_bitmap);
1190 start += size_256MB;
1191 remains -= size_256MB;
1196 static void __init kernel_physical_mapping_init(void)
1199 #ifdef CONFIG_DEBUG_PAGEALLOC
1200 unsigned long mem_alloced = 0UL;
1203 read_obp_memory("reg", &pall[0], &pall_ents);
1205 for (i = 0; i < pall_ents; i++) {
1206 unsigned long phys_start, phys_end;
1208 phys_start = pall[i].phys_addr;
1209 phys_end = phys_start + pall[i].reg_size;
1211 mark_kpte_bitmap(phys_start, phys_end);
1213 #ifdef CONFIG_DEBUG_PAGEALLOC
1214 mem_alloced += kernel_map_range(phys_start, phys_end,
1219 #ifdef CONFIG_DEBUG_PAGEALLOC
1220 printk("Allocated %ld bytes for kernel page tables.\n",
1223 kvmap_linear_patch[0] = 0x01000000; /* nop */
1224 flushi(&kvmap_linear_patch[0]);
1230 #ifdef CONFIG_DEBUG_PAGEALLOC
1231 void kernel_map_pages(struct page *page, int numpages, int enable)
1233 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1234 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1236 kernel_map_range(phys_start, phys_end,
1237 (enable ? PAGE_KERNEL : __pgprot(0)));
1239 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1240 PAGE_OFFSET + phys_end);
1242 /* we should perform an IPI and flush all tlbs,
1243 * but that can deadlock->flush only current cpu.
1245 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1246 PAGE_OFFSET + phys_end);
1250 unsigned long __init find_ecache_flush_span(unsigned long size)
1254 for (i = 0; i < pavail_ents; i++) {
1255 if (pavail[i].reg_size >= size)
1256 return pavail[i].phys_addr;
1262 static void __init tsb_phys_patch(void)
1264 struct tsb_ldquad_phys_patch_entry *pquad;
1265 struct tsb_phys_patch_entry *p;
1267 pquad = &__tsb_ldquad_phys_patch;
1268 while (pquad < &__tsb_ldquad_phys_patch_end) {
1269 unsigned long addr = pquad->addr;
1271 if (tlb_type == hypervisor)
1272 *(unsigned int *) addr = pquad->sun4v_insn;
1274 *(unsigned int *) addr = pquad->sun4u_insn;
1276 __asm__ __volatile__("flush %0"
1283 p = &__tsb_phys_patch;
1284 while (p < &__tsb_phys_patch_end) {
1285 unsigned long addr = p->addr;
1287 *(unsigned int *) addr = p->insn;
1289 __asm__ __volatile__("flush %0"
1297 /* Don't mark as init, we give this to the Hypervisor. */
1298 #ifndef CONFIG_DEBUG_PAGEALLOC
1299 #define NUM_KTSB_DESCR 2
1301 #define NUM_KTSB_DESCR 1
1303 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1304 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1306 static void __init sun4v_ktsb_init(void)
1308 unsigned long ktsb_pa;
1310 /* First KTSB for PAGE_SIZE mappings. */
1311 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1313 switch (PAGE_SIZE) {
1316 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1317 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1321 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1322 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1326 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1327 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1330 case 4 * 1024 * 1024:
1331 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1332 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1336 ktsb_descr[0].assoc = 1;
1337 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1338 ktsb_descr[0].ctx_idx = 0;
1339 ktsb_descr[0].tsb_base = ktsb_pa;
1340 ktsb_descr[0].resv = 0;
1342 #ifndef CONFIG_DEBUG_PAGEALLOC
1343 /* Second KTSB for 4MB/256MB mappings. */
1344 ktsb_pa = (kern_base +
1345 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1347 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1348 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1349 HV_PGSZ_MASK_256MB);
1350 ktsb_descr[1].assoc = 1;
1351 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1352 ktsb_descr[1].ctx_idx = 0;
1353 ktsb_descr[1].tsb_base = ktsb_pa;
1354 ktsb_descr[1].resv = 0;
1358 void __cpuinit sun4v_ktsb_register(void)
1360 register unsigned long func asm("%o5");
1361 register unsigned long arg0 asm("%o0");
1362 register unsigned long arg1 asm("%o1");
1365 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1367 func = HV_FAST_MMU_TSB_CTX0;
1368 arg0 = NUM_KTSB_DESCR;
1370 __asm__ __volatile__("ta %6"
1371 : "=&r" (func), "=&r" (arg0), "=&r" (arg1)
1372 : "0" (func), "1" (arg0), "2" (arg1),
1373 "i" (HV_FAST_TRAP));
1376 /* paging_init() sets up the page tables */
1378 extern void cheetah_ecache_flush_init(void);
1379 extern void sun4v_patch_tlb_handlers(void);
1381 static unsigned long last_valid_pfn;
1382 pgd_t swapper_pg_dir[2048];
1384 static void sun4u_pgprot_init(void);
1385 static void sun4v_pgprot_init(void);
1387 void __init paging_init(void)
1389 unsigned long end_pfn, pages_avail, shift, phys_base;
1390 unsigned long real_end, i;
1392 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1393 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1395 /* Invalidate both kernel TSBs. */
1396 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1397 #ifndef CONFIG_DEBUG_PAGEALLOC
1398 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1401 if (tlb_type == hypervisor)
1402 sun4v_pgprot_init();
1404 sun4u_pgprot_init();
1406 if (tlb_type == cheetah_plus ||
1407 tlb_type == hypervisor)
1410 if (tlb_type == hypervisor) {
1411 sun4v_patch_tlb_handlers();
1415 /* Find available physical memory... */
1416 read_obp_memory("available", &pavail[0], &pavail_ents);
1418 phys_base = 0xffffffffffffffffUL;
1419 for (i = 0; i < pavail_ents; i++)
1420 phys_base = min(phys_base, pavail[i].phys_addr);
1422 set_bit(0, mmu_context_bmap);
1424 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1426 real_end = (unsigned long)_end;
1427 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1429 if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1430 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1434 /* Set kernel pgd to upper alias so physical page computations
1437 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1439 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1441 /* Now can init the kernel/bad page tables. */
1442 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1443 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1445 inherit_prom_mappings();
1447 /* Ok, we can use our TLB miss and window trap handlers safely. */
1452 if (tlb_type == hypervisor)
1453 sun4v_ktsb_register();
1455 /* Setup bootmem... */
1457 last_valid_pfn = end_pfn = bootmem_init(&pages_avail, phys_base);
1459 max_mapnr = last_valid_pfn;
1461 kernel_physical_mapping_init();
1463 prom_build_devicetree();
1466 unsigned long zones_size[MAX_NR_ZONES];
1467 unsigned long zholes_size[MAX_NR_ZONES];
1470 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1471 zones_size[znum] = zholes_size[znum] = 0;
1473 zones_size[ZONE_NORMAL] = end_pfn;
1474 zholes_size[ZONE_NORMAL] = end_pfn - pages_avail;
1476 free_area_init_node(0, &contig_page_data, zones_size,
1477 __pa(PAGE_OFFSET) >> PAGE_SHIFT,
1484 static void __init taint_real_pages(void)
1488 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1490 /* Find changes discovered in the physmem available rescan and
1491 * reserve the lost portions in the bootmem maps.
1493 for (i = 0; i < pavail_ents; i++) {
1494 unsigned long old_start, old_end;
1496 old_start = pavail[i].phys_addr;
1497 old_end = old_start +
1499 while (old_start < old_end) {
1502 for (n = 0; n < pavail_rescan_ents; n++) {
1503 unsigned long new_start, new_end;
1505 new_start = pavail_rescan[n].phys_addr;
1506 new_end = new_start +
1507 pavail_rescan[n].reg_size;
1509 if (new_start <= old_start &&
1510 new_end >= (old_start + PAGE_SIZE)) {
1511 set_bit(old_start >> 22,
1512 sparc64_valid_addr_bitmap);
1516 reserve_bootmem(old_start, PAGE_SIZE);
1519 old_start += PAGE_SIZE;
1524 int __init page_in_phys_avail(unsigned long paddr)
1530 for (i = 0; i < pavail_rescan_ents; i++) {
1531 unsigned long start, end;
1533 start = pavail_rescan[i].phys_addr;
1534 end = start + pavail_rescan[i].reg_size;
1536 if (paddr >= start && paddr < end)
1539 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1541 #ifdef CONFIG_BLK_DEV_INITRD
1542 if (paddr >= __pa(initrd_start) &&
1543 paddr < __pa(PAGE_ALIGN(initrd_end)))
1550 void __init mem_init(void)
1552 unsigned long codepages, datapages, initpages;
1553 unsigned long addr, last;
1556 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1558 sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1559 if (sparc64_valid_addr_bitmap == NULL) {
1560 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1563 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1565 addr = PAGE_OFFSET + kern_base;
1566 last = PAGE_ALIGN(kern_size) + addr;
1567 while (addr < last) {
1568 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1574 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1576 #ifdef CONFIG_DEBUG_BOOTMEM
1577 prom_printf("mem_init: Calling free_all_bootmem().\n");
1579 totalram_pages = num_physpages = free_all_bootmem() - 1;
1582 * Set up the zero page, mark it reserved, so that page count
1583 * is not manipulated when freeing the page from user ptes.
1585 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1586 if (mem_map_zero == NULL) {
1587 prom_printf("paging_init: Cannot alloc zero page.\n");
1590 SetPageReserved(mem_map_zero);
1592 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1593 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1594 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1595 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1596 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1597 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1599 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1600 nr_free_pages() << (PAGE_SHIFT-10),
1601 codepages << (PAGE_SHIFT-10),
1602 datapages << (PAGE_SHIFT-10),
1603 initpages << (PAGE_SHIFT-10),
1604 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1606 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1607 cheetah_ecache_flush_init();
1610 void free_initmem(void)
1612 unsigned long addr, initend;
1615 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1617 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1618 initend = (unsigned long)(__init_end) & PAGE_MASK;
1619 for (; addr < initend; addr += PAGE_SIZE) {
1624 ((unsigned long) __va(kern_base)) -
1625 ((unsigned long) KERNBASE));
1626 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1627 p = virt_to_page(page);
1629 ClearPageReserved(p);
1637 #ifdef CONFIG_BLK_DEV_INITRD
1638 void free_initrd_mem(unsigned long start, unsigned long end)
1641 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1642 for (; start < end; start += PAGE_SIZE) {
1643 struct page *p = virt_to_page(start);
1645 ClearPageReserved(p);
1654 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1655 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1656 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1657 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1658 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1659 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1661 pgprot_t PAGE_KERNEL __read_mostly;
1662 EXPORT_SYMBOL(PAGE_KERNEL);
1664 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
1665 pgprot_t PAGE_COPY __read_mostly;
1667 pgprot_t PAGE_SHARED __read_mostly;
1668 EXPORT_SYMBOL(PAGE_SHARED);
1670 pgprot_t PAGE_EXEC __read_mostly;
1671 unsigned long pg_iobits __read_mostly;
1673 unsigned long _PAGE_IE __read_mostly;
1674 EXPORT_SYMBOL(_PAGE_IE);
1676 unsigned long _PAGE_E __read_mostly;
1677 EXPORT_SYMBOL(_PAGE_E);
1679 unsigned long _PAGE_CACHE __read_mostly;
1680 EXPORT_SYMBOL(_PAGE_CACHE);
1682 static void prot_init_common(unsigned long page_none,
1683 unsigned long page_shared,
1684 unsigned long page_copy,
1685 unsigned long page_readonly,
1686 unsigned long page_exec_bit)
1688 PAGE_COPY = __pgprot(page_copy);
1689 PAGE_SHARED = __pgprot(page_shared);
1691 protection_map[0x0] = __pgprot(page_none);
1692 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
1693 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
1694 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
1695 protection_map[0x4] = __pgprot(page_readonly);
1696 protection_map[0x5] = __pgprot(page_readonly);
1697 protection_map[0x6] = __pgprot(page_copy);
1698 protection_map[0x7] = __pgprot(page_copy);
1699 protection_map[0x8] = __pgprot(page_none);
1700 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
1701 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
1702 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
1703 protection_map[0xc] = __pgprot(page_readonly);
1704 protection_map[0xd] = __pgprot(page_readonly);
1705 protection_map[0xe] = __pgprot(page_shared);
1706 protection_map[0xf] = __pgprot(page_shared);
1709 static void __init sun4u_pgprot_init(void)
1711 unsigned long page_none, page_shared, page_copy, page_readonly;
1712 unsigned long page_exec_bit;
1714 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1715 _PAGE_CACHE_4U | _PAGE_P_4U |
1716 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1718 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
1719 _PAGE_CACHE_4U | _PAGE_P_4U |
1720 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
1721 _PAGE_EXEC_4U | _PAGE_L_4U);
1722 PAGE_EXEC = __pgprot(_PAGE_EXEC_4U);
1724 _PAGE_IE = _PAGE_IE_4U;
1725 _PAGE_E = _PAGE_E_4U;
1726 _PAGE_CACHE = _PAGE_CACHE_4U;
1728 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
1729 __ACCESS_BITS_4U | _PAGE_E_4U);
1731 #ifdef CONFIG_DEBUG_PAGEALLOC
1732 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
1735 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
1738 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
1739 _PAGE_P_4U | _PAGE_W_4U);
1741 /* XXX Should use 256MB on Panther. XXX */
1742 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1744 _PAGE_SZBITS = _PAGE_SZBITS_4U;
1745 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
1746 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
1747 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
1750 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
1751 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1752 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
1753 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1754 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1755 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
1756 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
1758 page_exec_bit = _PAGE_EXEC_4U;
1760 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1764 static void __init sun4v_pgprot_init(void)
1766 unsigned long page_none, page_shared, page_copy, page_readonly;
1767 unsigned long page_exec_bit;
1769 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
1770 _PAGE_CACHE_4V | _PAGE_P_4V |
1771 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
1773 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
1774 PAGE_EXEC = __pgprot(_PAGE_EXEC_4V);
1776 _PAGE_IE = _PAGE_IE_4V;
1777 _PAGE_E = _PAGE_E_4V;
1778 _PAGE_CACHE = _PAGE_CACHE_4V;
1780 #ifdef CONFIG_DEBUG_PAGEALLOC
1781 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1784 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
1787 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1788 _PAGE_P_4V | _PAGE_W_4V);
1790 #ifdef CONFIG_DEBUG_PAGEALLOC
1791 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
1794 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1797 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1798 _PAGE_P_4V | _PAGE_W_4V);
1800 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
1801 __ACCESS_BITS_4V | _PAGE_E_4V);
1803 _PAGE_SZBITS = _PAGE_SZBITS_4V;
1804 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
1805 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
1806 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
1807 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
1809 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
1810 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1811 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
1812 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1813 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1814 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
1815 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
1817 page_exec_bit = _PAGE_EXEC_4V;
1819 prot_init_common(page_none, page_shared, page_copy, page_readonly,
1823 unsigned long pte_sz_bits(unsigned long sz)
1825 if (tlb_type == hypervisor) {
1829 return _PAGE_SZ8K_4V;
1831 return _PAGE_SZ64K_4V;
1833 return _PAGE_SZ512K_4V;
1834 case 4 * 1024 * 1024:
1835 return _PAGE_SZ4MB_4V;
1841 return _PAGE_SZ8K_4U;
1843 return _PAGE_SZ64K_4U;
1845 return _PAGE_SZ512K_4U;
1846 case 4 * 1024 * 1024:
1847 return _PAGE_SZ4MB_4U;
1852 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
1856 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
1857 pte_val(pte) |= (((unsigned long)space) << 32);
1858 pte_val(pte) |= pte_sz_bits(page_size);
1863 static unsigned long kern_large_tte(unsigned long paddr)
1867 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
1868 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
1869 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
1870 if (tlb_type == hypervisor)
1871 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
1872 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
1873 _PAGE_EXEC_4V | _PAGE_W_4V);
1879 * Translate PROM's mapping we capture at boot time into physical address.
1880 * The second parameter is only set from prom_callback() invocations.
1882 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
1887 mask = _PAGE_PADDR_4U;
1888 if (tlb_type == hypervisor)
1889 mask = _PAGE_PADDR_4V;
1891 for (i = 0; i < prom_trans_ents; i++) {
1892 struct linux_prom_translation *p = &prom_trans[i];
1894 if (promva >= p->virt &&
1895 promva < (p->virt + p->size)) {
1896 unsigned long base = p->data & mask;
1900 return base + (promva & (8192 - 1));
1908 /* XXX We should kill off this ugly thing at so me point. XXX */
1909 unsigned long sun4u_get_pte(unsigned long addr)
1915 unsigned long mask = _PAGE_PADDR_4U;
1917 if (tlb_type == hypervisor)
1918 mask = _PAGE_PADDR_4V;
1920 if (addr >= PAGE_OFFSET)
1923 if ((addr >= LOW_OBP_ADDRESS) && (addr < HI_OBP_ADDRESS))
1924 return prom_virt_to_phys(addr, NULL);
1926 pgdp = pgd_offset_k(addr);
1927 pudp = pud_offset(pgdp, addr);
1928 pmdp = pmd_offset(pudp, addr);
1929 ptep = pte_offset_kernel(pmdp, addr);
1931 return pte_val(*ptep) & mask;
1934 /* If not locked, zap it. */
1935 void __flush_tlb_all(void)
1937 unsigned long pstate;
1940 __asm__ __volatile__("flushw\n\t"
1941 "rdpr %%pstate, %0\n\t"
1942 "wrpr %0, %1, %%pstate"
1945 if (tlb_type == spitfire) {
1946 for (i = 0; i < 64; i++) {
1947 /* Spitfire Errata #32 workaround */
1948 /* NOTE: Always runs on spitfire, so no
1949 * cheetah+ page size encodings.
1951 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1955 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1957 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
1958 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1961 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1962 spitfire_put_dtlb_data(i, 0x0UL);
1965 /* Spitfire Errata #32 workaround */
1966 /* NOTE: Always runs on spitfire, so no
1967 * cheetah+ page size encodings.
1969 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1973 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1975 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
1976 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1979 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1980 spitfire_put_itlb_data(i, 0x0UL);
1983 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1984 cheetah_flush_dtlb_all();
1985 cheetah_flush_itlb_all();
1987 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1991 #ifdef CONFIG_MEMORY_HOTPLUG
1993 void online_page(struct page *page)
1995 ClearPageReserved(page);
1996 init_page_count(page);
2002 int remove_memory(u64 start, u64 size)
2007 #endif /* CONFIG_MEMORY_HOTPLUG */