1 /* sun4v_ivec.S: Sun4v interrupt vector handling.
3 * Copyright (C) 2006 <davem@davemloft.net>
6 #include <asm/cpudata.h>
7 #include <asm/intr_queue.h>
14 /* Head offset in %g2, tail offset in %g4.
15 * If they are the same, no work.
17 mov INTRQ_CPU_MONDO_HEAD, %g2
18 ldxa [%g2] ASI_QUEUE, %g2
19 mov INTRQ_CPU_MONDO_TAIL, %g4
20 ldxa [%g4] ASI_QUEUE, %g4
22 be,pn %xcc, sun4v_cpu_mondo_queue_empty
25 /* Get &trap_block[smp_processor_id()] into %g4. */
26 ldxa [%g0] ASI_SCRATCHPAD, %g4
27 sub %g4, TRAP_PER_CPU_FAULT_INFO, %g4
29 /* Get CPU mondo queue base phys address into %g7. */
30 ldx [%g4 + TRAP_PER_CPU_CPU_MONDO_PA], %g7
32 /* Now get the cross-call arguments and handler PC, same
35 * 1st 64-bit word: low half is 32-bit PC, put into %g3 and jmpl to it
36 * high half is context arg to MMU flushes, into %g5
37 * 2nd 64-bit word: 64-bit arg, load into %g1
38 * 3rd 64-bit word: 64-bit arg, load into %g7
40 ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g3
43 ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g1
46 ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g7
47 add %g2, 0x40 - 0x8 - 0x8, %g2
49 /* Update queue head pointer. */
50 lduw [%g4 + TRAP_PER_CPU_CPU_MONDO_QMASK], %g4
53 mov INTRQ_CPU_MONDO_HEAD, %g4
54 stxa %g2, [%g4] ASI_QUEUE
60 sun4v_cpu_mondo_queue_empty:
64 /* Head offset in %g2, tail offset in %g4. */
65 mov INTRQ_DEVICE_MONDO_HEAD, %g2
66 ldxa [%g2] ASI_QUEUE, %g2
67 mov INTRQ_DEVICE_MONDO_TAIL, %g4
68 ldxa [%g4] ASI_QUEUE, %g4
70 be,pn %xcc, sun4v_dev_mondo_queue_empty
73 /* Get &trap_block[smp_processor_id()] into %g4. */
74 ldxa [%g0] ASI_SCRATCHPAD, %g4
75 sub %g4, TRAP_PER_CPU_FAULT_INFO, %g4
77 /* Get DEV mondo queue base phys address into %g5. */
78 ldx [%g4 + TRAP_PER_CPU_DEV_MONDO_PA], %g5
80 /* Load IVEC into %g3. */
81 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
84 /* XXX There can be a full 64-byte block of data here.
85 * XXX This is how we can get at MSI vector data.
86 * XXX Current we do not capture this, but when we do we'll
87 * XXX need to add a 64-byte storage area in the struct ino_bucket
88 * XXX or the struct irq_desc.
91 /* Update queue head pointer, this frees up some registers. */
92 lduw [%g4 + TRAP_PER_CPU_DEV_MONDO_QMASK], %g4
95 mov INTRQ_DEVICE_MONDO_HEAD, %g4
96 stxa %g2, [%g4] ASI_QUEUE
99 TRAP_LOAD_IRQ_WORK_PA(%g1, %g4)
101 /* Get __pa(&ivector_table[IVEC]) into %g4. */
102 sethi %hi(ivector_table_pa), %g4
103 ldx [%g4 + %lo(ivector_table_pa)], %g4
108 stxa %g2, [%g4] ASI_PHYS_USE_EC
111 /* Signal the interrupt by setting (1 << pil) in %softint. */
112 wr %g0, 1 << PIL_DEVICE_IRQ, %set_softint
114 sun4v_dev_mondo_queue_empty:
118 /* Head offset in %g2, tail offset in %g4. */
119 mov INTRQ_RESUM_MONDO_HEAD, %g2
120 ldxa [%g2] ASI_QUEUE, %g2
121 mov INTRQ_RESUM_MONDO_TAIL, %g4
122 ldxa [%g4] ASI_QUEUE, %g4
124 be,pn %xcc, sun4v_res_mondo_queue_empty
127 /* Get &trap_block[smp_processor_id()] into %g3. */
128 ldxa [%g0] ASI_SCRATCHPAD, %g3
129 sub %g3, TRAP_PER_CPU_FAULT_INFO, %g3
131 /* Get RES mondo queue base phys address into %g5. */
132 ldx [%g3 + TRAP_PER_CPU_RESUM_MONDO_PA], %g5
134 /* Get RES kernel buffer base phys address into %g7. */
135 ldx [%g3 + TRAP_PER_CPU_RESUM_KBUF_PA], %g7
137 /* If the first word is non-zero, queue is full. */
138 ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g1
139 brnz,pn %g1, sun4v_res_mondo_queue_full
142 lduw [%g3 + TRAP_PER_CPU_RESUM_QMASK], %g4
144 /* Remember this entry's offset in %g1. */
147 /* Copy 64-byte queue entry into kernel buffer. */
148 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
149 stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
151 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
152 stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
154 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
155 stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
157 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
158 stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
160 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
161 stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
163 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
164 stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
166 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
167 stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
169 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
170 stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
173 /* Update queue head pointer. */
176 mov INTRQ_RESUM_MONDO_HEAD, %g4
177 stxa %g2, [%g4] ASI_QUEUE
180 /* Disable interrupts and save register state so we can call
181 * C code. The etrap handling will leave %g4 in %l4 for us
187 ba,pt %xcc, etrap_irq
189 #ifdef CONFIG_TRACE_IRQFLAGS
190 call trace_hardirqs_off
194 add %sp, PTREGS_OFF, %o0
195 call sun4v_resum_error
198 /* Return from trap. */
199 ba,pt %xcc, rtrap_irq
202 sun4v_res_mondo_queue_empty:
205 sun4v_res_mondo_queue_full:
206 /* The queue is full, consolidate our damage by setting
207 * the head equal to the tail. We'll just trap again otherwise.
208 * Call C code to log the event.
210 mov INTRQ_RESUM_MONDO_HEAD, %g2
211 stxa %g4, [%g2] ASI_QUEUE
216 ba,pt %xcc, etrap_irq
218 #ifdef CONFIG_TRACE_IRQFLAGS
219 call trace_hardirqs_off
222 call sun4v_resum_overflow
223 add %sp, PTREGS_OFF, %o0
225 ba,pt %xcc, rtrap_irq
229 /* Head offset in %g2, tail offset in %g4. */
230 mov INTRQ_NONRESUM_MONDO_HEAD, %g2
231 ldxa [%g2] ASI_QUEUE, %g2
232 mov INTRQ_NONRESUM_MONDO_TAIL, %g4
233 ldxa [%g4] ASI_QUEUE, %g4
235 be,pn %xcc, sun4v_nonres_mondo_queue_empty
238 /* Get &trap_block[smp_processor_id()] into %g3. */
239 ldxa [%g0] ASI_SCRATCHPAD, %g3
240 sub %g3, TRAP_PER_CPU_FAULT_INFO, %g3
242 /* Get RES mondo queue base phys address into %g5. */
243 ldx [%g3 + TRAP_PER_CPU_NONRESUM_MONDO_PA], %g5
245 /* Get RES kernel buffer base phys address into %g7. */
246 ldx [%g3 + TRAP_PER_CPU_NONRESUM_KBUF_PA], %g7
248 /* If the first word is non-zero, queue is full. */
249 ldxa [%g7 + %g2] ASI_PHYS_USE_EC, %g1
250 brnz,pn %g1, sun4v_nonres_mondo_queue_full
253 lduw [%g3 + TRAP_PER_CPU_NONRESUM_QMASK], %g4
255 /* Remember this entry's offset in %g1. */
258 /* Copy 64-byte queue entry into kernel buffer. */
259 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
260 stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
262 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
263 stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
265 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
266 stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
268 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
269 stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
271 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
272 stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
274 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
275 stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
277 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
278 stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
280 ldxa [%g5 + %g2] ASI_PHYS_USE_EC, %g3
281 stxa %g3, [%g7 + %g2] ASI_PHYS_USE_EC
284 /* Update queue head pointer. */
287 mov INTRQ_NONRESUM_MONDO_HEAD, %g4
288 stxa %g2, [%g4] ASI_QUEUE
291 /* Disable interrupts and save register state so we can call
292 * C code. The etrap handling will leave %g4 in %l4 for us
298 ba,pt %xcc, etrap_irq
300 #ifdef CONFIG_TRACE_IRQFLAGS
301 call trace_hardirqs_off
305 add %sp, PTREGS_OFF, %o0
306 call sun4v_nonresum_error
309 /* Return from trap. */
310 ba,pt %xcc, rtrap_irq
313 sun4v_nonres_mondo_queue_empty:
316 sun4v_nonres_mondo_queue_full:
317 /* The queue is full, consolidate our damage by setting
318 * the head equal to the tail. We'll just trap again otherwise.
319 * Call C code to log the event.
321 mov INTRQ_NONRESUM_MONDO_HEAD, %g2
322 stxa %g4, [%g2] ASI_QUEUE
327 ba,pt %xcc, etrap_irq
329 #ifdef CONFIG_TRACE_IRQFLAGS
330 call trace_hardirqs_off
333 call sun4v_nonresum_overflow
334 add %sp, PTREGS_OFF, %o0
336 ba,pt %xcc, rtrap_irq