1 /* irq.c: UltraSparc IRQ handling/init/registry.
3 * Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
8 #include <linux/module.h>
9 #include <linux/sched.h>
10 #include <linux/ptrace.h>
11 #include <linux/errno.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/signal.h>
15 #include <linux/interrupt.h>
16 #include <linux/slab.h>
17 #include <linux/random.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/proc_fs.h>
21 #include <linux/seq_file.h>
22 #include <linux/bootmem.h>
23 #include <linux/irq.h>
24 #include <linux/msi.h>
26 #include <asm/ptrace.h>
27 #include <asm/processor.h>
28 #include <asm/atomic.h>
29 #include <asm/system.h>
33 #include <asm/iommu.h>
35 #include <asm/oplib.h>
37 #include <asm/timer.h>
39 #include <asm/starfire.h>
40 #include <asm/uaccess.h>
41 #include <asm/cache.h>
42 #include <asm/cpudata.h>
43 #include <asm/auxio.h>
45 #include <asm/hypervisor.h>
47 /* UPA nodes send interrupt packet to UltraSparc with first data reg
48 * value low 5 (7 on Starfire) bits holding the IRQ identifier being
49 * delivered. We must translate this into a non-vector IRQ so we can
50 * set the softint on this cpu.
52 * To make processing these packets efficient and race free we use
53 * an array of irq buckets below. The interrupt vector handler in
54 * entry.S feeds incoming packets into per-cpu pil-indexed lists.
55 * The IVEC handler does not need to act atomically, the PIL dispatch
56 * code uses CAS to get an atomic snapshot of the list and clear it
59 * If you make changes to ino_bucket, please update hand coded assembler
60 * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S
63 /* Next handler in per-CPU IRQ worklist. We know that
64 * bucket pointers have the high 32-bits clear, so to
65 * save space we only store the bits we need.
67 /*0x00*/unsigned int irq_chain;
69 /* Virtual interrupt number assigned to this INO. */
70 /*0x04*/unsigned int virt_irq;
73 #define NUM_IVECS (IMAP_INR + 1)
74 struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
76 #define __irq_ino(irq) \
77 (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
78 #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
79 #define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
81 /* This has to be in the main kernel image, it cannot be
82 * turned into per-cpu data. The reason is that the main
83 * kernel image is locked into the TLB and this structure
84 * is accessed from the vectored interrupt trap handler. If
85 * access to this structure takes a TLB miss it could cause
86 * the 5-level sparc v9 trap stack to overflow.
88 #define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist)
92 unsigned int dev_handle;
94 } virt_to_real_irq_table[NR_IRQS];
96 static unsigned char virt_irq_alloc(unsigned int real_irq)
100 BUILD_BUG_ON(NR_IRQS >= 256);
102 for (ent = 1; ent < NR_IRQS; ent++) {
103 if (!virt_to_real_irq_table[ent].irq)
106 if (ent >= NR_IRQS) {
107 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
111 virt_to_real_irq_table[ent].irq = real_irq;
116 #ifdef CONFIG_PCI_MSI
117 static void virt_irq_free(unsigned int virt_irq)
119 unsigned int real_irq;
121 if (virt_irq >= NR_IRQS)
124 real_irq = virt_to_real_irq_table[virt_irq].irq;
125 virt_to_real_irq_table[virt_irq].irq = 0;
127 __bucket(real_irq)->virt_irq = 0;
131 static unsigned int virt_to_real_irq(unsigned char virt_irq)
133 return virt_to_real_irq_table[virt_irq].irq;
137 * /proc/interrupts printing:
140 int show_interrupts(struct seq_file *p, void *v)
142 int i = *(loff_t *) v, j;
143 struct irqaction * action;
148 for_each_online_cpu(j)
149 seq_printf(p, "CPU%d ",j);
154 spin_lock_irqsave(&irq_desc[i].lock, flags);
155 action = irq_desc[i].action;
158 seq_printf(p, "%3d: ",i);
160 seq_printf(p, "%10u ", kstat_irqs(i));
162 for_each_online_cpu(j)
163 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
165 seq_printf(p, " %9s", irq_desc[i].chip->typename);
166 seq_printf(p, " %s", action->name);
168 for (action=action->next; action; action = action->next)
169 seq_printf(p, ", %s", action->name);
173 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
178 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
182 if (this_is_starfire) {
183 tid = starfire_translate(imap, cpuid);
184 tid <<= IMAP_TID_SHIFT;
187 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
190 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
191 if ((ver >> 32UL) == __JALAPENO_ID ||
192 (ver >> 32UL) == __SERRANO_ID) {
193 tid = cpuid << IMAP_TID_SHIFT;
194 tid &= IMAP_TID_JBUS;
196 unsigned int a = cpuid & 0x1f;
197 unsigned int n = (cpuid >> 5) & 0x1f;
199 tid = ((a << IMAP_AID_SHIFT) |
200 (n << IMAP_NID_SHIFT));
201 tid &= (IMAP_AID_SAFARI |
205 tid = cpuid << IMAP_TID_SHIFT;
213 struct irq_handler_data {
217 void (*pre_handler)(unsigned int, void *, void *);
218 void *pre_handler_arg1;
219 void *pre_handler_arg2;
224 void sparc64_set_msi(unsigned int virt_irq, u32 msi)
226 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
232 u32 sparc64_get_msi(unsigned int virt_irq)
234 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
241 static inline struct ino_bucket *virt_irq_to_bucket(unsigned int virt_irq)
243 unsigned int real_irq = virt_to_real_irq(virt_irq);
244 struct ino_bucket *bucket = NULL;
246 if (likely(real_irq))
247 bucket = __bucket(real_irq);
253 static int irq_choose_cpu(unsigned int virt_irq)
255 cpumask_t mask = irq_desc[virt_irq].affinity;
258 if (cpus_equal(mask, CPU_MASK_ALL)) {
259 static int irq_rover;
260 static DEFINE_SPINLOCK(irq_rover_lock);
263 /* Round-robin distribution... */
265 spin_lock_irqsave(&irq_rover_lock, flags);
267 while (!cpu_online(irq_rover)) {
268 if (++irq_rover >= NR_CPUS)
273 if (++irq_rover >= NR_CPUS)
275 } while (!cpu_online(irq_rover));
277 spin_unlock_irqrestore(&irq_rover_lock, flags);
281 cpus_and(tmp, cpu_online_map, mask);
286 cpuid = first_cpu(tmp);
292 static int irq_choose_cpu(unsigned int virt_irq)
294 return real_hard_smp_processor_id();
298 static void sun4u_irq_enable(unsigned int virt_irq)
300 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
303 unsigned long cpuid, imap, val;
306 cpuid = irq_choose_cpu(virt_irq);
309 tid = sun4u_compute_tid(imap, cpuid);
311 val = upa_readq(imap);
312 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
313 IMAP_AID_SAFARI | IMAP_NID_SAFARI);
314 val |= tid | IMAP_VALID;
315 upa_writeq(val, imap);
319 static void sun4u_set_affinity(unsigned int virt_irq, cpumask_t mask)
321 sun4u_irq_enable(virt_irq);
324 static void sun4u_irq_disable(unsigned int virt_irq)
326 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
329 unsigned long imap = data->imap;
330 unsigned long tmp = upa_readq(imap);
333 upa_writeq(tmp, imap);
337 static void sun4u_irq_end(unsigned int virt_irq)
339 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
340 struct irq_desc *desc = irq_desc + virt_irq;
342 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
346 upa_writeq(ICLR_IDLE, data->iclr);
349 static void sun4v_irq_enable(unsigned int virt_irq)
351 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
352 unsigned int ino = bucket - &ivector_table[0];
354 if (likely(bucket)) {
358 cpuid = irq_choose_cpu(virt_irq);
360 err = sun4v_intr_settarget(ino, cpuid);
362 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
363 "err(%d)\n", ino, cpuid, err);
364 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
366 printk(KERN_ERR "sun4v_intr_setstate(%x): "
367 "err(%d)\n", ino, err);
368 err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
370 printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
375 static void sun4v_set_affinity(unsigned int virt_irq, cpumask_t mask)
377 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
378 unsigned int ino = bucket - &ivector_table[0];
380 if (likely(bucket)) {
384 cpuid = irq_choose_cpu(virt_irq);
386 err = sun4v_intr_settarget(ino, cpuid);
388 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
389 "err(%d)\n", ino, cpuid, err);
393 static void sun4v_irq_disable(unsigned int virt_irq)
395 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
396 unsigned int ino = bucket - &ivector_table[0];
398 if (likely(bucket)) {
401 err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
403 printk(KERN_ERR "sun4v_intr_setenabled(%x): "
404 "err(%d)\n", ino, err);
408 #ifdef CONFIG_PCI_MSI
409 static void sun4u_msi_enable(unsigned int virt_irq)
411 sun4u_irq_enable(virt_irq);
412 unmask_msi_irq(virt_irq);
415 static void sun4u_msi_disable(unsigned int virt_irq)
417 mask_msi_irq(virt_irq);
418 sun4u_irq_disable(virt_irq);
421 static void sun4v_msi_enable(unsigned int virt_irq)
423 sun4v_irq_enable(virt_irq);
424 unmask_msi_irq(virt_irq);
427 static void sun4v_msi_disable(unsigned int virt_irq)
429 mask_msi_irq(virt_irq);
430 sun4v_irq_disable(virt_irq);
434 static void sun4v_irq_end(unsigned int virt_irq)
436 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
437 unsigned int ino = bucket - &ivector_table[0];
438 struct irq_desc *desc = irq_desc + virt_irq;
440 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
443 if (likely(bucket)) {
446 err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
448 printk(KERN_ERR "sun4v_intr_setstate(%x): "
449 "err(%d)\n", ino, err);
453 static void sun4v_virq_enable(unsigned int virt_irq)
455 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
457 if (likely(bucket)) {
458 unsigned long cpuid, dev_handle, dev_ino;
461 cpuid = irq_choose_cpu(virt_irq);
463 dev_handle = virt_to_real_irq_table[virt_irq].dev_handle;
464 dev_ino = virt_to_real_irq_table[virt_irq].dev_ino;
466 err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
468 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
470 dev_handle, dev_ino, cpuid, err);
471 err = sun4v_vintr_set_state(dev_handle, dev_ino,
474 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
475 "HV_INTR_STATE_IDLE): err(%d)\n",
476 dev_handle, dev_ino, err);
477 err = sun4v_vintr_set_valid(dev_handle, dev_ino,
480 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
481 "HV_INTR_ENABLED): err(%d)\n",
482 dev_handle, dev_ino, err);
486 static void sun4v_virt_set_affinity(unsigned int virt_irq, cpumask_t mask)
488 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
490 if (likely(bucket)) {
491 unsigned long cpuid, dev_handle, dev_ino;
494 cpuid = irq_choose_cpu(virt_irq);
496 dev_handle = virt_to_real_irq_table[virt_irq].dev_handle;
497 dev_ino = virt_to_real_irq_table[virt_irq].dev_ino;
499 err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
501 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
503 dev_handle, dev_ino, cpuid, err);
507 static void sun4v_virq_disable(unsigned int virt_irq)
509 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
511 if (likely(bucket)) {
512 unsigned long dev_handle, dev_ino;
515 dev_handle = virt_to_real_irq_table[virt_irq].dev_handle;
516 dev_ino = virt_to_real_irq_table[virt_irq].dev_ino;
518 err = sun4v_vintr_set_valid(dev_handle, dev_ino,
521 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
522 "HV_INTR_DISABLED): err(%d)\n",
523 dev_handle, dev_ino, err);
527 static void sun4v_virq_end(unsigned int virt_irq)
529 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
530 struct irq_desc *desc = irq_desc + virt_irq;
532 if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
535 if (likely(bucket)) {
536 unsigned long dev_handle, dev_ino;
539 dev_handle = virt_to_real_irq_table[virt_irq].dev_handle;
540 dev_ino = virt_to_real_irq_table[virt_irq].dev_ino;
542 err = sun4v_vintr_set_state(dev_handle, dev_ino,
545 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
546 "HV_INTR_STATE_IDLE): err(%d)\n",
547 dev_handle, dev_ino, err);
551 static void run_pre_handler(unsigned int virt_irq)
553 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
554 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
556 if (likely(data->pre_handler)) {
557 data->pre_handler(__irq_ino(__irq(bucket)),
558 data->pre_handler_arg1,
559 data->pre_handler_arg2);
563 static struct irq_chip sun4u_irq = {
565 .enable = sun4u_irq_enable,
566 .disable = sun4u_irq_disable,
567 .end = sun4u_irq_end,
568 .set_affinity = sun4u_set_affinity,
571 static struct irq_chip sun4u_irq_ack = {
572 .typename = "sun4u+ack",
573 .enable = sun4u_irq_enable,
574 .disable = sun4u_irq_disable,
575 .ack = run_pre_handler,
576 .end = sun4u_irq_end,
577 .set_affinity = sun4u_set_affinity,
580 static struct irq_chip sun4v_irq = {
582 .enable = sun4v_irq_enable,
583 .disable = sun4v_irq_disable,
584 .end = sun4v_irq_end,
585 .set_affinity = sun4v_set_affinity,
588 static struct irq_chip sun4v_irq_ack = {
589 .typename = "sun4v+ack",
590 .enable = sun4v_irq_enable,
591 .disable = sun4v_irq_disable,
592 .ack = run_pre_handler,
593 .end = sun4v_irq_end,
594 .set_affinity = sun4v_set_affinity,
597 #ifdef CONFIG_PCI_MSI
598 static struct irq_chip sun4u_msi = {
599 .typename = "sun4u+msi",
600 .mask = mask_msi_irq,
601 .unmask = unmask_msi_irq,
602 .enable = sun4u_msi_enable,
603 .disable = sun4u_msi_disable,
604 .ack = run_pre_handler,
605 .end = sun4u_irq_end,
606 .set_affinity = sun4u_set_affinity,
609 static struct irq_chip sun4v_msi = {
610 .typename = "sun4v+msi",
611 .mask = mask_msi_irq,
612 .unmask = unmask_msi_irq,
613 .enable = sun4v_msi_enable,
614 .disable = sun4v_msi_disable,
615 .ack = run_pre_handler,
616 .end = sun4v_irq_end,
617 .set_affinity = sun4v_set_affinity,
621 static struct irq_chip sun4v_virq = {
622 .typename = "vsun4v",
623 .enable = sun4v_virq_enable,
624 .disable = sun4v_virq_disable,
625 .end = sun4v_virq_end,
626 .set_affinity = sun4v_virt_set_affinity,
629 static struct irq_chip sun4v_virq_ack = {
630 .typename = "vsun4v+ack",
631 .enable = sun4v_virq_enable,
632 .disable = sun4v_virq_disable,
633 .ack = run_pre_handler,
634 .end = sun4v_virq_end,
635 .set_affinity = sun4v_virt_set_affinity,
638 void irq_install_pre_handler(int virt_irq,
639 void (*func)(unsigned int, void *, void *),
640 void *arg1, void *arg2)
642 struct irq_handler_data *data = get_irq_chip_data(virt_irq);
643 struct irq_chip *chip;
645 data->pre_handler = func;
646 data->pre_handler_arg1 = arg1;
647 data->pre_handler_arg2 = arg2;
649 chip = get_irq_chip(virt_irq);
650 if (chip == &sun4u_irq_ack ||
651 chip == &sun4v_irq_ack ||
652 chip == &sun4v_virq_ack
653 #ifdef CONFIG_PCI_MSI
654 || chip == &sun4u_msi
655 || chip == &sun4v_msi
660 chip = (chip == &sun4u_irq ?
662 (chip == &sun4v_irq ?
663 &sun4v_irq_ack : &sun4v_virq_ack));
664 set_irq_chip(virt_irq, chip);
667 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
669 struct ino_bucket *bucket;
670 struct irq_handler_data *data;
673 BUG_ON(tlb_type == hypervisor);
675 ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
676 bucket = &ivector_table[ino];
677 if (!bucket->virt_irq) {
678 bucket->virt_irq = virt_irq_alloc(__irq(bucket));
679 set_irq_chip(bucket->virt_irq, &sun4u_irq);
682 data = get_irq_chip_data(bucket->virt_irq);
686 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
687 if (unlikely(!data)) {
688 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
691 set_irq_chip_data(bucket->virt_irq, data);
697 return bucket->virt_irq;
700 static unsigned int sun4v_build_common(unsigned long sysino,
701 struct irq_chip *chip)
703 struct ino_bucket *bucket;
704 struct irq_handler_data *data;
706 BUG_ON(tlb_type != hypervisor);
708 bucket = &ivector_table[sysino];
709 if (!bucket->virt_irq) {
710 bucket->virt_irq = virt_irq_alloc(__irq(bucket));
711 set_irq_chip(bucket->virt_irq, chip);
714 data = get_irq_chip_data(bucket->virt_irq);
718 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
719 if (unlikely(!data)) {
720 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
723 set_irq_chip_data(bucket->virt_irq, data);
725 /* Catch accidental accesses to these things. IMAP/ICLR handling
726 * is done by hypervisor calls on sun4v platforms, not by direct
733 return bucket->virt_irq;
736 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
738 unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
740 return sun4v_build_common(sysino, &sun4v_irq);
743 unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
745 unsigned long sysino, hv_err;
748 BUG_ON(devhandle & devino);
750 sysino = devhandle | devino;
751 BUG_ON(sysino & ~(IMAP_IGN | IMAP_INO));
753 hv_err = sun4v_vintr_set_cookie(devhandle, devino, sysino);
755 prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] "
756 "err=%lu\n", devhandle, devino, hv_err);
760 virq = sun4v_build_common(sysino, &sun4v_virq);
762 virt_to_real_irq_table[virq].dev_handle = devhandle;
763 virt_to_real_irq_table[virq].dev_ino = devino;
768 #ifdef CONFIG_PCI_MSI
769 unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p,
770 unsigned int msi_start, unsigned int msi_end)
772 struct ino_bucket *bucket;
773 struct irq_handler_data *data;
774 unsigned long sysino;
777 BUG_ON(tlb_type != hypervisor);
779 /* Find a free devino in the given range. */
780 for (devino = msi_start; devino < msi_end; devino++) {
781 sysino = sun4v_devino_to_sysino(devhandle, devino);
782 bucket = &ivector_table[sysino];
783 if (!bucket->virt_irq)
786 if (devino >= msi_end)
789 sysino = sun4v_devino_to_sysino(devhandle, devino);
790 bucket = &ivector_table[sysino];
791 bucket->virt_irq = virt_irq_alloc(__irq(bucket));
792 *virt_irq_p = bucket->virt_irq;
793 set_irq_chip(bucket->virt_irq, &sun4v_msi);
795 data = get_irq_chip_data(bucket->virt_irq);
799 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
800 if (unlikely(!data)) {
801 virt_irq_free(*virt_irq_p);
804 set_irq_chip_data(bucket->virt_irq, data);
812 void sun4v_destroy_msi(unsigned int virt_irq)
814 virt_irq_free(virt_irq);
817 unsigned int sun4u_build_msi(u32 portid, unsigned int *virt_irq_p,
818 unsigned int msi_start, unsigned int msi_end,
819 unsigned long imap_base, unsigned long iclr_base)
821 struct ino_bucket *bucket;
822 struct irq_handler_data *data;
823 unsigned long sysino;
826 /* Find a free devino in the given range. */
827 for (devino = msi_start; devino < msi_end; devino++) {
828 sysino = (portid << 6) | devino;
829 bucket = &ivector_table[sysino];
830 if (!bucket->virt_irq)
833 if (devino >= msi_end)
836 sysino = (portid << 6) | devino;
837 bucket = &ivector_table[sysino];
838 bucket->virt_irq = virt_irq_alloc(__irq(bucket));
839 *virt_irq_p = bucket->virt_irq;
840 set_irq_chip(bucket->virt_irq, &sun4u_msi);
842 data = get_irq_chip_data(bucket->virt_irq);
846 data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
847 if (unlikely(!data)) {
848 virt_irq_free(*virt_irq_p);
851 set_irq_chip_data(bucket->virt_irq, data);
853 data->imap = (imap_base + (devino * 0x8UL));
854 data->iclr = (iclr_base + (devino * 0x8UL));
859 void sun4u_destroy_msi(unsigned int virt_irq)
861 virt_irq_free(virt_irq);
865 void ack_bad_irq(unsigned int virt_irq)
867 struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq);
868 unsigned int ino = 0xdeadbeef;
871 ino = bucket - &ivector_table[0];
873 printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n",
877 void handler_irq(int irq, struct pt_regs *regs)
879 struct ino_bucket *bucket;
880 struct pt_regs *old_regs;
882 clear_softint(1 << irq);
884 old_regs = set_irq_regs(regs);
888 bucket = __bucket(xchg32(irq_work(smp_processor_id()), 0));
890 struct ino_bucket *next = __bucket(bucket->irq_chain);
892 bucket->irq_chain = 0;
893 __do_IRQ(bucket->virt_irq);
899 set_irq_regs(old_regs);
902 #ifdef CONFIG_HOTPLUG_CPU
903 void fixup_irqs(void)
907 for (irq = 0; irq < NR_IRQS; irq++) {
910 spin_lock_irqsave(&irq_desc[irq].lock, flags);
911 if (irq_desc[irq].action &&
912 !(irq_desc[irq].status & IRQ_PER_CPU)) {
913 if (irq_desc[irq].chip->set_affinity)
914 irq_desc[irq].chip->set_affinity(irq,
915 irq_desc[irq].affinity);
917 spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
929 static struct sun5_timer *prom_timers;
930 static u64 prom_limit0, prom_limit1;
932 static void map_prom_timers(void)
934 struct device_node *dp;
935 const unsigned int *addr;
937 /* PROM timer node hangs out in the top level of device siblings... */
938 dp = of_find_node_by_path("/");
941 if (!strcmp(dp->name, "counter-timer"))
946 /* Assume if node is not present, PROM uses different tick mechanism
947 * which we should not care about.
950 prom_timers = (struct sun5_timer *) 0;
954 /* If PROM is really using this, it must be mapped by him. */
955 addr = of_get_property(dp, "address", NULL);
957 prom_printf("PROM does not have timer mapped, trying to continue.\n");
958 prom_timers = (struct sun5_timer *) 0;
961 prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
964 static void kill_prom_timer(void)
969 /* Save them away for later. */
970 prom_limit0 = prom_timers->limit0;
971 prom_limit1 = prom_timers->limit1;
973 /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
974 * We turn both off here just to be paranoid.
976 prom_timers->limit0 = 0;
977 prom_timers->limit1 = 0;
979 /* Wheee, eat the interrupt packet too... */
980 __asm__ __volatile__(
982 " ldxa [%%g0] %0, %%g1\n"
983 " ldxa [%%g2] %1, %%g1\n"
984 " stxa %%g0, [%%g0] %0\n"
987 : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
991 void init_irqwork_curcpu(void)
993 int cpu = hard_smp_processor_id();
995 trap_block[cpu].irq_worklist = 0;
998 /* Please be very careful with register_one_mondo() and
999 * sun4v_register_mondo_queues().
1001 * On SMP this gets invoked from the CPU trampoline before
1002 * the cpu has fully taken over the trap table from OBP,
1003 * and it's kernel stack + %g6 thread register state is
1004 * not fully cooked yet.
1006 * Therefore you cannot make any OBP calls, not even prom_printf,
1007 * from these two routines.
1009 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask)
1011 unsigned long num_entries = (qmask + 1) / 64;
1012 unsigned long status;
1014 status = sun4v_cpu_qconf(type, paddr, num_entries);
1015 if (status != HV_EOK) {
1016 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
1017 "err %lu\n", type, paddr, num_entries, status);
1022 void __cpuinit sun4v_register_mondo_queues(int this_cpu)
1024 struct trap_per_cpu *tb = &trap_block[this_cpu];
1026 register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
1027 tb->cpu_mondo_qmask);
1028 register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
1029 tb->dev_mondo_qmask);
1030 register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
1032 register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
1033 tb->nonresum_qmask);
1036 static void __init alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask)
1038 unsigned long size = PAGE_ALIGN(qmask + 1);
1039 void *p = __alloc_bootmem_low(size, size, 0);
1041 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
1048 static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask)
1050 unsigned long size = PAGE_ALIGN(qmask + 1);
1051 void *p = __alloc_bootmem_low(size, size, 0);
1054 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
1061 static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
1066 BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
1068 page = alloc_bootmem_low_pages(PAGE_SIZE);
1070 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
1074 tb->cpu_mondo_block_pa = __pa(page);
1075 tb->cpu_list_pa = __pa(page + 64);
1079 /* Allocate mondo and error queues for all possible cpus. */
1080 static void __init sun4v_init_mondo_queues(void)
1084 for_each_possible_cpu(cpu) {
1085 struct trap_per_cpu *tb = &trap_block[cpu];
1087 alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
1088 alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
1089 alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask);
1090 alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask);
1091 alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
1092 alloc_one_kbuf(&tb->nonresum_kernel_buf_pa,
1093 tb->nonresum_qmask);
1095 init_cpu_send_mondo_info(tb);
1098 /* Load up the boot cpu's entries. */
1099 sun4v_register_mondo_queues(hard_smp_processor_id());
1102 static struct irqaction timer_irq_action = {
1106 /* Only invoked on boot processor. */
1107 void __init init_IRQ(void)
1111 memset(&ivector_table[0], 0, sizeof(ivector_table));
1113 if (tlb_type == hypervisor)
1114 sun4v_init_mondo_queues();
1116 /* We need to clear any IRQ's pending in the soft interrupt
1117 * registers, a spurious one could be left around from the
1118 * PROM timer which we just disabled.
1120 clear_softint(get_softint());
1122 /* Now that ivector table is initialized, it is safe
1123 * to receive IRQ vector traps. We will normally take
1124 * one or two right now, in case some device PROM used
1125 * to boot us wants to speak to us. We just ignore them.
1127 __asm__ __volatile__("rdpr %%pstate, %%g1\n\t"
1128 "or %%g1, %0, %%g1\n\t"
1129 "wrpr %%g1, 0x0, %%pstate"
1134 irq_desc[0].action = &timer_irq_action;