arch/sparc/net/bpf_jit_comp.c

   1 #include <linux/moduleloader.h>
   2 #include <linux/workqueue.h>
   3 #include <linux/netdevice.h>
   4 #include <linux/filter.h>
   5 #include <linux/cache.h>
   6 #include <linux/if_vlan.h>
   7
   8 #include <asm/cacheflush.h>
   9 #include <asm/ptrace.h>
  10
  11 #include "bpf_jit.h"
  12
  13 int bpf_jit_enable __read_mostly;
  14
  15 static inline bool is_simm13(unsigned int value)
  16 {
  17         return value + 0x1000 < 0x2000;
  18 }
  19
  20 static void bpf_flush_icache(void *start_, void *end_)
  21 {
  22 #ifdef CONFIG_SPARC64
  23         /* Cheetah's I-cache is fully coherent.  */
  24         if (tlb_type == spitfire) {
  25                 unsigned long start = (unsigned long) start_;
  26                 unsigned long end = (unsigned long) end_;
  27
  28                 start &= ~7UL;
  29                 end = (end + 7UL) & ~7UL;
  30                 while (start < end) {
  31                         flushi(start);
  32                         start += 32;
  33                 }
  34         }
  35 #endif
  36 }
  37
  38 #define SEEN_DATAREF 1 /* might call external helpers */
  39 #define SEEN_XREG    2 /* ebx is used */
  40 #define SEEN_MEM     4 /* use mem[] for temporary storage */
  41
  42 #define S13(X)          ((X) & 0x1fff)
  43 #define IMMED           0x00002000
  44 #define RD(X)           ((X) << 25)
  45 #define RS1(X)          ((X) << 14)
  46 #define RS2(X)          ((X))
  47 #define OP(X)           ((X) << 30)
  48 #define OP2(X)          ((X) << 22)
  49 #define OP3(X)          ((X) << 19)
  50 #define COND(X)         ((X) << 25)
  51 #define F1(X)           OP(X)
  52 #define F2(X, Y)        (OP(X) | OP2(Y))
  53 #define F3(X, Y)        (OP(X) | OP3(Y))
  54
  55 #define CONDN           COND(0x0)
  56 #define CONDE           COND(0x1)
  57 #define CONDLE          COND(0x2)
  58 #define CONDL           COND(0x3)
  59 #define CONDLEU         COND(0x4)
  60 #define CONDCS          COND(0x5)
  61 #define CONDNEG         COND(0x6)
  62 #define CONDVC          COND(0x7)
  63 #define CONDA           COND(0x8)
  64 #define CONDNE          COND(0x9)
  65 #define CONDG           COND(0xa)
  66 #define CONDGE          COND(0xb)
  67 #define CONDGU          COND(0xc)
  68 #define CONDCC          COND(0xd)
  69 #define CONDPOS         COND(0xe)
  70 #define CONDVS          COND(0xf)
  71
  72 #define CONDGEU         CONDCC
  73 #define CONDLU          CONDCS
  74
  75 #define WDISP22(X)      (((X) >> 2) & 0x3fffff)
  76
  77 #define BA              (F2(0, 2) | CONDA)
  78 #define BGU             (F2(0, 2) | CONDGU)
  79 #define BLEU            (F2(0, 2) | CONDLEU)
  80 #define BGEU            (F2(0, 2) | CONDGEU)
  81 #define BLU             (F2(0, 2) | CONDLU)
  82 #define BE              (F2(0, 2) | CONDE)
  83 #define BNE             (F2(0, 2) | CONDNE)
  84
  85 #ifdef CONFIG_SPARC64
  86 #define BE_PTR          (F2(0, 1) | CONDE | (2 << 20))
  87 #else
  88 #define BE_PTR          BE
  89 #endif
  90
  91 #define SETHI(K, REG)   \
  92         (F2(0, 0x4) | RD(REG) | (((K) >> 10) & 0x3fffff))
  93 #define OR_LO(K, REG)   \
  94         (F3(2, 0x02) | IMMED | RS1(REG) | ((K) & 0x3ff) | RD(REG))
  95
  96 #define ADD             F3(2, 0x00)
  97 #define AND             F3(2, 0x01)
  98 #define ANDCC           F3(2, 0x11)
  99 #define OR              F3(2, 0x02)
 100 #define XOR             F3(2, 0x03)
 101 #define SUB             F3(2, 0x04)
 102 #define SUBCC           F3(2, 0x14)
 103 #define MUL             F3(2, 0x0a)     /* umul */
 104 #define DIV             F3(2, 0x0e)     /* udiv */
 105 #define SLL             F3(2, 0x25)
 106 #define SRL             F3(2, 0x26)
 107 #define JMPL            F3(2, 0x38)
 108 #define CALL            F1(1)
 109 #define BR              F2(0, 0x01)
 110 #define RD_Y            F3(2, 0x28)
 111 #define WR_Y            F3(2, 0x30)
 112
 113 #define LD32            F3(3, 0x00)
 114 #define LD8             F3(3, 0x01)
 115 #define LD16            F3(3, 0x02)
 116 #define LD64            F3(3, 0x0b)
 117 #define ST32            F3(3, 0x04)
 118
 119 #ifdef CONFIG_SPARC64
 120 #define LDPTR           LD64
 121 #define BASE_STACKFRAME 176
 122 #else
 123 #define LDPTR           LD32
 124 #define BASE_STACKFRAME 96
 125 #endif
 126
 127 #define LD32I           (LD32 | IMMED)
 128 #define LD8I            (LD8 | IMMED)
 129 #define LD16I           (LD16 | IMMED)
 130 #define LD64I           (LD64 | IMMED)
 131 #define LDPTRI          (LDPTR | IMMED)
 132 #define ST32I           (ST32 | IMMED)
 133
 134 #define emit_nop()              \
 135 do {                            \
 136         *prog++ = SETHI(0, G0); \
 137 } while (0)
 138
 139 #define emit_neg()                                      \
 140 do {    /* sub %g0, r_A, r_A */                         \
 141         *prog++ = SUB | RS1(G0) | RS2(r_A) | RD(r_A);   \
 142 } while (0)
 143
 144 #define emit_reg_move(FROM, TO)                         \
 145 do {    /* or %g0, FROM, TO */                          \
 146         *prog++ = OR | RS1(G0) | RS2(FROM) | RD(TO);    \
 147 } while (0)
 148
 149 #define emit_clear(REG)                                 \
 150 do {    /* or %g0, %g0, REG */                          \
 151         *prog++ = OR | RS1(G0) | RS2(G0) | RD(REG);     \
 152 } while (0)
 153
 154 #define emit_set_const(K, REG)                                  \
 155 do {    /* sethi %hi(K), REG */                                 \
 156         *prog++ = SETHI(K, REG);                                \
 157         /* or REG, %lo(K), REG */                               \
 158         *prog++ = OR_LO(K, REG);                                \
 159 } while (0)
 160
 161         /* Emit
 162          *
 163          *      OP      r_A, r_X, r_A
 164          */
 165 #define emit_alu_X(OPCODE)                                      \
 166 do {                                                            \
 167         seen |= SEEN_XREG;                                      \
 168         *prog++ = OPCODE | RS1(r_A) | RS2(r_X) | RD(r_A);       \
 169 } while (0)
 170
 171         /* Emit either:
 172          *
 173          *      OP      r_A, K, r_A
 174          *
 175          * or
 176          *
 177          *      sethi   %hi(K), r_TMP
 178          *      or      r_TMP, %lo(K), r_TMP
 179          *      OP      r_A, r_TMP, r_A
 180          *
 181          * depending upon whether K fits in a signed 13-bit
 182          * immediate instruction field.  Emit nothing if K
 183          * is zero.
 184          */
 185 #define emit_alu_K(OPCODE, K)                                   \
 186 do {                                                            \
 187         if (K) {                                                \
 188                 unsigned int _insn = OPCODE;                    \
 189                 _insn |= RS1(r_A) | RD(r_A);                    \
 190                 if (is_simm13(K)) {                             \
 191                         *prog++ = _insn | IMMED | S13(K);       \
 192                 } else {                                        \
 193                         emit_set_const(K, r_TMP);               \
 194                         *prog++ = _insn | RS2(r_TMP);           \
 195                 }                                               \
 196         }                                                       \
 197 } while (0)
 198
 199 #define emit_loadimm(K, DEST)                                           \
 200 do {                                                                    \
 201         if (is_simm13(K)) {                                             \
 202                 /* or %g0, K, DEST */                                   \
 203                 *prog++ = OR | IMMED | RS1(G0) | S13(K) | RD(DEST);     \
 204         } else {                                                        \
 205                 emit_set_const(K, DEST);                                \
 206         }                                                               \
 207 } while (0)
 208
 209 #define emit_loadptr(BASE, STRUCT, FIELD, DEST)                         \
 210 do {    unsigned int _off = offsetof(STRUCT, FIELD);                    \
 211         BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(void *));    \
 212         *prog++ = LDPTRI | RS1(BASE) | S13(_off) | RD(DEST);            \
 213 } while (0)
 214
 215 #define emit_load32(BASE, STRUCT, FIELD, DEST)                          \
 216 do {    unsigned int _off = offsetof(STRUCT, FIELD);                    \
 217         BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u32));       \
 218         *prog++ = LD32I | RS1(BASE) | S13(_off) | RD(DEST);             \
 219 } while (0)
 220
 221 #define emit_load16(BASE, STRUCT, FIELD, DEST)                          \
 222 do {    unsigned int _off = offsetof(STRUCT, FIELD);                    \
 223         BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u16));       \
 224         *prog++ = LD16I | RS1(BASE) | S13(_off) | RD(DEST);             \
 225 } while (0)
 226
 227 #define __emit_load8(BASE, STRUCT, FIELD, DEST)                         \
 228 do {    unsigned int _off = offsetof(STRUCT, FIELD);                    \
 229         *prog++ = LD8I | RS1(BASE) | S13(_off) | RD(DEST);              \
 230 } while (0)
 231
 232 #define emit_load8(BASE, STRUCT, FIELD, DEST)                           \
 233 do {    BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u8));        \
 234         __emit_load8(BASE, STRUCT, FIELD, DEST);                        \
 235 } while (0)
 236
 237 #define emit_ldmem(OFF, DEST)                                   \
 238 do {    *prog++ = LD32I | RS1(FP) | S13(-(OFF)) | RD(DEST);     \
 239 } while (0)
 240
 241 #define emit_stmem(OFF, SRC)                                    \
 242 do {    *prog++ = LD32I | RS1(FP) | S13(-(OFF)) | RD(SRC);      \
 243 } while (0)
 244
 245 #ifdef CONFIG_SMP
 246 #ifdef CONFIG_SPARC64
 247 #define emit_load_cpu(REG)                                              \
 248         emit_load16(G6, struct thread_info, cpu, REG)
 249 #else
 250 #define emit_load_cpu(REG)                                              \
 251         emit_load32(G6, struct thread_info, cpu, REG)
 252 #endif
 253 #else
 254 #define emit_load_cpu(REG)      emit_clear(REG)
 255 #endif
 256
 257 #define emit_skb_loadptr(FIELD, DEST) \
 258         emit_loadptr(r_SKB, struct sk_buff, FIELD, DEST)
 259 #define emit_skb_load32(FIELD, DEST) \
 260         emit_load32(r_SKB, struct sk_buff, FIELD, DEST)
 261 #define emit_skb_load16(FIELD, DEST) \
 262         emit_load16(r_SKB, struct sk_buff, FIELD, DEST)
 263 #define __emit_skb_load8(FIELD, DEST) \
 264         __emit_load8(r_SKB, struct sk_buff, FIELD, DEST)
 265 #define emit_skb_load8(FIELD, DEST) \
 266         emit_load8(r_SKB, struct sk_buff, FIELD, DEST)
 267
 268 #define emit_jmpl(BASE, IMM_OFF, LREG) \
 269         *prog++ = (JMPL | IMMED | RS1(BASE) | S13(IMM_OFF) | RD(LREG))
 270
 271 #define emit_call(FUNC)                                 \
 272 do {    void *_here = image + addrs[i] - 8;             \
 273         unsigned int _off = (void *)(FUNC) - _here;     \
 274         *prog++ = CALL | (((_off) >> 2) & 0x3fffffff);  \
 275         emit_nop();                                     \
 276 } while (0)
 277
 278 #define emit_branch(BR_OPC, DEST)                       \
 279 do {    unsigned int _here = addrs[i] - 8;              \
 280         *prog++ = BR_OPC | WDISP22((DEST) - _here);     \
 281 } while (0)
 282
 283 #define emit_branch_off(BR_OPC, OFF)                    \
 284 do {    *prog++ = BR_OPC | WDISP22(OFF);                \
 285 } while (0)
 286
 287 #define emit_jump(DEST)         emit_branch(BA, DEST)
 288
 289 #define emit_read_y(REG)        *prog++ = RD_Y | RD(REG)
 290 #define emit_write_y(REG)       *prog++ = WR_Y | IMMED | RS1(REG) | S13(0)
 291
 292 #define emit_cmp(R1, R2) \
 293         *prog++ = (SUBCC | RS1(R1) | RS2(R2) | RD(G0))
 294
 295 #define emit_cmpi(R1, IMM) \
 296         *prog++ = (SUBCC | IMMED | RS1(R1) | S13(IMM) | RD(G0));
 297
 298 #define emit_btst(R1, R2) \
 299         *prog++ = (ANDCC | RS1(R1) | RS2(R2) | RD(G0))
 300
 301 #define emit_btsti(R1, IMM) \
 302         *prog++ = (ANDCC | IMMED | RS1(R1) | S13(IMM) | RD(G0));
 303
 304 #define emit_sub(R1, R2, R3) \
 305         *prog++ = (SUB | RS1(R1) | RS2(R2) | RD(R3))
 306
 307 #define emit_subi(R1, IMM, R3) \
 308         *prog++ = (SUB | IMMED | RS1(R1) | S13(IMM) | RD(R3))
 309
 310 #define emit_add(R1, R2, R3) \
 311         *prog++ = (ADD | RS1(R1) | RS2(R2) | RD(R3))
 312
 313 #define emit_addi(R1, IMM, R3) \
 314         *prog++ = (ADD | IMMED | RS1(R1) | S13(IMM) | RD(R3))
 315
 316 #define emit_and(R1, R2, R3) \
 317         *prog++ = (AND | RS1(R1) | RS2(R2) | RD(R3))
 318
 319 #define emit_andi(R1, IMM, R3) \
 320         *prog++ = (AND | IMMED | RS1(R1) | S13(IMM) | RD(R3))
 321
 322 #define emit_alloc_stack(SZ) \
 323         *prog++ = (SUB | IMMED | RS1(SP) | S13(SZ) | RD(SP))
 324
 325 #define emit_release_stack(SZ) \
 326         *prog++ = (ADD | IMMED | RS1(SP) | S13(SZ) | RD(SP))
 327
 328 /* A note about branch offset calculations.  The addrs[] array,
 329  * indexed by BPF instruction, records the address after all the
 330  * sparc instructions emitted for that BPF instruction.
 331  *
 332  * The most common case is to emit a branch at the end of such
 333  * a code sequence.  So this would be two instructions, the
 334  * branch and it's delay slot.
 335  *
 336  * Therefore by default the branch emitters calculate the branch
 337  * offset field as:
 338  *
 339  *      destination - (addrs[i] - 8)
 340  *
 341  * This "addrs[i] - 8" is the address of the branch itself or
 342  * what "." would be in assembler notation.  The "8" part is
 343  * how we take into consideration the branch and it's delay
 344  * slot mentioned above.
 345  *
 346  * Sometimes we need to emit a branch earlier in the code
 347  * sequence.  And in these situations we adjust "destination"
 348  * to accomodate this difference.  For example, if we needed
 349  * to emit a branch (and it's delay slot) right before the
 350  * final instruction emitted for a BPF opcode, we'd use
 351  * "destination + 4" instead of just plain "destination" above.
 352  *
 353  * This is why you see all of these funny emit_branch() and
 354  * emit_jump() calls with adjusted offsets.
 355  */
 356
 357 void bpf_jit_compile(struct bpf_prog *fp)
 358 {
 359         unsigned int cleanup_addr, proglen, oldproglen = 0;
 360         u32 temp[8], *prog, *func, seen = 0, pass;
 361         const struct sock_filter *filter = fp->insns;
 362         int i, flen = fp->len, pc_ret0 = -1;
 363         unsigned int *addrs;
 364         void *image;
 365
 366         if (!bpf_jit_enable)
 367                 return;
 368
 369         addrs = kmalloc(flen * sizeof(*addrs), GFP_KERNEL);
 370         if (addrs == NULL)
 371                 return;
 372
 373         /* Before first pass, make a rough estimation of addrs[]
 374          * each bpf instruction is translated to less than 64 bytes
 375          */
 376         for (proglen = 0, i = 0; i < flen; i++) {
 377                 proglen += 64;
 378                 addrs[i] = proglen;
 379         }
 380         cleanup_addr = proglen; /* epilogue address */
 381         image = NULL;
 382         for (pass = 0; pass < 10; pass++) {
 383                 u8 seen_or_pass0 = (pass == 0) ? (SEEN_XREG | SEEN_DATAREF | SEEN_MEM) : seen;
 384
 385                 /* no prologue/epilogue for trivial filters (RET something) */
 386                 proglen = 0;
 387                 prog = temp;
 388
 389                 /* Prologue */
 390                 if (seen_or_pass0) {
 391                         if (seen_or_pass0 & SEEN_MEM) {
 392                                 unsigned int sz = BASE_STACKFRAME;
 393                                 sz += BPF_MEMWORDS * sizeof(u32);
 394                                 emit_alloc_stack(sz);
 395                         }
 396
 397                         /* Make sure we dont leek kernel memory. */
 398                         if (seen_or_pass0 & SEEN_XREG)
 399                                 emit_clear(r_X);
 400
 401                         /* If this filter needs to access skb data,
 402                          * load %o4 and %o5 with:
 403                          *  %o4 = skb->len - skb->data_len
 404                          *  %o5 = skb->data
 405                          * And also back up %o7 into r_saved_O7 so we can
 406                          * invoke the stubs using 'call'.
 407                          */
 408                         if (seen_or_pass0 & SEEN_DATAREF) {
 409                                 emit_load32(r_SKB, struct sk_buff, len, r_HEADLEN);
 410                                 emit_load32(r_SKB, struct sk_buff, data_len, r_TMP);
 411                                 emit_sub(r_HEADLEN, r_TMP, r_HEADLEN);
 412                                 emit_loadptr(r_SKB, struct sk_buff, data, r_SKB_DATA);
 413                         }
 414                 }
 415                 emit_reg_move(O7, r_saved_O7);
 416
 417                 switch (filter[0].code) {
 418                 case BPF_RET | BPF_K:
 419                 case BPF_LD | BPF_W | BPF_LEN:
 420                 case BPF_LD | BPF_W | BPF_ABS:
 421                 case BPF_LD | BPF_H | BPF_ABS:
 422                 case BPF_LD | BPF_B | BPF_ABS:
 423                         /* The first instruction sets the A register (or is
 424                          * a "RET 'constant'")
 425                          */
 426                         break;
 427                 default:
 428                         /* Make sure we dont leak kernel information to the
 429                          * user.
 430                          */
 431                         emit_clear(r_A); /* A = 0 */
 432                 }
 433
 434                 for (i = 0; i < flen; i++) {
 435                         unsigned int K = filter[i].k;
 436                         unsigned int t_offset;
 437                         unsigned int f_offset;
 438                         u32 t_op, f_op;
 439                         u16 code = bpf_anc_helper(&filter[i]);
 440                         int ilen;
 441
 442                         switch (code) {
 443                         case BPF_ALU | BPF_ADD | BPF_X: /* A += X; */
 444                                 emit_alu_X(ADD);
 445                                 break;
 446                         case BPF_ALU | BPF_ADD | BPF_K: /* A += K; */
 447                                 emit_alu_K(ADD, K);
 448                                 break;
 449                         case BPF_ALU | BPF_SUB | BPF_X: /* A -= X; */
 450                                 emit_alu_X(SUB);
 451                                 break;
 452                         case BPF_ALU | BPF_SUB | BPF_K: /* A -= K */
 453                                 emit_alu_K(SUB, K);
 454                                 break;
 455                         case BPF_ALU | BPF_AND | BPF_X: /* A &= X */
 456                                 emit_alu_X(AND);
 457                                 break;
 458                         case BPF_ALU | BPF_AND | BPF_K: /* A &= K */
 459                                 emit_alu_K(AND, K);
 460                                 break;
 461                         case BPF_ALU | BPF_OR | BPF_X:  /* A |= X */
 462                                 emit_alu_X(OR);
 463                                 break;
 464                         case BPF_ALU | BPF_OR | BPF_K:  /* A |= K */
 465                                 emit_alu_K(OR, K);
 466                                 break;
 467                         case BPF_ANC | SKF_AD_ALU_XOR_X: /* A ^= X; */
 468                         case BPF_ALU | BPF_XOR | BPF_X:
 469                                 emit_alu_X(XOR);
 470                                 break;
 471                         case BPF_ALU | BPF_XOR | BPF_K: /* A ^= K */
 472                                 emit_alu_K(XOR, K);
 473                                 break;
 474                         case BPF_ALU | BPF_LSH | BPF_X: /* A <<= X */
 475                                 emit_alu_X(SLL);
 476                                 break;
 477                         case BPF_ALU | BPF_LSH | BPF_K: /* A <<= K */
 478                                 emit_alu_K(SLL, K);
 479                                 break;
 480                         case BPF_ALU | BPF_RSH | BPF_X: /* A >>= X */
 481                                 emit_alu_X(SRL);
 482                                 break;
 483                         case BPF_ALU | BPF_RSH | BPF_K: /* A >>= K */
 484                                 emit_alu_K(SRL, K);
 485                                 break;
 486                         case BPF_ALU | BPF_MUL | BPF_X: /* A *= X; */
 487                                 emit_alu_X(MUL);
 488                                 break;
 489                         case BPF_ALU | BPF_MUL | BPF_K: /* A *= K */
 490                                 emit_alu_K(MUL, K);
 491                                 break;
 492                         case BPF_ALU | BPF_DIV | BPF_K: /* A /= K with K != 0*/
 493                                 if (K == 1)
 494                                         break;
 495                                 emit_write_y(G0);
 496 #ifdef CONFIG_SPARC32
 497                                 /* The Sparc v8 architecture requires
 498                                  * three instructions between a %y
 499                                  * register write and the first use.
 500                                  */
 501                                 emit_nop();
 502                                 emit_nop();
 503                                 emit_nop();
 504 #endif
 505                                 emit_alu_K(DIV, K);
 506                                 break;
 507                         case BPF_ALU | BPF_DIV | BPF_X: /* A /= X; */
 508                                 emit_cmpi(r_X, 0);
 509                                 if (pc_ret0 > 0) {
 510                                         t_offset = addrs[pc_ret0 - 1];
 511 #ifdef CONFIG_SPARC32
 512                                         emit_branch(BE, t_offset + 20);
 513 #else
 514                                         emit_branch(BE, t_offset + 8);
 515 #endif
 516                                         emit_nop(); /* delay slot */
 517                                 } else {
 518                                         emit_branch_off(BNE, 16);
 519                                         emit_nop();
 520 #ifdef CONFIG_SPARC32
 521                                         emit_jump(cleanup_addr + 20);
 522 #else
 523                                         emit_jump(cleanup_addr + 8);
 524 #endif
 525                                         emit_clear(r_A);
 526                                 }
 527                                 emit_write_y(G0);
 528 #ifdef CONFIG_SPARC32
 529                                 /* The Sparc v8 architecture requires
 530                                  * three instructions between a %y
 531                                  * register write and the first use.
 532                                  */
 533                                 emit_nop();
 534                                 emit_nop();
 535                                 emit_nop();
 536 #endif
 537                                 emit_alu_X(DIV);
 538                                 break;
 539                         case BPF_ALU | BPF_NEG:
 540                                 emit_neg();
 541                                 break;
 542                         case BPF_RET | BPF_K:
 543                                 if (!K) {
 544                                         if (pc_ret0 == -1)
 545                                                 pc_ret0 = i;
 546                                         emit_clear(r_A);
 547                                 } else {
 548                                         emit_loadimm(K, r_A);
 549                                 }
 550                                 /* Fallthrough */
 551                         case BPF_RET | BPF_A:
 552                                 if (seen_or_pass0) {
 553                                         if (i != flen - 1) {
 554                                                 emit_jump(cleanup_addr);
 555                                                 emit_nop();
 556                                                 break;
 557                                         }
 558                                         if (seen_or_pass0 & SEEN_MEM) {
 559                                                 unsigned int sz = BASE_STACKFRAME;
 560                                                 sz += BPF_MEMWORDS * sizeof(u32);
 561                                                 emit_release_stack(sz);
 562                                         }
 563                                 }
 564                                 /* jmpl %r_saved_O7 + 8, %g0 */
 565                                 emit_jmpl(r_saved_O7, 8, G0);
 566                                 emit_reg_move(r_A, O0); /* delay slot */
 567                                 break;
 568                         case BPF_MISC | BPF_TAX:
 569                                 seen |= SEEN_XREG;
 570                                 emit_reg_move(r_A, r_X);
 571                                 break;
 572                         case BPF_MISC | BPF_TXA:
 573                                 seen |= SEEN_XREG;
 574                                 emit_reg_move(r_X, r_A);
 575                                 break;
 576                         case BPF_ANC | SKF_AD_CPU:
 577                                 emit_load_cpu(r_A);
 578                                 break;
 579                         case BPF_ANC | SKF_AD_PROTOCOL:
 580                                 emit_skb_load16(protocol, r_A);
 581                                 break;
 582 #if 0
 583                                 /* GCC won't let us take the address of
 584                                  * a bit field even though we very much
 585                                  * know what we are doing here.
 586                                  */
 587                         case BPF_ANC | SKF_AD_PKTTYPE:
 588                                 __emit_skb_load8(pkt_type, r_A);
 589                                 emit_alu_K(SRL, 5);
 590                                 break;
 591 #endif
 592                         case BPF_ANC | SKF_AD_IFINDEX:
 593                                 emit_skb_loadptr(dev, r_A);
 594                                 emit_cmpi(r_A, 0);
 595                                 emit_branch(BE_PTR, cleanup_addr + 4);
 596                                 emit_nop();
 597                                 emit_load32(r_A, struct net_device, ifindex, r_A);
 598                                 break;
 599                         case BPF_ANC | SKF_AD_MARK:
 600                                 emit_skb_load32(mark, r_A);
 601                                 break;
 602                         case BPF_ANC | SKF_AD_QUEUE:
 603                                 emit_skb_load16(queue_mapping, r_A);
 604                                 break;
 605                         case BPF_ANC | SKF_AD_HATYPE:
 606                                 emit_skb_loadptr(dev, r_A);
 607                                 emit_cmpi(r_A, 0);
 608                                 emit_branch(BE_PTR, cleanup_addr + 4);
 609                                 emit_nop();
 610                                 emit_load16(r_A, struct net_device, type, r_A);
 611                                 break;
 612                         case BPF_ANC | SKF_AD_RXHASH:
 613                                 emit_skb_load32(hash, r_A);
 614                                 break;
 615                         case BPF_ANC | SKF_AD_VLAN_TAG:
 616                         case BPF_ANC | SKF_AD_VLAN_TAG_PRESENT:
 617                                 emit_skb_load16(vlan_tci, r_A);
 618                                 if (code == (BPF_ANC | SKF_AD_VLAN_TAG)) {
 619                                         emit_andi(r_A, VLAN_VID_MASK, r_A);
 620                                 } else {
 621                                         emit_loadimm(VLAN_TAG_PRESENT, r_TMP);
 622                                         emit_and(r_A, r_TMP, r_A);
 623                                 }
 624                                 break;
 625
 626                         case BPF_LD | BPF_IMM:
 627                                 emit_loadimm(K, r_A);
 628                                 break;
 629                         case BPF_LDX | BPF_IMM:
 630                                 emit_loadimm(K, r_X);
 631                                 break;
 632                         case BPF_LD | BPF_MEM:
 633                                 emit_ldmem(K * 4, r_A);
 634                                 break;
 635                         case BPF_LDX | BPF_MEM:
 636                                 emit_ldmem(K * 4, r_X);
 637                                 break;
 638                         case BPF_ST:
 639                                 emit_stmem(K * 4, r_A);
 640                                 break;
 641                         case BPF_STX:
 642                                 emit_stmem(K * 4, r_X);
 643                                 break;
 644
 645 #define CHOOSE_LOAD_FUNC(K, func) \
 646         ((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative_offset : func) : func##_positive_offset)
 647
 648                         case BPF_LD | BPF_W | BPF_ABS:
 649                                 func = CHOOSE_LOAD_FUNC(K, bpf_jit_load_word);
 650 common_load:                    seen |= SEEN_DATAREF;
 651                                 emit_loadimm(K, r_OFF);
 652                                 emit_call(func);
 653                                 break;
 654                         case BPF_LD | BPF_H | BPF_ABS:
 655                                 func = CHOOSE_LOAD_FUNC(K, bpf_jit_load_half);
 656                                 goto common_load;
 657                         case BPF_LD | BPF_B | BPF_ABS:
 658                                 func = CHOOSE_LOAD_FUNC(K, bpf_jit_load_byte);
 659                                 goto common_load;
 660                         case BPF_LDX | BPF_B | BPF_MSH:
 661                                 func = CHOOSE_LOAD_FUNC(K, bpf_jit_load_byte_msh);
 662                                 goto common_load;
 663                         case BPF_LD | BPF_W | BPF_IND:
 664                                 func = bpf_jit_load_word;
 665 common_load_ind:                seen |= SEEN_DATAREF | SEEN_XREG;
 666                                 if (K) {
 667                                         if (is_simm13(K)) {
 668                                                 emit_addi(r_X, K, r_OFF);
 669                                         } else {
 670                                                 emit_loadimm(K, r_TMP);
 671                                                 emit_add(r_X, r_TMP, r_OFF);
 672                                         }
 673                                 } else {
 674                                         emit_reg_move(r_X, r_OFF);
 675                                 }
 676                                 emit_call(func);
 677                                 break;
 678                         case BPF_LD | BPF_H | BPF_IND:
 679                                 func = bpf_jit_load_half;
 680                                 goto common_load_ind;
 681                         case BPF_LD | BPF_B | BPF_IND:
 682                                 func = bpf_jit_load_byte;
 683                                 goto common_load_ind;
 684                         case BPF_JMP | BPF_JA:
 685                                 emit_jump(addrs[i + K]);
 686                                 emit_nop();
 687                                 break;
 688
 689 #define COND_SEL(CODE, TOP, FOP)        \
 690         case CODE:                      \
 691                 t_op = TOP;             \
 692                 f_op = FOP;             \
 693                 goto cond_branch
 694
 695                         COND_SEL(BPF_JMP | BPF_JGT | BPF_K, BGU, BLEU);
 696                         COND_SEL(BPF_JMP | BPF_JGE | BPF_K, BGEU, BLU);
 697                         COND_SEL(BPF_JMP | BPF_JEQ | BPF_K, BE, BNE);
 698                         COND_SEL(BPF_JMP | BPF_JSET | BPF_K, BNE, BE);
 699                         COND_SEL(BPF_JMP | BPF_JGT | BPF_X, BGU, BLEU);
 700                         COND_SEL(BPF_JMP | BPF_JGE | BPF_X, BGEU, BLU);
 701                         COND_SEL(BPF_JMP | BPF_JEQ | BPF_X, BE, BNE);
 702                         COND_SEL(BPF_JMP | BPF_JSET | BPF_X, BNE, BE);
 703
 704 cond_branch:                    f_offset = addrs[i + filter[i].jf];
 705                                 t_offset = addrs[i + filter[i].jt];
 706
 707                                 /* same targets, can avoid doing the test :) */
 708                                 if (filter[i].jt == filter[i].jf) {
 709                                         emit_jump(t_offset);
 710                                         emit_nop();
 711                                         break;
 712                                 }
 713
 714                                 switch (code) {
 715                                 case BPF_JMP | BPF_JGT | BPF_X:
 716                                 case BPF_JMP | BPF_JGE | BPF_X:
 717                                 case BPF_JMP | BPF_JEQ | BPF_X:
 718                                         seen |= SEEN_XREG;
 719                                         emit_cmp(r_A, r_X);
 720                                         break;
 721                                 case BPF_JMP | BPF_JSET | BPF_X:
 722                                         seen |= SEEN_XREG;
 723                                         emit_btst(r_A, r_X);
 724                                         break;
 725                                 case BPF_JMP | BPF_JEQ | BPF_K:
 726                                 case BPF_JMP | BPF_JGT | BPF_K:
 727                                 case BPF_JMP | BPF_JGE | BPF_K:
 728                                         if (is_simm13(K)) {
 729                                                 emit_cmpi(r_A, K);
 730                                         } else {
 731                                                 emit_loadimm(K, r_TMP);
 732                                                 emit_cmp(r_A, r_TMP);
 733                                         }
 734                                         break;
 735                                 case BPF_JMP | BPF_JSET | BPF_K:
 736                                         if (is_simm13(K)) {
 737                                                 emit_btsti(r_A, K);
 738                                         } else {
 739                                                 emit_loadimm(K, r_TMP);
 740                                                 emit_btst(r_A, r_TMP);
 741                                         }
 742                                         break;
 743                                 }
 744                                 if (filter[i].jt != 0) {
 745                                         if (filter[i].jf)
 746                                                 t_offset += 8;
 747                                         emit_branch(t_op, t_offset);
 748                                         emit_nop(); /* delay slot */
 749                                         if (filter[i].jf) {
 750                                                 emit_jump(f_offset);
 751                                                 emit_nop();
 752                                         }
 753                                         break;
 754                                 }
 755                                 emit_branch(f_op, f_offset);
 756                                 emit_nop(); /* delay slot */
 757                                 break;
 758
 759                         default:
 760                                 /* hmm, too complex filter, give up with jit compiler */
 761                                 goto out;
 762                         }
 763                         ilen = (void *) prog - (void *) temp;
 764                         if (image) {
 765                                 if (unlikely(proglen + ilen > oldproglen)) {
 766                                         pr_err("bpb_jit_compile fatal error\n");
 767                                         kfree(addrs);
 768                                         module_free(NULL, image);
 769                                         return;
 770                                 }
 771                                 memcpy(image + proglen, temp, ilen);
 772                         }
 773                         proglen += ilen;
 774                         addrs[i] = proglen;
 775                         prog = temp;
 776                 }
 777                 /* last bpf instruction is always a RET :
 778                  * use it to give the cleanup instruction(s) addr
 779                  */
 780                 cleanup_addr = proglen - 8; /* jmpl; mov r_A,%o0; */
 781                 if (seen_or_pass0 & SEEN_MEM)
 782                         cleanup_addr -= 4; /* add %sp, X, %sp; */
 783
 784                 if (image) {
 785                         if (proglen != oldproglen)
 786                                 pr_err("bpb_jit_compile proglen=%u != oldproglen=%u\n",
 787                                        proglen, oldproglen);
 788                         break;
 789                 }
 790                 if (proglen == oldproglen) {
 791                         image = module_alloc(proglen);
 792                         if (!image)
 793                                 goto out;
 794                 }
 795                 oldproglen = proglen;
 796         }
 797
 798         if (bpf_jit_enable > 1)
 799                 bpf_jit_dump(flen, proglen, pass, image);
 800
 801         if (image) {
 802                 bpf_flush_icache(image, image + proglen);
 803                 fp->bpf_func = (void *)image;
 804                 fp->jited = 1;
 805         }
 806 out:
 807         kfree(addrs);
 808         return;
 809 }
 810
 811 void bpf_jit_free(struct bpf_prog *fp)
 812 {
 813         if (fp->jited)
 814                 module_free(NULL, fp->bpf_func);
 815         kfree(fp);
 816 }