arch/sparc/mm/srmmu.c

   1 /*
   2  * srmmu.c:  SRMMU specific routines for memory management.
   3  *
   4  * Copyright (C) 1995 David S. Miller  (davem@caip.rutgers.edu)
   5  * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
   6  * Copyright (C) 1996 Eddie C. Dost    (ecd@skynet.be)
   7  * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   8  * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/mm.h>
  13 #include <linux/vmalloc.h>
  14 #include <linux/pagemap.h>
  15 #include <linux/init.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/bootmem.h>
  18 #include <linux/fs.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/kdebug.h>
  21 #include <linux/log2.h>
  22 #include <linux/gfp.h>
  23
  24 #include <asm/bitext.h>
  25 #include <asm/page.h>
  26 #include <asm/pgalloc.h>
  27 #include <asm/pgtable.h>
  28 #include <asm/io.h>
  29 #include <asm/vaddrs.h>
  30 #include <asm/traps.h>
  31 #include <asm/smp.h>
  32 #include <asm/mbus.h>
  33 #include <asm/cache.h>
  34 #include <asm/oplib.h>
  35 #include <asm/asi.h>
  36 #include <asm/msi.h>
  37 #include <asm/mmu_context.h>
  38 #include <asm/io-unit.h>
  39 #include <asm/cacheflush.h>
  40 #include <asm/tlbflush.h>
  41
  42 /* Now the cpu specific definitions. */
  43 #include <asm/viking.h>
  44 #include <asm/mxcc.h>
  45 #include <asm/ross.h>
  46 #include <asm/tsunami.h>
  47 #include <asm/swift.h>
  48 #include <asm/turbosparc.h>
  49 #include <asm/leon.h>
  50
  51 #include <asm/btfixup.h>
  52
  53 enum mbus_module srmmu_modtype;
  54 static unsigned int hwbug_bitmask;
  55 int vac_cache_size;
  56 int vac_line_size;
  57
  58 extern struct resource sparc_iomap;
  59
  60 extern unsigned long last_valid_pfn;
  61
  62 extern unsigned long page_kernel;
  63
  64 static pgd_t *srmmu_swapper_pg_dir;
  65
  66 #ifdef CONFIG_SMP
  67 #define FLUSH_BEGIN(mm)
  68 #define FLUSH_END
  69 #else
  70 #define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {
  71 #define FLUSH_END       }
  72 #endif
  73
  74 BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)
  75 #define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
  76
  77 int flush_page_for_dma_global = 1;
  78
  79 #ifdef CONFIG_SMP
  80 BTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long)
  81 #define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)
  82 #endif
  83
  84 char *srmmu_name;
  85
  86 ctxd_t *srmmu_ctx_table_phys;
  87 static ctxd_t *srmmu_context_table;
  88
  89 int viking_mxcc_present;
  90 static DEFINE_SPINLOCK(srmmu_context_spinlock);
  91
  92 static int is_hypersparc;
  93
  94 static int srmmu_cache_pagetables;
  95
  96 /* these will be initialized in srmmu_nocache_calcsize() */
  97 static unsigned long srmmu_nocache_size;
  98 static unsigned long srmmu_nocache_end;
  99
 100 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
 101 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
 102
 103 /* The context table is a nocache user with the biggest alignment needs. */
 104 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
 105
 106 void *srmmu_nocache_pool;
 107 void *srmmu_nocache_bitmap;
 108 static struct bit_map srmmu_nocache_map;
 109
 110 static inline unsigned long srmmu_pgd_page(pgd_t pgd)
 111 { return srmmu_device_memory(pgd_val(pgd))?~0:(unsigned long)__nocache_va((pgd_val(pgd) & SRMMU_PTD_PMASK) << 4); }
 112
 113
 114 static inline int srmmu_pte_none(pte_t pte)
 115 { return !(pte_val(pte) & 0xFFFFFFF); }
 116
 117 static inline int srmmu_pte_present(pte_t pte)
 118 { return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); }
 119
 120 static inline int srmmu_pmd_none(pmd_t pmd)
 121 { return !(pmd_val(pmd) & 0xFFFFFFF); }
 122
 123 static inline int srmmu_pmd_bad(pmd_t pmd)
 124 { return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
 125
 126 static inline int srmmu_pmd_present(pmd_t pmd)
 127 { return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
 128
 129 static inline int srmmu_pgd_none(pgd_t pgd)
 130 { return !(pgd_val(pgd) & 0xFFFFFFF); }
 131
 132 static inline int srmmu_pgd_bad(pgd_t pgd)
 133 { return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
 134
 135 static inline int srmmu_pgd_present(pgd_t pgd)
 136 { return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
 137
 138 static inline pte_t srmmu_pte_wrprotect(pte_t pte)
 139 { return __pte(pte_val(pte) & ~SRMMU_WRITE);}
 140
 141 static inline pte_t srmmu_pte_mkclean(pte_t pte)
 142 { return __pte(pte_val(pte) & ~SRMMU_DIRTY);}
 143
 144 static inline pte_t srmmu_pte_mkold(pte_t pte)
 145 { return __pte(pte_val(pte) & ~SRMMU_REF);}
 146
 147 static inline pte_t srmmu_pte_mkwrite(pte_t pte)
 148 { return __pte(pte_val(pte) | SRMMU_WRITE);}
 149
 150 static inline pte_t srmmu_pte_mkdirty(pte_t pte)
 151 { return __pte(pte_val(pte) | SRMMU_DIRTY);}
 152
 153 static inline pte_t srmmu_pte_mkyoung(pte_t pte)
 154 { return __pte(pte_val(pte) | SRMMU_REF);}
 155
 156 /*
 157  * Conversion functions: convert a page and protection to a page entry,
 158  * and a page entry and page directory to the page they refer to.
 159  */
 160 static pte_t srmmu_mk_pte(struct page *page, pgprot_t pgprot)
 161 { return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot)); }
 162
 163 static pte_t srmmu_mk_pte_phys(unsigned long page, pgprot_t pgprot)
 164 { return __pte(((page) >> 4) | pgprot_val(pgprot)); }
 165
 166 static pte_t srmmu_mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
 167 { return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot)); }
 168
 169 /* XXX should we hyper_flush_whole_icache here - Anton */
 170 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
 171 { srmmu_set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
 172
 173 static inline void srmmu_pgd_set(pgd_t * pgdp, pmd_t * pmdp)
 174 { srmmu_set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pmdp) >> 4))); }
 175
 176 static void srmmu_pmd_set(pmd_t *pmdp, pte_t *ptep)
 177 {
 178         unsigned long ptp;      /* Physical address, shifted right by 4 */
 179         int i;
 180
 181         ptp = __nocache_pa((unsigned long) ptep) >> 4;
 182         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 183                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 184                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 185         }
 186 }
 187
 188 static void srmmu_pmd_populate(pmd_t *pmdp, struct page *ptep)
 189 {
 190         unsigned long ptp;      /* Physical address, shifted right by 4 */
 191         int i;
 192
 193         ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4);      /* watch for overflow */
 194         for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
 195                 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
 196                 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
 197         }
 198 }
 199
 200 static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot)
 201 { return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); }
 202
 203 /* to find an entry in a top-level page table... */
 204 static inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address)
 205 { return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); }
 206
 207 /* Find an entry in the second-level page table.. */
 208 static inline pmd_t *srmmu_pmd_offset(pgd_t * dir, unsigned long address)
 209 {
 210         return (pmd_t *) srmmu_pgd_page(*dir) +
 211             ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
 212 }
 213
 214 /* Find an entry in the third-level page table.. */
 215 static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address)
 216 {
 217         void *pte;
 218
 219         pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
 220         return (pte_t *) pte +
 221             ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
 222 }
 223
 224 static unsigned long srmmu_swp_type(swp_entry_t entry)
 225 {
 226         return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
 227 }
 228
 229 static unsigned long srmmu_swp_offset(swp_entry_t entry)
 230 {
 231         return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
 232 }
 233
 234 static swp_entry_t srmmu_swp_entry(unsigned long type, unsigned long offset)
 235 {
 236         return (swp_entry_t) {
 237                   (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
 238                 | (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
 239 }
 240
 241 /*
 242  * size: bytes to allocate in the nocache area.
 243  * align: bytes, number to align at.
 244  * Returns the virtual address of the allocated area.
 245  */
 246 static unsigned long __srmmu_get_nocache(int size, int align)
 247 {
 248         int offset;
 249
 250         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 251                 printk("Size 0x%x too small for nocache request\n", size);
 252                 size = SRMMU_NOCACHE_BITMAP_SHIFT;
 253         }
 254         if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) {
 255                 printk("Size 0x%x unaligned int nocache request\n", size);
 256                 size += SRMMU_NOCACHE_BITMAP_SHIFT-1;
 257         }
 258         BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
 259
 260         offset = bit_map_string_get(&srmmu_nocache_map,
 261                                         size >> SRMMU_NOCACHE_BITMAP_SHIFT,
 262                                         align >> SRMMU_NOCACHE_BITMAP_SHIFT);
 263         if (offset == -1) {
 264                 printk("srmmu: out of nocache %d: %d/%d\n",
 265                     size, (int) srmmu_nocache_size,
 266                     srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
 267                 return 0;
 268         }
 269
 270         return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
 271 }
 272
 273 static unsigned long srmmu_get_nocache(int size, int align)
 274 {
 275         unsigned long tmp;
 276
 277         tmp = __srmmu_get_nocache(size, align);
 278
 279         if (tmp)
 280                 memset((void *)tmp, 0, size);
 281
 282         return tmp;
 283 }
 284
 285 static void srmmu_free_nocache(unsigned long vaddr, int size)
 286 {
 287         int offset;
 288
 289         if (vaddr < SRMMU_NOCACHE_VADDR) {
 290                 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
 291                     vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
 292                 BUG();
 293         }
 294         if (vaddr+size > srmmu_nocache_end) {
 295                 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
 296                     vaddr, srmmu_nocache_end);
 297                 BUG();
 298         }
 299         if (!is_power_of_2(size)) {
 300                 printk("Size 0x%x is not a power of 2\n", size);
 301                 BUG();
 302         }
 303         if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
 304                 printk("Size 0x%x is too small\n", size);
 305                 BUG();
 306         }
 307         if (vaddr & (size-1)) {
 308                 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
 309                 BUG();
 310         }
 311
 312         offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
 313         size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 314
 315         bit_map_clear(&srmmu_nocache_map, offset, size);
 316 }
 317
 318 static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
 319                                                  unsigned long end);
 320
 321 extern unsigned long probe_memory(void);        /* in fault.c */
 322
 323 /*
 324  * Reserve nocache dynamically proportionally to the amount of
 325  * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
 326  */
 327 static void srmmu_nocache_calcsize(void)
 328 {
 329         unsigned long sysmemavail = probe_memory() / 1024;
 330         int srmmu_nocache_npages;
 331
 332         srmmu_nocache_npages =
 333                 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
 334
 335  /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
 336         // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
 337         if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
 338                 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
 339
 340         /* anything above 1280 blows up */
 341         if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
 342                 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
 343
 344         srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
 345         srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
 346 }
 347
 348 static void __init srmmu_nocache_init(void)
 349 {
 350         unsigned int bitmap_bits;
 351         pgd_t *pgd;
 352         pmd_t *pmd;
 353         pte_t *pte;
 354         unsigned long paddr, vaddr;
 355         unsigned long pteval;
 356
 357         bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
 358
 359         srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
 360                 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
 361         memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
 362
 363         srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL);
 364         bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
 365
 366         srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 367         memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
 368         init_mm.pgd = srmmu_swapper_pg_dir;
 369
 370         srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
 371
 372         paddr = __pa((unsigned long)srmmu_nocache_pool);
 373         vaddr = SRMMU_NOCACHE_VADDR;
 374
 375         while (vaddr < srmmu_nocache_end) {
 376                 pgd = pgd_offset_k(vaddr);
 377                 pmd = srmmu_pmd_offset(__nocache_fix(pgd), vaddr);
 378                 pte = srmmu_pte_offset(__nocache_fix(pmd), vaddr);
 379
 380                 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
 381
 382                 if (srmmu_cache_pagetables)
 383                         pteval |= SRMMU_CACHE;
 384
 385                 srmmu_set_pte(__nocache_fix(pte), __pte(pteval));
 386
 387                 vaddr += PAGE_SIZE;
 388                 paddr += PAGE_SIZE;
 389         }
 390
 391         flush_cache_all();
 392         flush_tlb_all();
 393 }
 394
 395 static inline pgd_t *srmmu_get_pgd_fast(void)
 396 {
 397         pgd_t *pgd = NULL;
 398
 399         pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
 400         if (pgd) {
 401                 pgd_t *init = pgd_offset_k(0);
 402                 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
 403                 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
 404                                                 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
 405         }
 406
 407         return pgd;
 408 }
 409
 410 static void srmmu_free_pgd_fast(pgd_t *pgd)
 411 {
 412         srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE);
 413 }
 414
 415 static pmd_t *srmmu_pmd_alloc_one(struct mm_struct *mm, unsigned long address)
 416 {
 417         return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
 418 }
 419
 420 static void srmmu_pmd_free(pmd_t * pmd)
 421 {
 422         srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE);
 423 }
 424
 425 /*
 426  * Hardware needs alignment to 256 only, but we align to whole page size
 427  * to reduce fragmentation problems due to the buddy principle.
 428  * XXX Provide actual fragmentation statistics in /proc.
 429  *
 430  * Alignments up to the page size are the same for physical and virtual
 431  * addresses of the nocache area.
 432  */
 433 static pte_t *
 434 srmmu_pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
 435 {
 436         return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
 437 }
 438
 439 static pgtable_t
 440 srmmu_pte_alloc_one(struct mm_struct *mm, unsigned long address)
 441 {
 442         unsigned long pte;
 443         struct page *page;
 444
 445         if ((pte = (unsigned long)srmmu_pte_alloc_one_kernel(mm, address)) == 0)
 446                 return NULL;
 447         page = pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
 448         pgtable_page_ctor(page);
 449         return page;
 450 }
 451
 452 static void srmmu_free_pte_fast(pte_t *pte)
 453 {
 454         srmmu_free_nocache((unsigned long)pte, PTE_SIZE);
 455 }
 456
 457 static void srmmu_pte_free(pgtable_t pte)
 458 {
 459         unsigned long p;
 460
 461         pgtable_page_dtor(pte);
 462         p = (unsigned long)page_address(pte);   /* Cached address (for test) */
 463         if (p == 0)
 464                 BUG();
 465         p = page_to_pfn(pte) << PAGE_SHIFT;     /* Physical address */
 466         p = (unsigned long) __nocache_va(p);    /* Nocached virtual */
 467         srmmu_free_nocache(p, PTE_SIZE);
 468 }
 469
 470 /*
 471  */
 472 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
 473 {
 474         struct ctx_list *ctxp;
 475
 476         ctxp = ctx_free.next;
 477         if(ctxp != &ctx_free) {
 478                 remove_from_ctx_list(ctxp);
 479                 add_to_used_ctxlist(ctxp);
 480                 mm->context = ctxp->ctx_number;
 481                 ctxp->ctx_mm = mm;
 482                 return;
 483         }
 484         ctxp = ctx_used.next;
 485         if(ctxp->ctx_mm == old_mm)
 486                 ctxp = ctxp->next;
 487         if(ctxp == &ctx_used)
 488                 panic("out of mmu contexts");
 489         flush_cache_mm(ctxp->ctx_mm);
 490         flush_tlb_mm(ctxp->ctx_mm);
 491         remove_from_ctx_list(ctxp);
 492         add_to_used_ctxlist(ctxp);
 493         ctxp->ctx_mm->context = NO_CONTEXT;
 494         ctxp->ctx_mm = mm;
 495         mm->context = ctxp->ctx_number;
 496 }
 497
 498 static inline void free_context(int context)
 499 {
 500         struct ctx_list *ctx_old;
 501
 502         ctx_old = ctx_list_pool + context;
 503         remove_from_ctx_list(ctx_old);
 504         add_to_free_ctxlist(ctx_old);
 505 }
 506
 507
 508 void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
 509                struct task_struct *tsk)
 510 {
 511         if(mm->context == NO_CONTEXT) {
 512                 spin_lock(&srmmu_context_spinlock);
 513                 alloc_context(old_mm, mm);
 514                 spin_unlock(&srmmu_context_spinlock);
 515                 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
 516         }
 517
 518         if (sparc_cpu_model == sparc_leon)
 519                 leon_switch_mm();
 520
 521         if (is_hypersparc)
 522                 hyper_flush_whole_icache();
 523
 524         srmmu_set_context(mm->context);
 525 }
 526
 527 /* Low level IO area allocation on the SRMMU. */
 528 static inline void srmmu_mapioaddr(unsigned long physaddr,
 529     unsigned long virt_addr, int bus_type)
 530 {
 531         pgd_t *pgdp;
 532         pmd_t *pmdp;
 533         pte_t *ptep;
 534         unsigned long tmp;
 535
 536         physaddr &= PAGE_MASK;
 537         pgdp = pgd_offset_k(virt_addr);
 538         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 539         ptep = srmmu_pte_offset(pmdp, virt_addr);
 540         tmp = (physaddr >> 4) | SRMMU_ET_PTE;
 541
 542         /*
 543          * I need to test whether this is consistent over all
 544          * sun4m's.  The bus_type represents the upper 4 bits of
 545          * 36-bit physical address on the I/O space lines...
 546          */
 547         tmp |= (bus_type << 28);
 548         tmp |= SRMMU_PRIV;
 549         __flush_page_to_ram(virt_addr);
 550         srmmu_set_pte(ptep, __pte(tmp));
 551 }
 552
 553 static void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
 554     unsigned long xva, unsigned int len)
 555 {
 556         while (len != 0) {
 557                 len -= PAGE_SIZE;
 558                 srmmu_mapioaddr(xpa, xva, bus);
 559                 xva += PAGE_SIZE;
 560                 xpa += PAGE_SIZE;
 561         }
 562         flush_tlb_all();
 563 }
 564
 565 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
 566 {
 567         pgd_t *pgdp;
 568         pmd_t *pmdp;
 569         pte_t *ptep;
 570
 571         pgdp = pgd_offset_k(virt_addr);
 572         pmdp = srmmu_pmd_offset(pgdp, virt_addr);
 573         ptep = srmmu_pte_offset(pmdp, virt_addr);
 574
 575         /* No need to flush uncacheable page. */
 576         __pte_clear(ptep);
 577 }
 578
 579 static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
 580 {
 581         while (len != 0) {
 582                 len -= PAGE_SIZE;
 583                 srmmu_unmapioaddr(virt_addr);
 584                 virt_addr += PAGE_SIZE;
 585         }
 586         flush_tlb_all();
 587 }
 588
 589 /*
 590  * On the SRMMU we do not have the problems with limited tlb entries
 591  * for mapping kernel pages, so we just take things from the free page
 592  * pool.  As a side effect we are putting a little too much pressure
 593  * on the gfp() subsystem.  This setup also makes the logic of the
 594  * iommu mapping code a lot easier as we can transparently handle
 595  * mappings on the kernel stack without any special code.
 596  */
 597 struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node)
 598 {
 599         struct thread_info *ret;
 600
 601         ret = (struct thread_info *)__get_free_pages(GFP_KERNEL,
 602                                                      THREAD_INFO_ORDER);
 603 #ifdef CONFIG_DEBUG_STACK_USAGE
 604         if (ret)
 605                 memset(ret, 0, PAGE_SIZE << THREAD_INFO_ORDER);
 606 #endif /* DEBUG_STACK_USAGE */
 607
 608         return ret;
 609 }
 610
 611 void free_thread_info(struct thread_info *ti)
 612 {
 613         free_pages((unsigned long)ti, THREAD_INFO_ORDER);
 614 }
 615
 616 /* tsunami.S */
 617 extern void tsunami_flush_cache_all(void);
 618 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
 619 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 620 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 621 extern void tsunami_flush_page_to_ram(unsigned long page);
 622 extern void tsunami_flush_page_for_dma(unsigned long page);
 623 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 624 extern void tsunami_flush_tlb_all(void);
 625 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
 626 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 627 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 628 extern void tsunami_setup_blockops(void);
 629
 630 /*
 631  * Workaround, until we find what's going on with Swift. When low on memory,
 632  * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find
 633  * out it is already in page tables/ fault again on the same instruction.
 634  * I really don't understand it, have checked it and contexts
 635  * are right, flush_tlb_all is done as well, and it faults again...
 636  * Strange. -jj
 637  *
 638  * The following code is a deadwood that may be necessary when
 639  * we start to make precise page flushes again. --zaitcev
 640  */
 641 static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t *ptep)
 642 {
 643 #if 0
 644         static unsigned long last;
 645         unsigned int val;
 646         /* unsigned int n; */
 647
 648         if (address == last) {
 649                 val = srmmu_hwprobe(address);
 650                 if (val != 0 && pte_val(*ptep) != val) {
 651                         printk("swift_update_mmu_cache: "
 652                             "addr %lx put %08x probed %08x from %pf\n",
 653                             address, pte_val(*ptep), val,
 654                             __builtin_return_address(0));
 655                         srmmu_flush_whole_tlb();
 656                 }
 657         }
 658         last = address;
 659 #endif
 660 }
 661
 662 /* swift.S */
 663 extern void swift_flush_cache_all(void);
 664 extern void swift_flush_cache_mm(struct mm_struct *mm);
 665 extern void swift_flush_cache_range(struct vm_area_struct *vma,
 666                                     unsigned long start, unsigned long end);
 667 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 668 extern void swift_flush_page_to_ram(unsigned long page);
 669 extern void swift_flush_page_for_dma(unsigned long page);
 670 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 671 extern void swift_flush_tlb_all(void);
 672 extern void swift_flush_tlb_mm(struct mm_struct *mm);
 673 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
 674                                   unsigned long start, unsigned long end);
 675 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 676
 677 #if 0  /* P3: deadwood to debug precise flushes on Swift. */
 678 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 679 {
 680         int cctx, ctx1;
 681
 682         page &= PAGE_MASK;
 683         if ((ctx1 = vma->vm_mm->context) != -1) {
 684                 cctx = srmmu_get_context();
 685 /* Is context # ever different from current context? P3 */
 686                 if (cctx != ctx1) {
 687                         printk("flush ctx %02x curr %02x\n", ctx1, cctx);
 688                         srmmu_set_context(ctx1);
 689                         swift_flush_page(page);
 690                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 691                                         "r" (page), "i" (ASI_M_FLUSH_PROBE));
 692                         srmmu_set_context(cctx);
 693                 } else {
 694                          /* Rm. prot. bits from virt. c. */
 695                         /* swift_flush_cache_all(); */
 696                         /* swift_flush_cache_page(vma, page); */
 697                         swift_flush_page(page);
 698
 699                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
 700                                 "r" (page), "i" (ASI_M_FLUSH_PROBE));
 701                         /* same as above: srmmu_flush_tlb_page() */
 702                 }
 703         }
 704 }
 705 #endif
 706
 707 /*
 708  * The following are all MBUS based SRMMU modules, and therefore could
 709  * be found in a multiprocessor configuration.  On the whole, these
 710  * chips seems to be much more touchy about DVMA and page tables
 711  * with respect to cache coherency.
 712  */
 713
 714 /* Cypress flushes. */
 715 static void cypress_flush_cache_all(void)
 716 {
 717         volatile unsigned long cypress_sucks;
 718         unsigned long faddr, tagval;
 719
 720         flush_user_windows();
 721         for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
 722                 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
 723                                      "=r" (tagval) :
 724                                      "r" (faddr), "r" (0x40000),
 725                                      "i" (ASI_M_DATAC_TAG));
 726
 727                 /* If modified and valid, kick it. */
 728                 if((tagval & 0x60) == 0x60)
 729                         cypress_sucks = *(unsigned long *)(0xf0020000 + faddr);
 730         }
 731 }
 732
 733 static void cypress_flush_cache_mm(struct mm_struct *mm)
 734 {
 735         register unsigned long a, b, c, d, e, f, g;
 736         unsigned long flags, faddr;
 737         int octx;
 738
 739         FLUSH_BEGIN(mm)
 740         flush_user_windows();
 741         local_irq_save(flags);
 742         octx = srmmu_get_context();
 743         srmmu_set_context(mm->context);
 744         a = 0x20; b = 0x40; c = 0x60;
 745         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 746
 747         faddr = (0x10000 - 0x100);
 748         goto inside;
 749         do {
 750                 faddr -= 0x100;
 751         inside:
 752                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 753                                      "sta %%g0, [%0 + %2] %1\n\t"
 754                                      "sta %%g0, [%0 + %3] %1\n\t"
 755                                      "sta %%g0, [%0 + %4] %1\n\t"
 756                                      "sta %%g0, [%0 + %5] %1\n\t"
 757                                      "sta %%g0, [%0 + %6] %1\n\t"
 758                                      "sta %%g0, [%0 + %7] %1\n\t"
 759                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 760                                      "r" (faddr), "i" (ASI_M_FLUSH_CTX),
 761                                      "r" (a), "r" (b), "r" (c), "r" (d),
 762                                      "r" (e), "r" (f), "r" (g));
 763         } while(faddr);
 764         srmmu_set_context(octx);
 765         local_irq_restore(flags);
 766         FLUSH_END
 767 }
 768
 769 static void cypress_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 770 {
 771         struct mm_struct *mm = vma->vm_mm;
 772         register unsigned long a, b, c, d, e, f, g;
 773         unsigned long flags, faddr;
 774         int octx;
 775
 776         FLUSH_BEGIN(mm)
 777         flush_user_windows();
 778         local_irq_save(flags);
 779         octx = srmmu_get_context();
 780         srmmu_set_context(mm->context);
 781         a = 0x20; b = 0x40; c = 0x60;
 782         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 783
 784         start &= SRMMU_REAL_PMD_MASK;
 785         while(start < end) {
 786                 faddr = (start + (0x10000 - 0x100));
 787                 goto inside;
 788                 do {
 789                         faddr -= 0x100;
 790                 inside:
 791                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 792                                              "sta %%g0, [%0 + %2] %1\n\t"
 793                                              "sta %%g0, [%0 + %3] %1\n\t"
 794                                              "sta %%g0, [%0 + %4] %1\n\t"
 795                                              "sta %%g0, [%0 + %5] %1\n\t"
 796                                              "sta %%g0, [%0 + %6] %1\n\t"
 797                                              "sta %%g0, [%0 + %7] %1\n\t"
 798                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 799                                              "r" (faddr),
 800                                              "i" (ASI_M_FLUSH_SEG),
 801                                              "r" (a), "r" (b), "r" (c), "r" (d),
 802                                              "r" (e), "r" (f), "r" (g));
 803                 } while (faddr != start);
 804                 start += SRMMU_REAL_PMD_SIZE;
 805         }
 806         srmmu_set_context(octx);
 807         local_irq_restore(flags);
 808         FLUSH_END
 809 }
 810
 811 static void cypress_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
 812 {
 813         register unsigned long a, b, c, d, e, f, g;
 814         struct mm_struct *mm = vma->vm_mm;
 815         unsigned long flags, line;
 816         int octx;
 817
 818         FLUSH_BEGIN(mm)
 819         flush_user_windows();
 820         local_irq_save(flags);
 821         octx = srmmu_get_context();
 822         srmmu_set_context(mm->context);
 823         a = 0x20; b = 0x40; c = 0x60;
 824         d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 825
 826         page &= PAGE_MASK;
 827         line = (page + PAGE_SIZE) - 0x100;
 828         goto inside;
 829         do {
 830                 line -= 0x100;
 831         inside:
 832                         __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 833                                              "sta %%g0, [%0 + %2] %1\n\t"
 834                                              "sta %%g0, [%0 + %3] %1\n\t"
 835                                              "sta %%g0, [%0 + %4] %1\n\t"
 836                                              "sta %%g0, [%0 + %5] %1\n\t"
 837                                              "sta %%g0, [%0 + %6] %1\n\t"
 838                                              "sta %%g0, [%0 + %7] %1\n\t"
 839                                              "sta %%g0, [%0 + %8] %1\n\t" : :
 840                                              "r" (line),
 841                                              "i" (ASI_M_FLUSH_PAGE),
 842                                              "r" (a), "r" (b), "r" (c), "r" (d),
 843                                              "r" (e), "r" (f), "r" (g));
 844         } while(line != page);
 845         srmmu_set_context(octx);
 846         local_irq_restore(flags);
 847         FLUSH_END
 848 }
 849
 850 /* Cypress is copy-back, at least that is how we configure it. */
 851 static void cypress_flush_page_to_ram(unsigned long page)
 852 {
 853         register unsigned long a, b, c, d, e, f, g;
 854         unsigned long line;
 855
 856         a = 0x20; b = 0x40; c = 0x60; d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
 857         page &= PAGE_MASK;
 858         line = (page + PAGE_SIZE) - 0x100;
 859         goto inside;
 860         do {
 861                 line -= 0x100;
 862         inside:
 863                 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
 864                                      "sta %%g0, [%0 + %2] %1\n\t"
 865                                      "sta %%g0, [%0 + %3] %1\n\t"
 866                                      "sta %%g0, [%0 + %4] %1\n\t"
 867                                      "sta %%g0, [%0 + %5] %1\n\t"
 868                                      "sta %%g0, [%0 + %6] %1\n\t"
 869                                      "sta %%g0, [%0 + %7] %1\n\t"
 870                                      "sta %%g0, [%0 + %8] %1\n\t" : :
 871                                      "r" (line),
 872                                      "i" (ASI_M_FLUSH_PAGE),
 873                                      "r" (a), "r" (b), "r" (c), "r" (d),
 874                                      "r" (e), "r" (f), "r" (g));
 875         } while(line != page);
 876 }
 877
 878 /* Cypress is also IO cache coherent. */
 879 static void cypress_flush_page_for_dma(unsigned long page)
 880 {
 881 }
 882
 883 /* Cypress has unified L2 VIPT, from which both instructions and data
 884  * are stored.  It does not have an onboard icache of any sort, therefore
 885  * no flush is necessary.
 886  */
 887 static void cypress_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
 888 {
 889 }
 890
 891 static void cypress_flush_tlb_all(void)
 892 {
 893         srmmu_flush_whole_tlb();
 894 }
 895
 896 static void cypress_flush_tlb_mm(struct mm_struct *mm)
 897 {
 898         FLUSH_BEGIN(mm)
 899         __asm__ __volatile__(
 900         "lda    [%0] %3, %%g5\n\t"
 901         "sta    %2, [%0] %3\n\t"
 902         "sta    %%g0, [%1] %4\n\t"
 903         "sta    %%g5, [%0] %3\n"
 904         : /* no outputs */
 905         : "r" (SRMMU_CTX_REG), "r" (0x300), "r" (mm->context),
 906           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
 907         : "g5");
 908         FLUSH_END
 909 }
 910
 911 static void cypress_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 912 {
 913         struct mm_struct *mm = vma->vm_mm;
 914         unsigned long size;
 915
 916         FLUSH_BEGIN(mm)
 917         start &= SRMMU_PGDIR_MASK;
 918         size = SRMMU_PGDIR_ALIGN(end) - start;
 919         __asm__ __volatile__(
 920                 "lda    [%0] %5, %%g5\n\t"
 921                 "sta    %1, [%0] %5\n"
 922                 "1:\n\t"
 923                 "subcc  %3, %4, %3\n\t"
 924                 "bne    1b\n\t"
 925                 " sta   %%g0, [%2 + %3] %6\n\t"
 926                 "sta    %%g5, [%0] %5\n"
 927         : /* no outputs */
 928         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (start | 0x200),
 929           "r" (size), "r" (SRMMU_PGDIR_SIZE), "i" (ASI_M_MMUREGS),
 930           "i" (ASI_M_FLUSH_PROBE)
 931         : "g5", "cc");
 932         FLUSH_END
 933 }
 934
 935 static void cypress_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
 936 {
 937         struct mm_struct *mm = vma->vm_mm;
 938
 939         FLUSH_BEGIN(mm)
 940         __asm__ __volatile__(
 941         "lda    [%0] %3, %%g5\n\t"
 942         "sta    %1, [%0] %3\n\t"
 943         "sta    %%g0, [%2] %4\n\t"
 944         "sta    %%g5, [%0] %3\n"
 945         : /* no outputs */
 946         : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (page & PAGE_MASK),
 947           "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
 948         : "g5");
 949         FLUSH_END
 950 }
 951
 952 /* viking.S */
 953 extern void viking_flush_cache_all(void);
 954 extern void viking_flush_cache_mm(struct mm_struct *mm);
 955 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
 956                                      unsigned long end);
 957 extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 958 extern void viking_flush_page_to_ram(unsigned long page);
 959 extern void viking_flush_page_for_dma(unsigned long page);
 960 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
 961 extern void viking_flush_page(unsigned long page);
 962 extern void viking_mxcc_flush_page(unsigned long page);
 963 extern void viking_flush_tlb_all(void);
 964 extern void viking_flush_tlb_mm(struct mm_struct *mm);
 965 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 966                                    unsigned long end);
 967 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
 968                                   unsigned long page);
 969 extern void sun4dsmp_flush_tlb_all(void);
 970 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
 971 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
 972                                    unsigned long end);
 973 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
 974                                   unsigned long page);
 975
 976 /* hypersparc.S */
 977 extern void hypersparc_flush_cache_all(void);
 978 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
 979 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 980 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
 981 extern void hypersparc_flush_page_to_ram(unsigned long page);
 982 extern void hypersparc_flush_page_for_dma(unsigned long page);
 983 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
 984 extern void hypersparc_flush_tlb_all(void);
 985 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
 986 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 987 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
 988 extern void hypersparc_setup_blockops(void);
 989
 990 /*
 991  * NOTE: All of this startup code assumes the low 16mb (approx.) of
 992  *       kernel mappings are done with one single contiguous chunk of
 993  *       ram.  On small ram machines (classics mainly) we only get
 994  *       around 8mb mapped for us.
 995  */
 996
 997 static void __init early_pgtable_allocfail(char *type)
 998 {
 999         prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
1000         prom_halt();
1001 }
1002
1003 static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
1004                                                         unsigned long end)
1005 {
1006         pgd_t *pgdp;
1007         pmd_t *pmdp;
1008         pte_t *ptep;
1009
1010         while(start < end) {
1011                 pgdp = pgd_offset_k(start);
1012                 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1013                         pmdp = (pmd_t *) __srmmu_get_nocache(
1014                             SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1015                         if (pmdp == NULL)
1016                                 early_pgtable_allocfail("pmd");
1017                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1018                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1019                 }
1020                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1021                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1022                         ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
1023                         if (ptep == NULL)
1024                                 early_pgtable_allocfail("pte");
1025                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
1026                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1027                 }
1028                 if (start > (0xffffffffUL - PMD_SIZE))
1029                         break;
1030                 start = (start + PMD_SIZE) & PMD_MASK;
1031         }
1032 }
1033
1034 static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
1035                                                   unsigned long end)
1036 {
1037         pgd_t *pgdp;
1038         pmd_t *pmdp;
1039         pte_t *ptep;
1040
1041         while(start < end) {
1042                 pgdp = pgd_offset_k(start);
1043                 if(srmmu_pgd_none(*pgdp)) {
1044                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1045                         if (pmdp == NULL)
1046                                 early_pgtable_allocfail("pmd");
1047                         memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
1048                         srmmu_pgd_set(pgdp, pmdp);
1049                 }
1050                 pmdp = srmmu_pmd_offset(pgdp, start);
1051                 if(srmmu_pmd_none(*pmdp)) {
1052                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1053                                                              PTE_SIZE);
1054                         if (ptep == NULL)
1055                                 early_pgtable_allocfail("pte");
1056                         memset(ptep, 0, PTE_SIZE);
1057                         srmmu_pmd_set(pmdp, ptep);
1058                 }
1059                 if (start > (0xffffffffUL - PMD_SIZE))
1060                         break;
1061                 start = (start + PMD_SIZE) & PMD_MASK;
1062         }
1063 }
1064
1065 /*
1066  * This is much cleaner than poking around physical address space
1067  * looking at the prom's page table directly which is what most
1068  * other OS's do.  Yuck... this is much better.
1069  */
1070 static void __init srmmu_inherit_prom_mappings(unsigned long start,
1071                                                unsigned long end)
1072 {
1073         pgd_t *pgdp;
1074         pmd_t *pmdp;
1075         pte_t *ptep;
1076         int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
1077         unsigned long prompte;
1078
1079         while(start <= end) {
1080                 if (start == 0)
1081                         break; /* probably wrap around */
1082                 if(start == 0xfef00000)
1083                         start = KADB_DEBUGGER_BEGVM;
1084                 if(!(prompte = srmmu_hwprobe(start))) {
1085                         start += PAGE_SIZE;
1086                         continue;
1087                 }
1088
1089                 /* A red snapper, see what it really is. */
1090                 what = 0;
1091
1092                 if(!(start & ~(SRMMU_REAL_PMD_MASK))) {
1093                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_REAL_PMD_SIZE) == prompte)
1094                                 what = 1;
1095                 }
1096
1097                 if(!(start & ~(SRMMU_PGDIR_MASK))) {
1098                         if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) ==
1099                            prompte)
1100                                 what = 2;
1101                 }
1102
1103                 pgdp = pgd_offset_k(start);
1104                 if(what == 2) {
1105                         *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte);
1106                         start += SRMMU_PGDIR_SIZE;
1107                         continue;
1108                 }
1109                 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1110                         pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1111                         if (pmdp == NULL)
1112                                 early_pgtable_allocfail("pmd");
1113                         memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1114                         srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1115                 }
1116                 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1117                 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1118                         ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1119                                                              PTE_SIZE);
1120                         if (ptep == NULL)
1121                                 early_pgtable_allocfail("pte");
1122                         memset(__nocache_fix(ptep), 0, PTE_SIZE);
1123                         srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1124                 }
1125                 if(what == 1) {
1126                         /*
1127                          * We bend the rule where all 16 PTPs in a pmd_t point
1128                          * inside the same PTE page, and we leak a perfectly
1129                          * good hardware PTE piece. Alternatives seem worse.
1130                          */
1131                         unsigned int x; /* Index of HW PMD in soft cluster */
1132                         x = (start >> PMD_SHIFT) & 15;
1133                         *(unsigned long *)__nocache_fix(&pmdp->pmdv[x]) = prompte;
1134                         start += SRMMU_REAL_PMD_SIZE;
1135                         continue;
1136                 }
1137                 ptep = srmmu_pte_offset(__nocache_fix(pmdp), start);
1138                 *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
1139                 start += PAGE_SIZE;
1140         }
1141 }
1142
1143 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
1144
1145 /* Create a third-level SRMMU 16MB page mapping. */
1146 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
1147 {
1148         pgd_t *pgdp = pgd_offset_k(vaddr);
1149         unsigned long big_pte;
1150
1151         big_pte = KERNEL_PTE(phys_base >> 4);
1152         *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
1153 }
1154
1155 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
1156 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
1157 {
1158         unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
1159         unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
1160         unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
1161         /* Map "low" memory only */
1162         const unsigned long min_vaddr = PAGE_OFFSET;
1163         const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
1164
1165         if (vstart < min_vaddr || vstart >= max_vaddr)
1166                 return vstart;
1167
1168         if (vend > max_vaddr || vend < min_vaddr)
1169                 vend = max_vaddr;
1170
1171         while(vstart < vend) {
1172                 do_large_mapping(vstart, pstart);
1173                 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
1174         }
1175         return vstart;
1176 }
1177
1178 static inline void memprobe_error(char *msg)
1179 {
1180         prom_printf(msg);
1181         prom_printf("Halting now...\n");
1182         prom_halt();
1183 }
1184
1185 static inline void map_kernel(void)
1186 {
1187         int i;
1188
1189         if (phys_base > 0) {
1190                 do_large_mapping(PAGE_OFFSET, phys_base);
1191         }
1192
1193         for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1194                 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
1195         }
1196 }
1197
1198 /* Paging initialization on the Sparc Reference MMU. */
1199 extern void sparc_context_init(int);
1200
1201 void (*poke_srmmu)(void) __cpuinitdata = NULL;
1202
1203 extern unsigned long bootmem_init(unsigned long *pages_avail);
1204
1205 void __init srmmu_paging_init(void)
1206 {
1207         int i;
1208         phandle cpunode;
1209         char node_str[128];
1210         pgd_t *pgd;
1211         pmd_t *pmd;
1212         pte_t *pte;
1213         unsigned long pages_avail;
1214
1215         sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
1216
1217         if (sparc_cpu_model == sun4d)
1218                 num_contexts = 65536; /* We know it is Viking */
1219         else {
1220                 /* Find the number of contexts on the srmmu. */
1221                 cpunode = prom_getchild(prom_root_node);
1222                 num_contexts = 0;
1223                 while(cpunode != 0) {
1224                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1225                         if(!strcmp(node_str, "cpu")) {
1226                                 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
1227                                 break;
1228                         }
1229                         cpunode = prom_getsibling(cpunode);
1230                 }
1231         }
1232
1233         if(!num_contexts) {
1234                 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
1235                 prom_halt();
1236         }
1237
1238         pages_avail = 0;
1239         last_valid_pfn = bootmem_init(&pages_avail);
1240
1241         srmmu_nocache_calcsize();
1242         srmmu_nocache_init();
1243         srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE));
1244         map_kernel();
1245
1246         /* ctx table has to be physically aligned to its size */
1247         srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t));
1248         srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
1249
1250         for(i = 0; i < num_contexts; i++)
1251                 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
1252
1253         flush_cache_all();
1254         srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
1255 #ifdef CONFIG_SMP
1256         /* Stop from hanging here... */
1257         local_flush_tlb_all();
1258 #else
1259         flush_tlb_all();
1260 #endif
1261         poke_srmmu();
1262
1263         srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
1264         srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
1265
1266         srmmu_allocate_ptable_skeleton(
1267                 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
1268         srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
1269
1270         pgd = pgd_offset_k(PKMAP_BASE);
1271         pmd = srmmu_pmd_offset(pgd, PKMAP_BASE);
1272         pte = srmmu_pte_offset(pmd, PKMAP_BASE);
1273         pkmap_page_table = pte;
1274
1275         flush_cache_all();
1276         flush_tlb_all();
1277
1278         sparc_context_init(num_contexts);
1279
1280         kmap_init();
1281
1282         {
1283                 unsigned long zones_size[MAX_NR_ZONES];
1284                 unsigned long zholes_size[MAX_NR_ZONES];
1285                 unsigned long npages;
1286                 int znum;
1287
1288                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1289                         zones_size[znum] = zholes_size[znum] = 0;
1290
1291                 npages = max_low_pfn - pfn_base;
1292
1293                 zones_size[ZONE_DMA] = npages;
1294                 zholes_size[ZONE_DMA] = npages - pages_avail;
1295
1296                 npages = highend_pfn - max_low_pfn;
1297                 zones_size[ZONE_HIGHMEM] = npages;
1298                 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
1299
1300                 free_area_init_node(0, zones_size, pfn_base, zholes_size);
1301         }
1302 }
1303
1304 static void srmmu_mmu_info(struct seq_file *m)
1305 {
1306         seq_printf(m,
1307                    "MMU type\t: %s\n"
1308                    "contexts\t: %d\n"
1309                    "nocache total\t: %ld\n"
1310                    "nocache used\t: %d\n",
1311                    srmmu_name,
1312                    num_contexts,
1313                    srmmu_nocache_size,
1314                    srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
1315 }
1316
1317 static void srmmu_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
1318 {
1319 }
1320
1321 static void srmmu_destroy_context(struct mm_struct *mm)
1322 {
1323
1324         if(mm->context != NO_CONTEXT) {
1325                 flush_cache_mm(mm);
1326                 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1327                 flush_tlb_mm(mm);
1328                 spin_lock(&srmmu_context_spinlock);
1329                 free_context(mm->context);
1330                 spin_unlock(&srmmu_context_spinlock);
1331                 mm->context = NO_CONTEXT;
1332         }
1333 }
1334
1335 /* Init various srmmu chip types. */
1336 static void __init srmmu_is_bad(void)
1337 {
1338         prom_printf("Could not determine SRMMU chip type.\n");
1339         prom_halt();
1340 }
1341
1342 static void __init init_vac_layout(void)
1343 {
1344         phandle nd;
1345         int cache_lines;
1346         char node_str[128];
1347 #ifdef CONFIG_SMP
1348         int cpu = 0;
1349         unsigned long max_size = 0;
1350         unsigned long min_line_size = 0x10000000;
1351 #endif
1352
1353         nd = prom_getchild(prom_root_node);
1354         while((nd = prom_getsibling(nd)) != 0) {
1355                 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1356                 if(!strcmp(node_str, "cpu")) {
1357                         vac_line_size = prom_getint(nd, "cache-line-size");
1358                         if (vac_line_size == -1) {
1359                                 prom_printf("can't determine cache-line-size, "
1360                                             "halting.\n");
1361                                 prom_halt();
1362                         }
1363                         cache_lines = prom_getint(nd, "cache-nlines");
1364                         if (cache_lines == -1) {
1365                                 prom_printf("can't determine cache-nlines, halting.\n");
1366                                 prom_halt();
1367                         }
1368
1369                         vac_cache_size = cache_lines * vac_line_size;
1370 #ifdef CONFIG_SMP
1371                         if(vac_cache_size > max_size)
1372                                 max_size = vac_cache_size;
1373                         if(vac_line_size < min_line_size)
1374                                 min_line_size = vac_line_size;
1375                         //FIXME: cpus not contiguous!!
1376                         cpu++;
1377                         if (cpu >= nr_cpu_ids || !cpu_online(cpu))
1378                                 break;
1379 #else
1380                         break;
1381 #endif
1382                 }
1383         }
1384         if(nd == 0) {
1385                 prom_printf("No CPU nodes found, halting.\n");
1386                 prom_halt();
1387         }
1388 #ifdef CONFIG_SMP
1389         vac_cache_size = max_size;
1390         vac_line_size = min_line_size;
1391 #endif
1392         printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1393                (int)vac_cache_size, (int)vac_line_size);
1394 }
1395
1396 static void __cpuinit poke_hypersparc(void)
1397 {
1398         volatile unsigned long clear;
1399         unsigned long mreg = srmmu_get_mmureg();
1400
1401         hyper_flush_unconditional_combined();
1402
1403         mreg &= ~(HYPERSPARC_CWENABLE);
1404         mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1405         mreg |= (HYPERSPARC_CMODE);
1406
1407         srmmu_set_mmureg(mreg);
1408
1409 #if 0 /* XXX I think this is bad news... -DaveM */
1410         hyper_clear_all_tags();
1411 #endif
1412
1413         put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1414         hyper_flush_whole_icache();
1415         clear = srmmu_get_faddr();
1416         clear = srmmu_get_fstatus();
1417 }
1418
1419 static void __init init_hypersparc(void)
1420 {
1421         srmmu_name = "ROSS HyperSparc";
1422         srmmu_modtype = HyperSparc;
1423
1424         init_vac_layout();
1425
1426         is_hypersparc = 1;
1427
1428         BTFIXUPSET_CALL(flush_cache_all, hypersparc_flush_cache_all, BTFIXUPCALL_NORM);
1429         BTFIXUPSET_CALL(flush_cache_mm, hypersparc_flush_cache_mm, BTFIXUPCALL_NORM);
1430         BTFIXUPSET_CALL(flush_cache_range, hypersparc_flush_cache_range, BTFIXUPCALL_NORM);
1431         BTFIXUPSET_CALL(flush_cache_page, hypersparc_flush_cache_page, BTFIXUPCALL_NORM);
1432
1433         BTFIXUPSET_CALL(flush_tlb_all, hypersparc_flush_tlb_all, BTFIXUPCALL_NORM);
1434         BTFIXUPSET_CALL(flush_tlb_mm, hypersparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1435         BTFIXUPSET_CALL(flush_tlb_range, hypersparc_flush_tlb_range, BTFIXUPCALL_NORM);
1436         BTFIXUPSET_CALL(flush_tlb_page, hypersparc_flush_tlb_page, BTFIXUPCALL_NORM);
1437
1438         BTFIXUPSET_CALL(__flush_page_to_ram, hypersparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1439         BTFIXUPSET_CALL(flush_sig_insns, hypersparc_flush_sig_insns, BTFIXUPCALL_NORM);
1440         BTFIXUPSET_CALL(flush_page_for_dma, hypersparc_flush_page_for_dma, BTFIXUPCALL_NOP);
1441
1442
1443         poke_srmmu = poke_hypersparc;
1444
1445         hypersparc_setup_blockops();
1446 }
1447
1448 static void __cpuinit poke_cypress(void)
1449 {
1450         unsigned long mreg = srmmu_get_mmureg();
1451         unsigned long faddr, tagval;
1452         volatile unsigned long cypress_sucks;
1453         volatile unsigned long clear;
1454
1455         clear = srmmu_get_faddr();
1456         clear = srmmu_get_fstatus();
1457
1458         if (!(mreg & CYPRESS_CENABLE)) {
1459                 for(faddr = 0x0; faddr < 0x10000; faddr += 20) {
1460                         __asm__ __volatile__("sta %%g0, [%0 + %1] %2\n\t"
1461                                              "sta %%g0, [%0] %2\n\t" : :
1462                                              "r" (faddr), "r" (0x40000),
1463                                              "i" (ASI_M_DATAC_TAG));
1464                 }
1465         } else {
1466                 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
1467                         __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
1468                                              "=r" (tagval) :
1469                                              "r" (faddr), "r" (0x40000),
1470                                              "i" (ASI_M_DATAC_TAG));
1471
1472                         /* If modified and valid, kick it. */
1473                         if((tagval & 0x60) == 0x60)
1474                                 cypress_sucks = *(unsigned long *)
1475                                                         (0xf0020000 + faddr);
1476                 }
1477         }
1478
1479         /* And one more, for our good neighbor, Mr. Broken Cypress. */
1480         clear = srmmu_get_faddr();
1481         clear = srmmu_get_fstatus();
1482
1483         mreg |= (CYPRESS_CENABLE | CYPRESS_CMODE);
1484         srmmu_set_mmureg(mreg);
1485 }
1486
1487 static void __init init_cypress_common(void)
1488 {
1489         init_vac_layout();
1490
1491         BTFIXUPSET_CALL(flush_cache_all, cypress_flush_cache_all, BTFIXUPCALL_NORM);
1492         BTFIXUPSET_CALL(flush_cache_mm, cypress_flush_cache_mm, BTFIXUPCALL_NORM);
1493         BTFIXUPSET_CALL(flush_cache_range, cypress_flush_cache_range, BTFIXUPCALL_NORM);
1494         BTFIXUPSET_CALL(flush_cache_page, cypress_flush_cache_page, BTFIXUPCALL_NORM);
1495
1496         BTFIXUPSET_CALL(flush_tlb_all, cypress_flush_tlb_all, BTFIXUPCALL_NORM);
1497         BTFIXUPSET_CALL(flush_tlb_mm, cypress_flush_tlb_mm, BTFIXUPCALL_NORM);
1498         BTFIXUPSET_CALL(flush_tlb_page, cypress_flush_tlb_page, BTFIXUPCALL_NORM);
1499         BTFIXUPSET_CALL(flush_tlb_range, cypress_flush_tlb_range, BTFIXUPCALL_NORM);
1500
1501
1502         BTFIXUPSET_CALL(__flush_page_to_ram, cypress_flush_page_to_ram, BTFIXUPCALL_NORM);
1503         BTFIXUPSET_CALL(flush_sig_insns, cypress_flush_sig_insns, BTFIXUPCALL_NOP);
1504         BTFIXUPSET_CALL(flush_page_for_dma, cypress_flush_page_for_dma, BTFIXUPCALL_NOP);
1505
1506         poke_srmmu = poke_cypress;
1507 }
1508
1509 static void __init init_cypress_604(void)
1510 {
1511         srmmu_name = "ROSS Cypress-604(UP)";
1512         srmmu_modtype = Cypress;
1513         init_cypress_common();
1514 }
1515
1516 static void __init init_cypress_605(unsigned long mrev)
1517 {
1518         srmmu_name = "ROSS Cypress-605(MP)";
1519         if(mrev == 0xe) {
1520                 srmmu_modtype = Cypress_vE;
1521                 hwbug_bitmask |= HWBUG_COPYBACK_BROKEN;
1522         } else {
1523                 if(mrev == 0xd) {
1524                         srmmu_modtype = Cypress_vD;
1525                         hwbug_bitmask |= HWBUG_ASIFLUSH_BROKEN;
1526                 } else {
1527                         srmmu_modtype = Cypress;
1528                 }
1529         }
1530         init_cypress_common();
1531 }
1532
1533 static void __cpuinit poke_swift(void)
1534 {
1535         unsigned long mreg;
1536
1537         /* Clear any crap from the cache or else... */
1538         swift_flush_cache_all();
1539
1540         /* Enable I & D caches */
1541         mreg = srmmu_get_mmureg();
1542         mreg |= (SWIFT_IE | SWIFT_DE);
1543         /*
1544          * The Swift branch folding logic is completely broken.  At
1545          * trap time, if things are just right, if can mistakenly
1546          * think that a trap is coming from kernel mode when in fact
1547          * it is coming from user mode (it mis-executes the branch in
1548          * the trap code).  So you see things like crashme completely
1549          * hosing your machine which is completely unacceptable.  Turn
1550          * this shit off... nice job Fujitsu.
1551          */
1552         mreg &= ~(SWIFT_BF);
1553         srmmu_set_mmureg(mreg);
1554 }
1555
1556 #define SWIFT_MASKID_ADDR  0x10003018
1557 static void __init init_swift(void)
1558 {
1559         unsigned long swift_rev;
1560
1561         __asm__ __volatile__("lda [%1] %2, %0\n\t"
1562                              "srl %0, 0x18, %0\n\t" :
1563                              "=r" (swift_rev) :
1564                              "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1565         srmmu_name = "Fujitsu Swift";
1566         switch(swift_rev) {
1567         case 0x11:
1568         case 0x20:
1569         case 0x23:
1570         case 0x30:
1571                 srmmu_modtype = Swift_lots_o_bugs;
1572                 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1573                 /*
1574                  * Gee george, I wonder why Sun is so hush hush about
1575                  * this hardware bug... really braindamage stuff going
1576                  * on here.  However I think we can find a way to avoid
1577                  * all of the workaround overhead under Linux.  Basically,
1578                  * any page fault can cause kernel pages to become user
1579                  * accessible (the mmu gets confused and clears some of
1580                  * the ACC bits in kernel ptes).  Aha, sounds pretty
1581                  * horrible eh?  But wait, after extensive testing it appears
1582                  * that if you use pgd_t level large kernel pte's (like the
1583                  * 4MB pages on the Pentium) the bug does not get tripped
1584                  * at all.  This avoids almost all of the major overhead.
1585                  * Welcome to a world where your vendor tells you to,
1586                  * "apply this kernel patch" instead of "sorry for the
1587                  * broken hardware, send it back and we'll give you
1588                  * properly functioning parts"
1589                  */
1590                 break;
1591         case 0x25:
1592         case 0x31:
1593                 srmmu_modtype = Swift_bad_c;
1594                 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1595                 /*
1596                  * You see Sun allude to this hardware bug but never
1597                  * admit things directly, they'll say things like,
1598                  * "the Swift chip cache problems" or similar.
1599                  */
1600                 break;
1601         default:
1602                 srmmu_modtype = Swift_ok;
1603                 break;
1604         }
1605
1606         BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
1607         BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
1608         BTFIXUPSET_CALL(flush_cache_page, swift_flush_cache_page, BTFIXUPCALL_NORM);
1609         BTFIXUPSET_CALL(flush_cache_range, swift_flush_cache_range, BTFIXUPCALL_NORM);
1610
1611
1612         BTFIXUPSET_CALL(flush_tlb_all, swift_flush_tlb_all, BTFIXUPCALL_NORM);
1613         BTFIXUPSET_CALL(flush_tlb_mm, swift_flush_tlb_mm, BTFIXUPCALL_NORM);
1614         BTFIXUPSET_CALL(flush_tlb_page, swift_flush_tlb_page, BTFIXUPCALL_NORM);
1615         BTFIXUPSET_CALL(flush_tlb_range, swift_flush_tlb_range, BTFIXUPCALL_NORM);
1616
1617         BTFIXUPSET_CALL(__flush_page_to_ram, swift_flush_page_to_ram, BTFIXUPCALL_NORM);
1618         BTFIXUPSET_CALL(flush_sig_insns, swift_flush_sig_insns, BTFIXUPCALL_NORM);
1619         BTFIXUPSET_CALL(flush_page_for_dma, swift_flush_page_for_dma, BTFIXUPCALL_NORM);
1620
1621         BTFIXUPSET_CALL(update_mmu_cache, swift_update_mmu_cache, BTFIXUPCALL_NORM);
1622
1623         flush_page_for_dma_global = 0;
1624
1625         /*
1626          * Are you now convinced that the Swift is one of the
1627          * biggest VLSI abortions of all time?  Bravo Fujitsu!
1628          * Fujitsu, the !#?!%$'d up processor people.  I bet if
1629          * you examined the microcode of the Swift you'd find
1630          * XXX's all over the place.
1631          */
1632         poke_srmmu = poke_swift;
1633 }
1634
1635 static void turbosparc_flush_cache_all(void)
1636 {
1637         flush_user_windows();
1638         turbosparc_idflash_clear();
1639 }
1640
1641 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1642 {
1643         FLUSH_BEGIN(mm)
1644         flush_user_windows();
1645         turbosparc_idflash_clear();
1646         FLUSH_END
1647 }
1648
1649 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1650 {
1651         FLUSH_BEGIN(vma->vm_mm)
1652         flush_user_windows();
1653         turbosparc_idflash_clear();
1654         FLUSH_END
1655 }
1656
1657 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1658 {
1659         FLUSH_BEGIN(vma->vm_mm)
1660         flush_user_windows();
1661         if (vma->vm_flags & VM_EXEC)
1662                 turbosparc_flush_icache();
1663         turbosparc_flush_dcache();
1664         FLUSH_END
1665 }
1666
1667 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1668 static void turbosparc_flush_page_to_ram(unsigned long page)
1669 {
1670 #ifdef TURBOSPARC_WRITEBACK
1671         volatile unsigned long clear;
1672
1673         if (srmmu_hwprobe(page))
1674                 turbosparc_flush_page_cache(page);
1675         clear = srmmu_get_fstatus();
1676 #endif
1677 }
1678
1679 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1680 {
1681 }
1682
1683 static void turbosparc_flush_page_for_dma(unsigned long page)
1684 {
1685         turbosparc_flush_dcache();
1686 }
1687
1688 static void turbosparc_flush_tlb_all(void)
1689 {
1690         srmmu_flush_whole_tlb();
1691 }
1692
1693 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1694 {
1695         FLUSH_BEGIN(mm)
1696         srmmu_flush_whole_tlb();
1697         FLUSH_END
1698 }
1699
1700 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1701 {
1702         FLUSH_BEGIN(vma->vm_mm)
1703         srmmu_flush_whole_tlb();
1704         FLUSH_END
1705 }
1706
1707 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1708 {
1709         FLUSH_BEGIN(vma->vm_mm)
1710         srmmu_flush_whole_tlb();
1711         FLUSH_END
1712 }
1713
1714
1715 static void __cpuinit poke_turbosparc(void)
1716 {
1717         unsigned long mreg = srmmu_get_mmureg();
1718         unsigned long ccreg;
1719
1720         /* Clear any crap from the cache or else... */
1721         turbosparc_flush_cache_all();
1722         mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */
1723         mreg &= ~(TURBOSPARC_PCENABLE);         /* Don't check parity */
1724         srmmu_set_mmureg(mreg);
1725
1726         ccreg = turbosparc_get_ccreg();
1727
1728 #ifdef TURBOSPARC_WRITEBACK
1729         ccreg |= (TURBOSPARC_SNENABLE);         /* Do DVMA snooping in Dcache */
1730         ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1731                         /* Write-back D-cache, emulate VLSI
1732                          * abortion number three, not number one */
1733 #else
1734         /* For now let's play safe, optimize later */
1735         ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1736                         /* Do DVMA snooping in Dcache, Write-thru D-cache */
1737         ccreg &= ~(TURBOSPARC_uS2);
1738                         /* Emulate VLSI abortion number three, not number one */
1739 #endif
1740
1741         switch (ccreg & 7) {
1742         case 0: /* No SE cache */
1743         case 7: /* Test mode */
1744                 break;
1745         default:
1746                 ccreg |= (TURBOSPARC_SCENABLE);
1747         }
1748         turbosparc_set_ccreg (ccreg);
1749
1750         mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1751         mreg |= (TURBOSPARC_ICSNOOP);           /* Icache snooping on */
1752         srmmu_set_mmureg(mreg);
1753 }
1754
1755 static void __init init_turbosparc(void)
1756 {
1757         srmmu_name = "Fujitsu TurboSparc";
1758         srmmu_modtype = TurboSparc;
1759
1760         BTFIXUPSET_CALL(flush_cache_all, turbosparc_flush_cache_all, BTFIXUPCALL_NORM);
1761         BTFIXUPSET_CALL(flush_cache_mm, turbosparc_flush_cache_mm, BTFIXUPCALL_NORM);
1762         BTFIXUPSET_CALL(flush_cache_page, turbosparc_flush_cache_page, BTFIXUPCALL_NORM);
1763         BTFIXUPSET_CALL(flush_cache_range, turbosparc_flush_cache_range, BTFIXUPCALL_NORM);
1764
1765         BTFIXUPSET_CALL(flush_tlb_all, turbosparc_flush_tlb_all, BTFIXUPCALL_NORM);
1766         BTFIXUPSET_CALL(flush_tlb_mm, turbosparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1767         BTFIXUPSET_CALL(flush_tlb_page, turbosparc_flush_tlb_page, BTFIXUPCALL_NORM);
1768         BTFIXUPSET_CALL(flush_tlb_range, turbosparc_flush_tlb_range, BTFIXUPCALL_NORM);
1769
1770         BTFIXUPSET_CALL(__flush_page_to_ram, turbosparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1771
1772         BTFIXUPSET_CALL(flush_sig_insns, turbosparc_flush_sig_insns, BTFIXUPCALL_NOP);
1773         BTFIXUPSET_CALL(flush_page_for_dma, turbosparc_flush_page_for_dma, BTFIXUPCALL_NORM);
1774
1775         poke_srmmu = poke_turbosparc;
1776 }
1777
1778 static void __cpuinit poke_tsunami(void)
1779 {
1780         unsigned long mreg = srmmu_get_mmureg();
1781
1782         tsunami_flush_icache();
1783         tsunami_flush_dcache();
1784         mreg &= ~TSUNAMI_ITD;
1785         mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1786         srmmu_set_mmureg(mreg);
1787 }
1788
1789 static void __init init_tsunami(void)
1790 {
1791         /*
1792          * Tsunami's pretty sane, Sun and TI actually got it
1793          * somewhat right this time.  Fujitsu should have
1794          * taken some lessons from them.
1795          */
1796
1797         srmmu_name = "TI Tsunami";
1798         srmmu_modtype = Tsunami;
1799
1800         BTFIXUPSET_CALL(flush_cache_all, tsunami_flush_cache_all, BTFIXUPCALL_NORM);
1801         BTFIXUPSET_CALL(flush_cache_mm, tsunami_flush_cache_mm, BTFIXUPCALL_NORM);
1802         BTFIXUPSET_CALL(flush_cache_page, tsunami_flush_cache_page, BTFIXUPCALL_NORM);
1803         BTFIXUPSET_CALL(flush_cache_range, tsunami_flush_cache_range, BTFIXUPCALL_NORM);
1804
1805
1806         BTFIXUPSET_CALL(flush_tlb_all, tsunami_flush_tlb_all, BTFIXUPCALL_NORM);
1807         BTFIXUPSET_CALL(flush_tlb_mm, tsunami_flush_tlb_mm, BTFIXUPCALL_NORM);
1808         BTFIXUPSET_CALL(flush_tlb_page, tsunami_flush_tlb_page, BTFIXUPCALL_NORM);
1809         BTFIXUPSET_CALL(flush_tlb_range, tsunami_flush_tlb_range, BTFIXUPCALL_NORM);
1810
1811         BTFIXUPSET_CALL(__flush_page_to_ram, tsunami_flush_page_to_ram, BTFIXUPCALL_NOP);
1812         BTFIXUPSET_CALL(flush_sig_insns, tsunami_flush_sig_insns, BTFIXUPCALL_NORM);
1813         BTFIXUPSET_CALL(flush_page_for_dma, tsunami_flush_page_for_dma, BTFIXUPCALL_NORM);
1814
1815         poke_srmmu = poke_tsunami;
1816
1817         tsunami_setup_blockops();
1818 }
1819
1820 static void __cpuinit poke_viking(void)
1821 {
1822         unsigned long mreg = srmmu_get_mmureg();
1823         static int smp_catch;
1824
1825         if(viking_mxcc_present) {
1826                 unsigned long mxcc_control = mxcc_get_creg();
1827
1828                 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1829                 mxcc_control &= ~(MXCC_CTL_RRC);
1830                 mxcc_set_creg(mxcc_control);
1831
1832                 /*
1833                  * We don't need memory parity checks.
1834                  * XXX This is a mess, have to dig out later. ecd.
1835                 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1836                  */
1837
1838                 /* We do cache ptables on MXCC. */
1839                 mreg |= VIKING_TCENABLE;
1840         } else {
1841                 unsigned long bpreg;
1842
1843                 mreg &= ~(VIKING_TCENABLE);
1844                 if(smp_catch++) {
1845                         /* Must disable mixed-cmd mode here for other cpu's. */
1846                         bpreg = viking_get_bpreg();
1847                         bpreg &= ~(VIKING_ACTION_MIX);
1848                         viking_set_bpreg(bpreg);
1849
1850                         /* Just in case PROM does something funny. */
1851                         msi_set_sync();
1852                 }
1853         }
1854
1855         mreg |= VIKING_SPENABLE;
1856         mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1857         mreg |= VIKING_SBENABLE;
1858         mreg &= ~(VIKING_ACENABLE);
1859         srmmu_set_mmureg(mreg);
1860 }
1861
1862 static void __init init_viking(void)
1863 {
1864         unsigned long mreg = srmmu_get_mmureg();
1865
1866         /* Ahhh, the viking.  SRMMU VLSI abortion number two... */
1867         if(mreg & VIKING_MMODE) {
1868                 srmmu_name = "TI Viking";
1869                 viking_mxcc_present = 0;
1870                 msi_set_sync();
1871
1872                 /*
1873                  * We need this to make sure old viking takes no hits
1874                  * on it's cache for dma snoops to workaround the
1875                  * "load from non-cacheable memory" interrupt bug.
1876                  * This is only necessary because of the new way in
1877                  * which we use the IOMMU.
1878                  */
1879                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page, BTFIXUPCALL_NORM);
1880
1881                 flush_page_for_dma_global = 0;
1882         } else {
1883                 srmmu_name = "TI Viking/MXCC";
1884                 viking_mxcc_present = 1;
1885
1886                 srmmu_cache_pagetables = 1;
1887
1888                 /* MXCC vikings lack the DMA snooping bug. */
1889                 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page_for_dma, BTFIXUPCALL_NOP);
1890         }
1891
1892         BTFIXUPSET_CALL(flush_cache_all, viking_flush_cache_all, BTFIXUPCALL_NORM);
1893         BTFIXUPSET_CALL(flush_cache_mm, viking_flush_cache_mm, BTFIXUPCALL_NORM);
1894         BTFIXUPSET_CALL(flush_cache_page, viking_flush_cache_page, BTFIXUPCALL_NORM);
1895         BTFIXUPSET_CALL(flush_cache_range, viking_flush_cache_range, BTFIXUPCALL_NORM);
1896
1897 #ifdef CONFIG_SMP
1898         if (sparc_cpu_model == sun4d) {
1899                 BTFIXUPSET_CALL(flush_tlb_all, sun4dsmp_flush_tlb_all, BTFIXUPCALL_NORM);
1900                 BTFIXUPSET_CALL(flush_tlb_mm, sun4dsmp_flush_tlb_mm, BTFIXUPCALL_NORM);
1901                 BTFIXUPSET_CALL(flush_tlb_page, sun4dsmp_flush_tlb_page, BTFIXUPCALL_NORM);
1902                 BTFIXUPSET_CALL(flush_tlb_range, sun4dsmp_flush_tlb_range, BTFIXUPCALL_NORM);
1903         } else
1904 #endif
1905         {
1906                 BTFIXUPSET_CALL(flush_tlb_all, viking_flush_tlb_all, BTFIXUPCALL_NORM);
1907                 BTFIXUPSET_CALL(flush_tlb_mm, viking_flush_tlb_mm, BTFIXUPCALL_NORM);
1908                 BTFIXUPSET_CALL(flush_tlb_page, viking_flush_tlb_page, BTFIXUPCALL_NORM);
1909                 BTFIXUPSET_CALL(flush_tlb_range, viking_flush_tlb_range, BTFIXUPCALL_NORM);
1910         }
1911
1912         BTFIXUPSET_CALL(__flush_page_to_ram, viking_flush_page_to_ram, BTFIXUPCALL_NOP);
1913         BTFIXUPSET_CALL(flush_sig_insns, viking_flush_sig_insns, BTFIXUPCALL_NOP);
1914
1915         poke_srmmu = poke_viking;
1916 }
1917
1918 #ifdef CONFIG_SPARC_LEON
1919
1920 void __init poke_leonsparc(void)
1921 {
1922 }
1923
1924 void __init init_leon(void)
1925 {
1926
1927         srmmu_name = "LEON";
1928
1929         BTFIXUPSET_CALL(flush_cache_all, leon_flush_cache_all,
1930                         BTFIXUPCALL_NORM);
1931         BTFIXUPSET_CALL(flush_cache_mm, leon_flush_cache_all,
1932                         BTFIXUPCALL_NORM);
1933         BTFIXUPSET_CALL(flush_cache_page, leon_flush_pcache_all,
1934                         BTFIXUPCALL_NORM);
1935         BTFIXUPSET_CALL(flush_cache_range, leon_flush_cache_all,
1936                         BTFIXUPCALL_NORM);
1937         BTFIXUPSET_CALL(flush_page_for_dma, leon_flush_dcache_all,
1938                         BTFIXUPCALL_NORM);
1939
1940         BTFIXUPSET_CALL(flush_tlb_all, leon_flush_tlb_all, BTFIXUPCALL_NORM);
1941         BTFIXUPSET_CALL(flush_tlb_mm, leon_flush_tlb_all, BTFIXUPCALL_NORM);
1942         BTFIXUPSET_CALL(flush_tlb_page, leon_flush_tlb_all, BTFIXUPCALL_NORM);
1943         BTFIXUPSET_CALL(flush_tlb_range, leon_flush_tlb_all, BTFIXUPCALL_NORM);
1944
1945         BTFIXUPSET_CALL(__flush_page_to_ram, leon_flush_cache_all,
1946                         BTFIXUPCALL_NOP);
1947         BTFIXUPSET_CALL(flush_sig_insns, leon_flush_cache_all, BTFIXUPCALL_NOP);
1948
1949         poke_srmmu = poke_leonsparc;
1950
1951         srmmu_cache_pagetables = 0;
1952
1953         leon_flush_during_switch = leon_flush_needed();
1954 }
1955 #endif
1956
1957 /* Probe for the srmmu chip version. */
1958 static void __init get_srmmu_type(void)
1959 {
1960         unsigned long mreg, psr;
1961         unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1962
1963         srmmu_modtype = SRMMU_INVAL_MOD;
1964         hwbug_bitmask = 0;
1965
1966         mreg = srmmu_get_mmureg(); psr = get_psr();
1967         mod_typ = (mreg & 0xf0000000) >> 28;
1968         mod_rev = (mreg & 0x0f000000) >> 24;
1969         psr_typ = (psr >> 28) & 0xf;
1970         psr_vers = (psr >> 24) & 0xf;
1971
1972         /* First, check for sparc-leon. */
1973         if (sparc_cpu_model == sparc_leon) {
1974                 init_leon();
1975                 return;
1976         }
1977
1978         /* Second, check for HyperSparc or Cypress. */
1979         if(mod_typ == 1) {
1980                 switch(mod_rev) {
1981                 case 7:
1982                         /* UP or MP Hypersparc */
1983                         init_hypersparc();
1984                         break;
1985                 case 0:
1986                 case 2:
1987                         /* Uniprocessor Cypress */
1988                         init_cypress_604();
1989                         break;
1990                 case 10:
1991                 case 11:
1992                 case 12:
1993                         /* _REALLY OLD_ Cypress MP chips... */
1994                 case 13:
1995                 case 14:
1996                 case 15:
1997                         /* MP Cypress mmu/cache-controller */
1998                         init_cypress_605(mod_rev);
1999                         break;
2000                 default:
2001                         /* Some other Cypress revision, assume a 605. */
2002                         init_cypress_605(mod_rev);
2003                         break;
2004                 }
2005                 return;
2006         }
2007
2008         /*
2009          * Now Fujitsu TurboSparc. It might happen that it is
2010          * in Swift emulation mode, so we will check later...
2011          */
2012         if (psr_typ == 0 && psr_vers == 5) {
2013                 init_turbosparc();
2014                 return;
2015         }
2016
2017         /* Next check for Fujitsu Swift. */
2018         if(psr_typ == 0 && psr_vers == 4) {
2019                 phandle cpunode;
2020                 char node_str[128];
2021
2022                 /* Look if it is not a TurboSparc emulating Swift... */
2023                 cpunode = prom_getchild(prom_root_node);
2024                 while((cpunode = prom_getsibling(cpunode)) != 0) {
2025                         prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
2026                         if(!strcmp(node_str, "cpu")) {
2027                                 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
2028                                     prom_getintdefault(cpunode, "psr-version", 1) == 5) {
2029                                         init_turbosparc();
2030                                         return;
2031                                 }
2032                                 break;
2033                         }
2034                 }
2035
2036                 init_swift();
2037                 return;
2038         }
2039
2040         /* Now the Viking family of srmmu. */
2041         if(psr_typ == 4 &&
2042            ((psr_vers == 0) ||
2043             ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
2044                 init_viking();
2045                 return;
2046         }
2047
2048         /* Finally the Tsunami. */
2049         if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
2050                 init_tsunami();
2051                 return;
2052         }
2053
2054         /* Oh well */
2055         srmmu_is_bad();
2056 }
2057
2058 extern unsigned long spwin_mmu_patchme, fwin_mmu_patchme,
2059         tsetup_mmu_patchme, rtrap_mmu_patchme;
2060
2061 extern unsigned long spwin_srmmu_stackchk, srmmu_fwin_stackchk,
2062         tsetup_srmmu_stackchk, srmmu_rett_stackchk;
2063
2064 #ifdef CONFIG_SMP
2065 /* Local cross-calls. */
2066 static void smp_flush_page_for_dma(unsigned long page)
2067 {
2068         xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_for_dma), page);
2069         local_flush_page_for_dma(page);
2070 }
2071
2072 #endif
2073
2074 /* Load up routines and constants for sun4m and sun4d mmu */
2075 void __init ld_mmu_srmmu(void)
2076 {
2077         extern void ld_mmu_iommu(void);
2078         extern void ld_mmu_iounit(void);
2079         extern void ___xchg32_sun4md(void);
2080
2081         BTFIXUPSET_INT(page_none, pgprot_val(SRMMU_PAGE_NONE));
2082         PAGE_SHARED = pgprot_val(SRMMU_PAGE_SHARED);
2083         BTFIXUPSET_INT(page_copy, pgprot_val(SRMMU_PAGE_COPY));
2084         BTFIXUPSET_INT(page_readonly, pgprot_val(SRMMU_PAGE_RDONLY));
2085         BTFIXUPSET_INT(page_kernel, pgprot_val(SRMMU_PAGE_KERNEL));
2086         page_kernel = pgprot_val(SRMMU_PAGE_KERNEL);
2087
2088         /* Functions */
2089 #ifndef CONFIG_SMP
2090         BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4md, BTFIXUPCALL_SWAPG1G2);
2091 #endif
2092
2093         BTFIXUPSET_CALL(set_pte, srmmu_set_pte, BTFIXUPCALL_SWAPO0O1);
2094
2095         BTFIXUPSET_CALL(pgd_page_vaddr, srmmu_pgd_page, BTFIXUPCALL_NORM);
2096
2097         BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM);
2098
2099         BTFIXUPSET_CALL(pmd_bad, srmmu_pmd_bad, BTFIXUPCALL_NORM);
2100         BTFIXUPSET_CALL(pmd_present, srmmu_pmd_present, BTFIXUPCALL_NORM);
2101
2102         BTFIXUPSET_CALL(pgd_none, srmmu_pgd_none, BTFIXUPCALL_NORM);
2103         BTFIXUPSET_CALL(pgd_bad, srmmu_pgd_bad, BTFIXUPCALL_NORM);
2104         BTFIXUPSET_CALL(pgd_present, srmmu_pgd_present, BTFIXUPCALL_NORM);
2105
2106         BTFIXUPSET_CALL(mk_pte, srmmu_mk_pte, BTFIXUPCALL_NORM);
2107         BTFIXUPSET_CALL(mk_pte_phys, srmmu_mk_pte_phys, BTFIXUPCALL_NORM);
2108         BTFIXUPSET_CALL(mk_pte_io, srmmu_mk_pte_io, BTFIXUPCALL_NORM);
2109         BTFIXUPSET_CALL(pgd_set, srmmu_pgd_set, BTFIXUPCALL_NORM);
2110         BTFIXUPSET_CALL(pmd_set, srmmu_pmd_set, BTFIXUPCALL_NORM);
2111         BTFIXUPSET_CALL(pmd_populate, srmmu_pmd_populate, BTFIXUPCALL_NORM);
2112
2113         BTFIXUPSET_INT(pte_modify_mask, SRMMU_CHG_MASK);
2114         BTFIXUPSET_CALL(pmd_offset, srmmu_pmd_offset, BTFIXUPCALL_NORM);
2115         BTFIXUPSET_CALL(pte_offset_kernel, srmmu_pte_offset, BTFIXUPCALL_NORM);
2116
2117         BTFIXUPSET_CALL(free_pte_fast, srmmu_free_pte_fast, BTFIXUPCALL_NORM);
2118         BTFIXUPSET_CALL(pte_free, srmmu_pte_free, BTFIXUPCALL_NORM);
2119         BTFIXUPSET_CALL(pte_alloc_one_kernel, srmmu_pte_alloc_one_kernel, BTFIXUPCALL_NORM);
2120         BTFIXUPSET_CALL(pte_alloc_one, srmmu_pte_alloc_one, BTFIXUPCALL_NORM);
2121         BTFIXUPSET_CALL(free_pmd_fast, srmmu_pmd_free, BTFIXUPCALL_NORM);
2122         BTFIXUPSET_CALL(pmd_alloc_one, srmmu_pmd_alloc_one, BTFIXUPCALL_NORM);
2123         BTFIXUPSET_CALL(free_pgd_fast, srmmu_free_pgd_fast, BTFIXUPCALL_NORM);
2124         BTFIXUPSET_CALL(get_pgd_fast, srmmu_get_pgd_fast, BTFIXUPCALL_NORM);
2125
2126         BTFIXUPSET_HALF(pte_writei, SRMMU_WRITE);
2127         BTFIXUPSET_HALF(pte_dirtyi, SRMMU_DIRTY);
2128         BTFIXUPSET_HALF(pte_youngi, SRMMU_REF);
2129         BTFIXUPSET_HALF(pte_filei, SRMMU_FILE);
2130         BTFIXUPSET_HALF(pte_wrprotecti, SRMMU_WRITE);
2131         BTFIXUPSET_HALF(pte_mkcleani, SRMMU_DIRTY);
2132         BTFIXUPSET_HALF(pte_mkoldi, SRMMU_REF);
2133         BTFIXUPSET_CALL(pte_mkwrite, srmmu_pte_mkwrite, BTFIXUPCALL_ORINT(SRMMU_WRITE));
2134         BTFIXUPSET_CALL(pte_mkdirty, srmmu_pte_mkdirty, BTFIXUPCALL_ORINT(SRMMU_DIRTY));
2135         BTFIXUPSET_CALL(pte_mkyoung, srmmu_pte_mkyoung, BTFIXUPCALL_ORINT(SRMMU_REF));
2136         BTFIXUPSET_CALL(update_mmu_cache, srmmu_update_mmu_cache, BTFIXUPCALL_NOP);
2137         BTFIXUPSET_CALL(destroy_context, srmmu_destroy_context, BTFIXUPCALL_NORM);
2138
2139         BTFIXUPSET_CALL(sparc_mapiorange, srmmu_mapiorange, BTFIXUPCALL_NORM);
2140         BTFIXUPSET_CALL(sparc_unmapiorange, srmmu_unmapiorange, BTFIXUPCALL_NORM);
2141
2142         BTFIXUPSET_CALL(__swp_type, srmmu_swp_type, BTFIXUPCALL_NORM);
2143         BTFIXUPSET_CALL(__swp_offset, srmmu_swp_offset, BTFIXUPCALL_NORM);
2144         BTFIXUPSET_CALL(__swp_entry, srmmu_swp_entry, BTFIXUPCALL_NORM);
2145
2146         BTFIXUPSET_CALL(mmu_info, srmmu_mmu_info, BTFIXUPCALL_NORM);
2147
2148         get_srmmu_type();
2149
2150 #ifdef CONFIG_SMP
2151         /* El switcheroo... */
2152
2153         BTFIXUPCOPY_CALL(local_flush_cache_all, flush_cache_all);
2154         BTFIXUPCOPY_CALL(local_flush_cache_mm, flush_cache_mm);
2155         BTFIXUPCOPY_CALL(local_flush_cache_range, flush_cache_range);
2156         BTFIXUPCOPY_CALL(local_flush_cache_page, flush_cache_page);
2157         BTFIXUPCOPY_CALL(local_flush_tlb_all, flush_tlb_all);
2158         BTFIXUPCOPY_CALL(local_flush_tlb_mm, flush_tlb_mm);
2159         BTFIXUPCOPY_CALL(local_flush_tlb_range, flush_tlb_range);
2160         BTFIXUPCOPY_CALL(local_flush_tlb_page, flush_tlb_page);
2161         BTFIXUPCOPY_CALL(local_flush_page_to_ram, __flush_page_to_ram);
2162         BTFIXUPCOPY_CALL(local_flush_sig_insns, flush_sig_insns);
2163         BTFIXUPCOPY_CALL(local_flush_page_for_dma, flush_page_for_dma);
2164
2165         BTFIXUPSET_CALL(flush_cache_all, smp_flush_cache_all, BTFIXUPCALL_NORM);
2166         BTFIXUPSET_CALL(flush_cache_mm, smp_flush_cache_mm, BTFIXUPCALL_NORM);
2167         BTFIXUPSET_CALL(flush_cache_range, smp_flush_cache_range, BTFIXUPCALL_NORM);
2168         BTFIXUPSET_CALL(flush_cache_page, smp_flush_cache_page, BTFIXUPCALL_NORM);
2169         if (sparc_cpu_model != sun4d &&
2170             sparc_cpu_model != sparc_leon) {
2171                 BTFIXUPSET_CALL(flush_tlb_all, smp_flush_tlb_all, BTFIXUPCALL_NORM);
2172                 BTFIXUPSET_CALL(flush_tlb_mm, smp_flush_tlb_mm, BTFIXUPCALL_NORM);
2173                 BTFIXUPSET_CALL(flush_tlb_range, smp_flush_tlb_range, BTFIXUPCALL_NORM);
2174                 BTFIXUPSET_CALL(flush_tlb_page, smp_flush_tlb_page, BTFIXUPCALL_NORM);
2175         }
2176         BTFIXUPSET_CALL(__flush_page_to_ram, smp_flush_page_to_ram, BTFIXUPCALL_NORM);
2177         BTFIXUPSET_CALL(flush_sig_insns, smp_flush_sig_insns, BTFIXUPCALL_NORM);
2178         BTFIXUPSET_CALL(flush_page_for_dma, smp_flush_page_for_dma, BTFIXUPCALL_NORM);
2179
2180         if (poke_srmmu == poke_viking) {
2181                 /* Avoid unnecessary cross calls. */
2182                 BTFIXUPCOPY_CALL(flush_cache_all, local_flush_cache_all);
2183                 BTFIXUPCOPY_CALL(flush_cache_mm, local_flush_cache_mm);
2184                 BTFIXUPCOPY_CALL(flush_cache_range, local_flush_cache_range);
2185                 BTFIXUPCOPY_CALL(flush_cache_page, local_flush_cache_page);
2186                 BTFIXUPCOPY_CALL(__flush_page_to_ram, local_flush_page_to_ram);
2187                 BTFIXUPCOPY_CALL(flush_sig_insns, local_flush_sig_insns);
2188                 BTFIXUPCOPY_CALL(flush_page_for_dma, local_flush_page_for_dma);
2189         }
2190 #endif
2191
2192         if (sparc_cpu_model == sun4d)
2193                 ld_mmu_iounit();
2194         else
2195                 ld_mmu_iommu();
2196 #ifdef CONFIG_SMP
2197         if (sparc_cpu_model == sun4d)
2198                 sun4d_init_smp();
2199         else if (sparc_cpu_model == sparc_leon)
2200                 leon_init_smp();
2201         else
2202                 sun4m_init_smp();
2203 #endif
2204 }