arch/sparc/mm/init_64.c

   1 /*
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/initrd.h>
  17 #include <linux/swap.h>
  18 #include <linux/pagemap.h>
  19 #include <linux/poison.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/kprobes.h>
  23 #include <linux/cache.h>
  24 #include <linux/sort.h>
  25 #include <linux/percpu.h>
  26 #include <linux/memblock.h>
  27 #include <linux/mmzone.h>
  28 #include <linux/gfp.h>
  29
  30 #include <asm/head.h>
  31 #include <asm/page.h>
  32 #include <asm/pgalloc.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/oplib.h>
  35 #include <asm/iommu.h>
  36 #include <asm/io.h>
  37 #include <asm/uaccess.h>
  38 #include <asm/mmu_context.h>
  39 #include <asm/tlbflush.h>
  40 #include <asm/dma.h>
  41 #include <asm/starfire.h>
  42 #include <asm/tlb.h>
  43 #include <asm/spitfire.h>
  44 #include <asm/sections.h>
  45 #include <asm/tsb.h>
  46 #include <asm/hypervisor.h>
  47 #include <asm/prom.h>
  48 #include <asm/mdesc.h>
  49 #include <asm/cpudata.h>
  50 #include <asm/irq.h>
  51
  52 #include "init_64.h"
  53
  54 unsigned long kern_linear_pte_xor[4] __read_mostly;
  55
  56 /* A bitmap, two bits for every 256MB of physical memory.  These two
  57  * bits determine what page size we use for kernel linear
  58  * translations.  They form an index into kern_linear_pte_xor[].  The
  59  * value in the indexed slot is XOR'd with the TLB miss virtual
  60  * address to form the resulting TTE.  The mapping is:
  61  *
  62  *      0       ==>     4MB
  63  *      1       ==>     256MB
  64  *      2       ==>     2GB
  65  *      3       ==>     16GB
  66  *
  67  * All sun4v chips support 256MB pages.  Only SPARC-T4 and later
  68  * support 2GB pages, and hopefully future cpus will support the 16GB
  69  * pages as well.  For slots 2 and 3, we encode a 256MB TTE xor there
  70  * if these larger page sizes are not supported by the cpu.
  71  *
  72  * It would be nice to determine this from the machine description
  73  * 'cpu' properties, but we need to have this table setup before the
  74  * MDESC is initialized.
  75  */
  76 unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
  77
  78 #ifndef CONFIG_DEBUG_PAGEALLOC
  79 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
  80  * Space is allocated for this right after the trap table in
  81  * arch/sparc64/kernel/head.S
  82  */
  83 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
  84 #endif
  85
  86 static unsigned long cpu_pgsz_mask;
  87
  88 #define MAX_BANKS       32
  89
  90 static struct linux_prom64_registers pavail[MAX_BANKS];
  91 static int pavail_ents;
  92
  93 static int cmp_p64(const void *a, const void *b)
  94 {
  95         const struct linux_prom64_registers *x = a, *y = b;
  96
  97         if (x->phys_addr > y->phys_addr)
  98                 return 1;
  99         if (x->phys_addr < y->phys_addr)
 100                 return -1;
 101         return 0;
 102 }
 103
 104 static void __init read_obp_memory(const char *property,
 105                                    struct linux_prom64_registers *regs,
 106                                    int *num_ents)
 107 {
 108         phandle node = prom_finddevice("/memory");
 109         int prop_size = prom_getproplen(node, property);
 110         int ents, ret, i;
 111
 112         ents = prop_size / sizeof(struct linux_prom64_registers);
 113         if (ents > MAX_BANKS) {
 114                 prom_printf("The machine has more %s property entries than "
 115                             "this kernel can support (%d).\n",
 116                             property, MAX_BANKS);
 117                 prom_halt();
 118         }
 119
 120         ret = prom_getproperty(node, property, (char *) regs, prop_size);
 121         if (ret == -1) {
 122                 prom_printf("Couldn't get %s property from /memory.\n",
 123                                 property);
 124                 prom_halt();
 125         }
 126
 127         /* Sanitize what we got from the firmware, by page aligning
 128          * everything.
 129          */
 130         for (i = 0; i < ents; i++) {
 131                 unsigned long base, size;
 132
 133                 base = regs[i].phys_addr;
 134                 size = regs[i].reg_size;
 135
 136                 size &= PAGE_MASK;
 137                 if (base & ~PAGE_MASK) {
 138                         unsigned long new_base = PAGE_ALIGN(base);
 139
 140                         size -= new_base - base;
 141                         if ((long) size < 0L)
 142                                 size = 0UL;
 143                         base = new_base;
 144                 }
 145                 if (size == 0UL) {
 146                         /* If it is empty, simply get rid of it.
 147                          * This simplifies the logic of the other
 148                          * functions that process these arrays.
 149                          */
 150                         memmove(&regs[i], &regs[i + 1],
 151                                 (ents - i - 1) * sizeof(regs[0]));
 152                         i--;
 153                         ents--;
 154                         continue;
 155                 }
 156                 regs[i].phys_addr = base;
 157                 regs[i].reg_size = size;
 158         }
 159
 160         *num_ents = ents;
 161
 162         sort(regs, ents, sizeof(struct linux_prom64_registers),
 163              cmp_p64, NULL);
 164 }
 165
 166 unsigned long sparc64_valid_addr_bitmap[VALID_ADDR_BITMAP_BYTES /
 167                                         sizeof(unsigned long)];
 168 EXPORT_SYMBOL(sparc64_valid_addr_bitmap);
 169
 170 /* Kernel physical address base and size in bytes.  */
 171 unsigned long kern_base __read_mostly;
 172 unsigned long kern_size __read_mostly;
 173
 174 /* Initial ramdisk setup */
 175 extern unsigned long sparc_ramdisk_image64;
 176 extern unsigned int sparc_ramdisk_image;
 177 extern unsigned int sparc_ramdisk_size;
 178
 179 struct page *mem_map_zero __read_mostly;
 180 EXPORT_SYMBOL(mem_map_zero);
 181
 182 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 183
 184 unsigned long sparc64_kern_pri_context __read_mostly;
 185 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 186 unsigned long sparc64_kern_sec_context __read_mostly;
 187
 188 int num_kernel_image_mappings;
 189
 190 #ifdef CONFIG_DEBUG_DCFLUSH
 191 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 192 #ifdef CONFIG_SMP
 193 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 194 #endif
 195 #endif
 196
 197 inline void flush_dcache_page_impl(struct page *page)
 198 {
 199         BUG_ON(tlb_type == hypervisor);
 200 #ifdef CONFIG_DEBUG_DCFLUSH
 201         atomic_inc(&dcpage_flushes);
 202 #endif
 203
 204 #ifdef DCACHE_ALIASING_POSSIBLE
 205         __flush_dcache_page(page_address(page),
 206                             ((tlb_type == spitfire) &&
 207                              page_mapping(page) != NULL));
 208 #else
 209         if (page_mapping(page) != NULL &&
 210             tlb_type == spitfire)
 211                 __flush_icache_page(__pa(page_address(page)));
 212 #endif
 213 }
 214
 215 #define PG_dcache_dirty         PG_arch_1
 216 #define PG_dcache_cpu_shift     32UL
 217 #define PG_dcache_cpu_mask      \
 218         ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
 219
 220 #define dcache_dirty_cpu(page) \
 221         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 222
 223 static inline void set_dcache_dirty(struct page *page, int this_cpu)
 224 {
 225         unsigned long mask = this_cpu;
 226         unsigned long non_cpu_bits;
 227
 228         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 229         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 230
 231         __asm__ __volatile__("1:\n\t"
 232                              "ldx       [%2], %%g7\n\t"
 233                              "and       %%g7, %1, %%g1\n\t"
 234                              "or        %%g1, %0, %%g1\n\t"
 235                              "casx      [%2], %%g7, %%g1\n\t"
 236                              "cmp       %%g7, %%g1\n\t"
 237                              "bne,pn    %%xcc, 1b\n\t"
 238                              " nop"
 239                              : /* no outputs */
 240                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 241                              : "g1", "g7");
 242 }
 243
 244 static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 245 {
 246         unsigned long mask = (1UL << PG_dcache_dirty);
 247
 248         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 249                              "1:\n\t"
 250                              "ldx       [%2], %%g7\n\t"
 251                              "srlx      %%g7, %4, %%g1\n\t"
 252                              "and       %%g1, %3, %%g1\n\t"
 253                              "cmp       %%g1, %0\n\t"
 254                              "bne,pn    %%icc, 2f\n\t"
 255                              " andn     %%g7, %1, %%g1\n\t"
 256                              "casx      [%2], %%g7, %%g1\n\t"
 257                              "cmp       %%g7, %%g1\n\t"
 258                              "bne,pn    %%xcc, 1b\n\t"
 259                              " nop\n"
 260                              "2:"
 261                              : /* no outputs */
 262                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 263                                "i" (PG_dcache_cpu_mask),
 264                                "i" (PG_dcache_cpu_shift)
 265                              : "g1", "g7");
 266 }
 267
 268 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
 269 {
 270         unsigned long tsb_addr = (unsigned long) ent;
 271
 272         if (tlb_type == cheetah_plus || tlb_type == hypervisor)
 273                 tsb_addr = __pa(tsb_addr);
 274
 275         __tsb_insert(tsb_addr, tag, pte);
 276 }
 277
 278 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
 279
 280 static void flush_dcache(unsigned long pfn)
 281 {
 282         struct page *page;
 283
 284         page = pfn_to_page(pfn);
 285         if (page) {
 286                 unsigned long pg_flags;
 287
 288                 pg_flags = page->flags;
 289                 if (pg_flags & (1UL << PG_dcache_dirty)) {
 290                         int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 291                                    PG_dcache_cpu_mask);
 292                         int this_cpu = get_cpu();
 293
 294                         /* This is just to optimize away some function calls
 295                          * in the SMP case.
 296                          */
 297                         if (cpu == this_cpu)
 298                                 flush_dcache_page_impl(page);
 299                         else
 300                                 smp_flush_dcache_page_impl(page, cpu);
 301
 302                         clear_dcache_dirty_cpu(page, cpu);
 303
 304                         put_cpu();
 305                 }
 306         }
 307 }
 308
 309 /* mm->context.lock must be held */
 310 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
 311                                     unsigned long tsb_hash_shift, unsigned long address,
 312                                     unsigned long tte)
 313 {
 314         struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
 315         unsigned long tag;
 316
 317         if (unlikely(!tsb))
 318                 return;
 319
 320         tsb += ((address >> tsb_hash_shift) &
 321                 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
 322         tag = (address >> 22UL);
 323         tsb_insert(tsb, tag, tte);
 324 }
 325
 326 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
 327 static inline bool is_hugetlb_pte(pte_t pte)
 328 {
 329         if ((tlb_type == hypervisor &&
 330              (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
 331             (tlb_type != hypervisor &&
 332              (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U))
 333                 return true;
 334         return false;
 335 }
 336 #endif
 337
 338 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
 339 {
 340         struct mm_struct *mm;
 341         unsigned long flags;
 342         pte_t pte = *ptep;
 343
 344         if (tlb_type != hypervisor) {
 345                 unsigned long pfn = pte_pfn(pte);
 346
 347                 if (pfn_valid(pfn))
 348                         flush_dcache(pfn);
 349         }
 350
 351         mm = vma->vm_mm;
 352
 353         spin_lock_irqsave(&mm->context.lock, flags);
 354
 355 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
 356         if (mm->context.huge_pte_count && is_hugetlb_pte(pte))
 357                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, HPAGE_SHIFT,
 358                                         address, pte_val(pte));
 359         else
 360 #endif
 361                 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
 362                                         address, pte_val(pte));
 363
 364         spin_unlock_irqrestore(&mm->context.lock, flags);
 365 }
 366
 367 void flush_dcache_page(struct page *page)
 368 {
 369         struct address_space *mapping;
 370         int this_cpu;
 371
 372         if (tlb_type == hypervisor)
 373                 return;
 374
 375         /* Do not bother with the expensive D-cache flush if it
 376          * is merely the zero page.  The 'bigcore' testcase in GDB
 377          * causes this case to run millions of times.
 378          */
 379         if (page == ZERO_PAGE(0))
 380                 return;
 381
 382         this_cpu = get_cpu();
 383
 384         mapping = page_mapping(page);
 385         if (mapping && !mapping_mapped(mapping)) {
 386                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 387                 if (dirty) {
 388                         int dirty_cpu = dcache_dirty_cpu(page);
 389
 390                         if (dirty_cpu == this_cpu)
 391                                 goto out;
 392                         smp_flush_dcache_page_impl(page, dirty_cpu);
 393                 }
 394                 set_dcache_dirty(page, this_cpu);
 395         } else {
 396                 /* We could delay the flush for the !page_mapping
 397                  * case too.  But that case is for exec env/arg
 398                  * pages and those are %99 certainly going to get
 399                  * faulted into the tlb (and thus flushed) anyways.
 400                  */
 401                 flush_dcache_page_impl(page);
 402         }
 403
 404 out:
 405         put_cpu();
 406 }
 407 EXPORT_SYMBOL(flush_dcache_page);
 408
 409 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 410 {
 411         /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
 412         if (tlb_type == spitfire) {
 413                 unsigned long kaddr;
 414
 415                 /* This code only runs on Spitfire cpus so this is
 416                  * why we can assume _PAGE_PADDR_4U.
 417                  */
 418                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
 419                         unsigned long paddr, mask = _PAGE_PADDR_4U;
 420
 421                         if (kaddr >= PAGE_OFFSET)
 422                                 paddr = kaddr & mask;
 423                         else {
 424                                 pgd_t *pgdp = pgd_offset_k(kaddr);
 425                                 pud_t *pudp = pud_offset(pgdp, kaddr);
 426                                 pmd_t *pmdp = pmd_offset(pudp, kaddr);
 427                                 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
 428
 429                                 paddr = pte_val(*ptep) & mask;
 430                         }
 431                         __flush_icache_page(paddr);
 432                 }
 433         }
 434 }
 435 EXPORT_SYMBOL(flush_icache_range);
 436
 437 void mmu_info(struct seq_file *m)
 438 {
 439         static const char *pgsz_strings[] = {
 440                 "8K", "64K", "512K", "4MB", "32MB",
 441                 "256MB", "2GB", "16GB",
 442         };
 443         int i, printed;
 444
 445         if (tlb_type == cheetah)
 446                 seq_printf(m, "MMU Type\t: Cheetah\n");
 447         else if (tlb_type == cheetah_plus)
 448                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 449         else if (tlb_type == spitfire)
 450                 seq_printf(m, "MMU Type\t: Spitfire\n");
 451         else if (tlb_type == hypervisor)
 452                 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
 453         else
 454                 seq_printf(m, "MMU Type\t: ???\n");
 455
 456         seq_printf(m, "MMU PGSZs\t: ");
 457         printed = 0;
 458         for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
 459                 if (cpu_pgsz_mask & (1UL << i)) {
 460                         seq_printf(m, "%s%s",
 461                                    printed ? "," : "", pgsz_strings[i]);
 462                         printed++;
 463                 }
 464         }
 465         seq_putc(m, '\n');
 466
 467 #ifdef CONFIG_DEBUG_DCFLUSH
 468         seq_printf(m, "DCPageFlushes\t: %d\n",
 469                    atomic_read(&dcpage_flushes));
 470 #ifdef CONFIG_SMP
 471         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 472                    atomic_read(&dcpage_flushes_xcall));
 473 #endif /* CONFIG_SMP */
 474 #endif /* CONFIG_DEBUG_DCFLUSH */
 475 }
 476
 477 struct linux_prom_translation prom_trans[512] __read_mostly;
 478 unsigned int prom_trans_ents __read_mostly;
 479
 480 unsigned long kern_locked_tte_data;
 481
 482 /* The obp translations are saved based on 8k pagesize, since obp can
 483  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 484  * HI_OBP_ADDRESS range are handled in ktlb.S.
 485  */
 486 static inline int in_obp_range(unsigned long vaddr)
 487 {
 488         return (vaddr >= LOW_OBP_ADDRESS &&
 489                 vaddr < HI_OBP_ADDRESS);
 490 }
 491
 492 static int cmp_ptrans(const void *a, const void *b)
 493 {
 494         const struct linux_prom_translation *x = a, *y = b;
 495
 496         if (x->virt > y->virt)
 497                 return 1;
 498         if (x->virt < y->virt)
 499                 return -1;
 500         return 0;
 501 }
 502
 503 /* Read OBP translations property into 'prom_trans[]'.  */
 504 static void __init read_obp_translations(void)
 505 {
 506         int n, node, ents, first, last, i;
 507
 508         node = prom_finddevice("/virtual-memory");
 509         n = prom_getproplen(node, "translations");
 510         if (unlikely(n == 0 || n == -1)) {
 511                 prom_printf("prom_mappings: Couldn't get size.\n");
 512                 prom_halt();
 513         }
 514         if (unlikely(n > sizeof(prom_trans))) {
 515                 prom_printf("prom_mappings: Size %d is too big.\n", n);
 516                 prom_halt();
 517         }
 518
 519         if ((n = prom_getproperty(node, "translations",
 520                                   (char *)&prom_trans[0],
 521                                   sizeof(prom_trans))) == -1) {
 522                 prom_printf("prom_mappings: Couldn't get property.\n");
 523                 prom_halt();
 524         }
 525
 526         n = n / sizeof(struct linux_prom_translation);
 527
 528         ents = n;
 529
 530         sort(prom_trans, ents, sizeof(struct linux_prom_translation),
 531              cmp_ptrans, NULL);
 532
 533         /* Now kick out all the non-OBP entries.  */
 534         for (i = 0; i < ents; i++) {
 535                 if (in_obp_range(prom_trans[i].virt))
 536                         break;
 537         }
 538         first = i;
 539         for (; i < ents; i++) {
 540                 if (!in_obp_range(prom_trans[i].virt))
 541                         break;
 542         }
 543         last = i;
 544
 545         for (i = 0; i < (last - first); i++) {
 546                 struct linux_prom_translation *src = &prom_trans[i + first];
 547                 struct linux_prom_translation *dest = &prom_trans[i];
 548
 549                 *dest = *src;
 550         }
 551         for (; i < ents; i++) {
 552                 struct linux_prom_translation *dest = &prom_trans[i];
 553                 dest->virt = dest->size = dest->data = 0x0UL;
 554         }
 555
 556         prom_trans_ents = last - first;
 557
 558         if (tlb_type == spitfire) {
 559                 /* Clear diag TTE bits. */
 560                 for (i = 0; i < prom_trans_ents; i++)
 561                         prom_trans[i].data &= ~0x0003fe0000000000UL;
 562         }
 563
 564         /* Force execute bit on.  */
 565         for (i = 0; i < prom_trans_ents; i++)
 566                 prom_trans[i].data |= (tlb_type == hypervisor ?
 567                                        _PAGE_EXEC_4V : _PAGE_EXEC_4U);
 568 }
 569
 570 static void __init hypervisor_tlb_lock(unsigned long vaddr,
 571                                        unsigned long pte,
 572                                        unsigned long mmu)
 573 {
 574         unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
 575
 576         if (ret != 0) {
 577                 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
 578                             "errors with %lx\n", vaddr, 0, pte, mmu, ret);
 579                 prom_halt();
 580         }
 581 }
 582
 583 static unsigned long kern_large_tte(unsigned long paddr);
 584
 585 static void __init remap_kernel(void)
 586 {
 587         unsigned long phys_page, tte_vaddr, tte_data;
 588         int i, tlb_ent = sparc64_highest_locked_tlbent();
 589
 590         tte_vaddr = (unsigned long) KERNBASE;
 591         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
 592         tte_data = kern_large_tte(phys_page);
 593
 594         kern_locked_tte_data = tte_data;
 595
 596         /* Now lock us into the TLBs via Hypervisor or OBP. */
 597         if (tlb_type == hypervisor) {
 598                 for (i = 0; i < num_kernel_image_mappings; i++) {
 599                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
 600                         hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
 601                         tte_vaddr += 0x400000;
 602                         tte_data += 0x400000;
 603                 }
 604         } else {
 605                 for (i = 0; i < num_kernel_image_mappings; i++) {
 606                         prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
 607                         prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
 608                         tte_vaddr += 0x400000;
 609                         tte_data += 0x400000;
 610                 }
 611                 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
 612         }
 613         if (tlb_type == cheetah_plus) {
 614                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 615                                             CTX_CHEETAH_PLUS_NUC);
 616                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 617                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 618         }
 619 }
 620
 621
 622 static void __init inherit_prom_mappings(void)
 623 {
 624         /* Now fixup OBP's idea about where we really are mapped. */
 625         printk("Remapping the kernel... ");
 626         remap_kernel();
 627         printk("done.\n");
 628 }
 629
 630 void prom_world(int enter)
 631 {
 632         if (!enter)
 633                 set_fs(get_fs());
 634
 635         __asm__ __volatile__("flushw");
 636 }
 637
 638 void __flush_dcache_range(unsigned long start, unsigned long end)
 639 {
 640         unsigned long va;
 641
 642         if (tlb_type == spitfire) {
 643                 int n = 0;
 644
 645                 for (va = start; va < end; va += 32) {
 646                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 647                         if (++n >= 512)
 648                                 break;
 649                 }
 650         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 651                 start = __pa(start);
 652                 end = __pa(end);
 653                 for (va = start; va < end; va += 32)
 654                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 655                                              "membar #Sync"
 656                                              : /* no outputs */
 657                                              : "r" (va),
 658                                                "i" (ASI_DCACHE_INVALIDATE));
 659         }
 660 }
 661 EXPORT_SYMBOL(__flush_dcache_range);
 662
 663 /* get_new_mmu_context() uses "cache + 1".  */
 664 DEFINE_SPINLOCK(ctx_alloc_lock);
 665 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
 666 #define MAX_CTX_NR      (1UL << CTX_NR_BITS)
 667 #define CTX_BMAP_SLOTS  BITS_TO_LONGS(MAX_CTX_NR)
 668 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
 669
 670 /* Caller does TLB context flushing on local CPU if necessary.
 671  * The caller also ensures that CTX_VALID(mm->context) is false.
 672  *
 673  * We must be careful about boundary cases so that we never
 674  * let the user have CTX 0 (nucleus) or we ever use a CTX
 675  * version of zero (and thus NO_CONTEXT would not be caught
 676  * by version mis-match tests in mmu_context.h).
 677  *
 678  * Always invoked with interrupts disabled.
 679  */
 680 void get_new_mmu_context(struct mm_struct *mm)
 681 {
 682         unsigned long ctx, new_ctx;
 683         unsigned long orig_pgsz_bits;
 684         int new_version;
 685
 686         spin_lock(&ctx_alloc_lock);
 687         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
 688         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
 689         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
 690         new_version = 0;
 691         if (new_ctx >= (1 << CTX_NR_BITS)) {
 692                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
 693                 if (new_ctx >= ctx) {
 694                         int i;
 695                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
 696                                 CTX_FIRST_VERSION;
 697                         if (new_ctx == 1)
 698                                 new_ctx = CTX_FIRST_VERSION;
 699
 700                         /* Don't call memset, for 16 entries that's just
 701                          * plain silly...
 702                          */
 703                         mmu_context_bmap[0] = 3;
 704                         mmu_context_bmap[1] = 0;
 705                         mmu_context_bmap[2] = 0;
 706                         mmu_context_bmap[3] = 0;
 707                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
 708                                 mmu_context_bmap[i + 0] = 0;
 709                                 mmu_context_bmap[i + 1] = 0;
 710                                 mmu_context_bmap[i + 2] = 0;
 711                                 mmu_context_bmap[i + 3] = 0;
 712                         }
 713                         new_version = 1;
 714                         goto out;
 715                 }
 716         }
 717         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
 718         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
 719 out:
 720         tlb_context_cache = new_ctx;
 721         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
 722         spin_unlock(&ctx_alloc_lock);
 723
 724         if (unlikely(new_version))
 725                 smp_new_mmu_context_version();
 726 }
 727
 728 static int numa_enabled = 1;
 729 static int numa_debug;
 730
 731 static int __init early_numa(char *p)
 732 {
 733         if (!p)
 734                 return 0;
 735
 736         if (strstr(p, "off"))
 737                 numa_enabled = 0;
 738
 739         if (strstr(p, "debug"))
 740                 numa_debug = 1;
 741
 742         return 0;
 743 }
 744 early_param("numa", early_numa);
 745
 746 #define numadbg(f, a...) \
 747 do {    if (numa_debug) \
 748                 printk(KERN_INFO f, ## a); \
 749 } while (0)
 750
 751 static void __init find_ramdisk(unsigned long phys_base)
 752 {
 753 #ifdef CONFIG_BLK_DEV_INITRD
 754         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
 755                 unsigned long ramdisk_image;
 756
 757                 /* Older versions of the bootloader only supported a
 758                  * 32-bit physical address for the ramdisk image
 759                  * location, stored at sparc_ramdisk_image.  Newer
 760                  * SILO versions set sparc_ramdisk_image to zero and
 761                  * provide a full 64-bit physical address at
 762                  * sparc_ramdisk_image64.
 763                  */
 764                 ramdisk_image = sparc_ramdisk_image;
 765                 if (!ramdisk_image)
 766                         ramdisk_image = sparc_ramdisk_image64;
 767
 768                 /* Another bootloader quirk.  The bootloader normalizes
 769                  * the physical address to KERNBASE, so we have to
 770                  * factor that back out and add in the lowest valid
 771                  * physical page address to get the true physical address.
 772                  */
 773                 ramdisk_image -= KERNBASE;
 774                 ramdisk_image += phys_base;
 775
 776                 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
 777                         ramdisk_image, sparc_ramdisk_size);
 778
 779                 initrd_start = ramdisk_image;
 780                 initrd_end = ramdisk_image + sparc_ramdisk_size;
 781
 782                 memblock_reserve(initrd_start, sparc_ramdisk_size);
 783
 784                 initrd_start += PAGE_OFFSET;
 785                 initrd_end += PAGE_OFFSET;
 786         }
 787 #endif
 788 }
 789
 790 struct node_mem_mask {
 791         unsigned long mask;
 792         unsigned long val;
 793 };
 794 static struct node_mem_mask node_masks[MAX_NUMNODES];
 795 static int num_node_masks;
 796
 797 int numa_cpu_lookup_table[NR_CPUS];
 798 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
 799
 800 #ifdef CONFIG_NEED_MULTIPLE_NODES
 801
 802 struct mdesc_mblock {
 803         u64     base;
 804         u64     size;
 805         u64     offset; /* RA-to-PA */
 806 };
 807 static struct mdesc_mblock *mblocks;
 808 static int num_mblocks;
 809
 810 static unsigned long ra_to_pa(unsigned long addr)
 811 {
 812         int i;
 813
 814         for (i = 0; i < num_mblocks; i++) {
 815                 struct mdesc_mblock *m = &mblocks[i];
 816
 817                 if (addr >= m->base &&
 818                     addr < (m->base + m->size)) {
 819                         addr += m->offset;
 820                         break;
 821                 }
 822         }
 823         return addr;
 824 }
 825
 826 static int find_node(unsigned long addr)
 827 {
 828         int i;
 829
 830         addr = ra_to_pa(addr);
 831         for (i = 0; i < num_node_masks; i++) {
 832                 struct node_mem_mask *p = &node_masks[i];
 833
 834                 if ((addr & p->mask) == p->val)
 835                         return i;
 836         }
 837         return -1;
 838 }
 839
 840 static u64 memblock_nid_range(u64 start, u64 end, int *nid)
 841 {
 842         *nid = find_node(start);
 843         start += PAGE_SIZE;
 844         while (start < end) {
 845                 int n = find_node(start);
 846
 847                 if (n != *nid)
 848                         break;
 849                 start += PAGE_SIZE;
 850         }
 851
 852         if (start > end)
 853                 start = end;
 854
 855         return start;
 856 }
 857 #endif
 858
 859 /* This must be invoked after performing all of the necessary
 860  * memblock_set_node() calls for 'nid'.  We need to be able to get
 861  * correct data from get_pfn_range_for_nid().
 862  */
 863 static void __init allocate_node_data(int nid)
 864 {
 865         struct pglist_data *p;
 866         unsigned long start_pfn, end_pfn;
 867 #ifdef CONFIG_NEED_MULTIPLE_NODES
 868         unsigned long paddr;
 869
 870         paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
 871         if (!paddr) {
 872                 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
 873                 prom_halt();
 874         }
 875         NODE_DATA(nid) = __va(paddr);
 876         memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
 877
 878         NODE_DATA(nid)->node_id = nid;
 879 #endif
 880
 881         p = NODE_DATA(nid);
 882
 883         get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
 884         p->node_start_pfn = start_pfn;
 885         p->node_spanned_pages = end_pfn - start_pfn;
 886 }
 887
 888 static void init_node_masks_nonnuma(void)
 889 {
 890         int i;
 891
 892         numadbg("Initializing tables for non-numa.\n");
 893
 894         node_masks[0].mask = node_masks[0].val = 0;
 895         num_node_masks = 1;
 896
 897         for (i = 0; i < NR_CPUS; i++)
 898                 numa_cpu_lookup_table[i] = 0;
 899
 900         cpumask_setall(&numa_cpumask_lookup_table[0]);
 901 }
 902
 903 #ifdef CONFIG_NEED_MULTIPLE_NODES
 904 struct pglist_data *node_data[MAX_NUMNODES];
 905
 906 EXPORT_SYMBOL(numa_cpu_lookup_table);
 907 EXPORT_SYMBOL(numa_cpumask_lookup_table);
 908 EXPORT_SYMBOL(node_data);
 909
 910 struct mdesc_mlgroup {
 911         u64     node;
 912         u64     latency;
 913         u64     match;
 914         u64     mask;
 915 };
 916 static struct mdesc_mlgroup *mlgroups;
 917 static int num_mlgroups;
 918
 919 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
 920                                    u32 cfg_handle)
 921 {
 922         u64 arc;
 923
 924         mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
 925                 u64 target = mdesc_arc_target(md, arc);
 926                 const u64 *val;
 927
 928                 val = mdesc_get_property(md, target,
 929                                          "cfg-handle", NULL);
 930                 if (val && *val == cfg_handle)
 931                         return 0;
 932         }
 933         return -ENODEV;
 934 }
 935
 936 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
 937                                     u32 cfg_handle)
 938 {
 939         u64 arc, candidate, best_latency = ~(u64)0;
 940
 941         candidate = MDESC_NODE_NULL;
 942         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
 943                 u64 target = mdesc_arc_target(md, arc);
 944                 const char *name = mdesc_node_name(md, target);
 945                 const u64 *val;
 946
 947                 if (strcmp(name, "pio-latency-group"))
 948                         continue;
 949
 950                 val = mdesc_get_property(md, target, "latency", NULL);
 951                 if (!val)
 952                         continue;
 953
 954                 if (*val < best_latency) {
 955                         candidate = target;
 956                         best_latency = *val;
 957                 }
 958         }
 959
 960         if (candidate == MDESC_NODE_NULL)
 961                 return -ENODEV;
 962
 963         return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
 964 }
 965
 966 int of_node_to_nid(struct device_node *dp)
 967 {
 968         const struct linux_prom64_registers *regs;
 969         struct mdesc_handle *md;
 970         u32 cfg_handle;
 971         int count, nid;
 972         u64 grp;
 973
 974         /* This is the right thing to do on currently supported
 975          * SUN4U NUMA platforms as well, as the PCI controller does
 976          * not sit behind any particular memory controller.
 977          */
 978         if (!mlgroups)
 979                 return -1;
 980
 981         regs = of_get_property(dp, "reg", NULL);
 982         if (!regs)
 983                 return -1;
 984
 985         cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
 986
 987         md = mdesc_grab();
 988
 989         count = 0;
 990         nid = -1;
 991         mdesc_for_each_node_by_name(md, grp, "group") {
 992                 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
 993                         nid = count;
 994                         break;
 995                 }
 996                 count++;
 997         }
 998
 999         mdesc_release(md);
1000
1001         return nid;
1002 }
1003
1004 static void __init add_node_ranges(void)
1005 {
1006         struct memblock_region *reg;
1007
1008         for_each_memblock(memory, reg) {
1009                 unsigned long size = reg->size;
1010                 unsigned long start, end;
1011
1012                 start = reg->base;
1013                 end = start + size;
1014                 while (start < end) {
1015                         unsigned long this_end;
1016                         int nid;
1017
1018                         this_end = memblock_nid_range(start, end, &nid);
1019
1020                         numadbg("Setting memblock NUMA node nid[%d] "
1021                                 "start[%lx] end[%lx]\n",
1022                                 nid, start, this_end);
1023
1024                         memblock_set_node(start, this_end - start, nid);
1025                         start = this_end;
1026                 }
1027         }
1028 }
1029
1030 static int __init grab_mlgroups(struct mdesc_handle *md)
1031 {
1032         unsigned long paddr;
1033         int count = 0;
1034         u64 node;
1035
1036         mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1037                 count++;
1038         if (!count)
1039                 return -ENOENT;
1040
1041         paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1042                           SMP_CACHE_BYTES);
1043         if (!paddr)
1044                 return -ENOMEM;
1045
1046         mlgroups = __va(paddr);
1047         num_mlgroups = count;
1048
1049         count = 0;
1050         mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1051                 struct mdesc_mlgroup *m = &mlgroups[count++];
1052                 const u64 *val;
1053
1054                 m->node = node;
1055
1056                 val = mdesc_get_property(md, node, "latency", NULL);
1057                 m->latency = *val;
1058                 val = mdesc_get_property(md, node, "address-match", NULL);
1059                 m->match = *val;
1060                 val = mdesc_get_property(md, node, "address-mask", NULL);
1061                 m->mask = *val;
1062
1063                 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1064                         "match[%llx] mask[%llx]\n",
1065                         count - 1, m->node, m->latency, m->match, m->mask);
1066         }
1067
1068         return 0;
1069 }
1070
1071 static int __init grab_mblocks(struct mdesc_handle *md)
1072 {
1073         unsigned long paddr;
1074         int count = 0;
1075         u64 node;
1076
1077         mdesc_for_each_node_by_name(md, node, "mblock")
1078                 count++;
1079         if (!count)
1080                 return -ENOENT;
1081
1082         paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1083                           SMP_CACHE_BYTES);
1084         if (!paddr)
1085                 return -ENOMEM;
1086
1087         mblocks = __va(paddr);
1088         num_mblocks = count;
1089
1090         count = 0;
1091         mdesc_for_each_node_by_name(md, node, "mblock") {
1092                 struct mdesc_mblock *m = &mblocks[count++];
1093                 const u64 *val;
1094
1095                 val = mdesc_get_property(md, node, "base", NULL);
1096                 m->base = *val;
1097                 val = mdesc_get_property(md, node, "size", NULL);
1098                 m->size = *val;
1099                 val = mdesc_get_property(md, node,
1100                                          "address-congruence-offset", NULL);
1101                 m->offset = *val;
1102
1103                 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1104                         count - 1, m->base, m->size, m->offset);
1105         }
1106
1107         return 0;
1108 }
1109
1110 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1111                                                u64 grp, cpumask_t *mask)
1112 {
1113         u64 arc;
1114
1115         cpumask_clear(mask);
1116
1117         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1118                 u64 target = mdesc_arc_target(md, arc);
1119                 const char *name = mdesc_node_name(md, target);
1120                 const u64 *id;
1121
1122                 if (strcmp(name, "cpu"))
1123                         continue;
1124                 id = mdesc_get_property(md, target, "id", NULL);
1125                 if (*id < nr_cpu_ids)
1126                         cpumask_set_cpu(*id, mask);
1127         }
1128 }
1129
1130 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1131 {
1132         int i;
1133
1134         for (i = 0; i < num_mlgroups; i++) {
1135                 struct mdesc_mlgroup *m = &mlgroups[i];
1136                 if (m->node == node)
1137                         return m;
1138         }
1139         return NULL;
1140 }
1141
1142 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1143                                       int index)
1144 {
1145         struct mdesc_mlgroup *candidate = NULL;
1146         u64 arc, best_latency = ~(u64)0;
1147         struct node_mem_mask *n;
1148
1149         mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1150                 u64 target = mdesc_arc_target(md, arc);
1151                 struct mdesc_mlgroup *m = find_mlgroup(target);
1152                 if (!m)
1153                         continue;
1154                 if (m->latency < best_latency) {
1155                         candidate = m;
1156                         best_latency = m->latency;
1157                 }
1158         }
1159         if (!candidate)
1160                 return -ENOENT;
1161
1162         if (num_node_masks != index) {
1163                 printk(KERN_ERR "Inconsistent NUMA state, "
1164                        "index[%d] != num_node_masks[%d]\n",
1165                        index, num_node_masks);
1166                 return -EINVAL;
1167         }
1168
1169         n = &node_masks[num_node_masks++];
1170
1171         n->mask = candidate->mask;
1172         n->val = candidate->match;
1173
1174         numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1175                 index, n->mask, n->val, candidate->latency);
1176
1177         return 0;
1178 }
1179
1180 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1181                                          int index)
1182 {
1183         cpumask_t mask;
1184         int cpu;
1185
1186         numa_parse_mdesc_group_cpus(md, grp, &mask);
1187
1188         for_each_cpu(cpu, &mask)
1189                 numa_cpu_lookup_table[cpu] = index;
1190         cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1191
1192         if (numa_debug) {
1193                 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1194                 for_each_cpu(cpu, &mask)
1195                         printk("%d ", cpu);
1196                 printk("]\n");
1197         }
1198
1199         return numa_attach_mlgroup(md, grp, index);
1200 }
1201
1202 static int __init numa_parse_mdesc(void)
1203 {
1204         struct mdesc_handle *md = mdesc_grab();
1205         int i, err, count;
1206         u64 node;
1207
1208         node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1209         if (node == MDESC_NODE_NULL) {
1210                 mdesc_release(md);
1211                 return -ENOENT;
1212         }
1213
1214         err = grab_mblocks(md);
1215         if (err < 0)
1216                 goto out;
1217
1218         err = grab_mlgroups(md);
1219         if (err < 0)
1220                 goto out;
1221
1222         count = 0;
1223         mdesc_for_each_node_by_name(md, node, "group") {
1224                 err = numa_parse_mdesc_group(md, node, count);
1225                 if (err < 0)
1226                         break;
1227                 count++;
1228         }
1229
1230         add_node_ranges();
1231
1232         for (i = 0; i < num_node_masks; i++) {
1233                 allocate_node_data(i);
1234                 node_set_online(i);
1235         }
1236
1237         err = 0;
1238 out:
1239         mdesc_release(md);
1240         return err;
1241 }
1242
1243 static int __init numa_parse_jbus(void)
1244 {
1245         unsigned long cpu, index;
1246
1247         /* NUMA node id is encoded in bits 36 and higher, and there is
1248          * a 1-to-1 mapping from CPU ID to NUMA node ID.
1249          */
1250         index = 0;
1251         for_each_present_cpu(cpu) {
1252                 numa_cpu_lookup_table[cpu] = index;
1253                 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1254                 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1255                 node_masks[index].val = cpu << 36UL;
1256
1257                 index++;
1258         }
1259         num_node_masks = index;
1260
1261         add_node_ranges();
1262
1263         for (index = 0; index < num_node_masks; index++) {
1264                 allocate_node_data(index);
1265                 node_set_online(index);
1266         }
1267
1268         return 0;
1269 }
1270
1271 static int __init numa_parse_sun4u(void)
1272 {
1273         if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1274                 unsigned long ver;
1275
1276                 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1277                 if ((ver >> 32UL) == __JALAPENO_ID ||
1278                     (ver >> 32UL) == __SERRANO_ID)
1279                         return numa_parse_jbus();
1280         }
1281         return -1;
1282 }
1283
1284 static int __init bootmem_init_numa(void)
1285 {
1286         int err = -1;
1287
1288         numadbg("bootmem_init_numa()\n");
1289
1290         if (numa_enabled) {
1291                 if (tlb_type == hypervisor)
1292                         err = numa_parse_mdesc();
1293                 else
1294                         err = numa_parse_sun4u();
1295         }
1296         return err;
1297 }
1298
1299 #else
1300
1301 static int bootmem_init_numa(void)
1302 {
1303         return -1;
1304 }
1305
1306 #endif
1307
1308 static void __init bootmem_init_nonnuma(void)
1309 {
1310         unsigned long top_of_ram = memblock_end_of_DRAM();
1311         unsigned long total_ram = memblock_phys_mem_size();
1312
1313         numadbg("bootmem_init_nonnuma()\n");
1314
1315         printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1316                top_of_ram, total_ram);
1317         printk(KERN_INFO "Memory hole size: %ldMB\n",
1318                (top_of_ram - total_ram) >> 20);
1319
1320         init_node_masks_nonnuma();
1321         memblock_set_node(0, (phys_addr_t)ULLONG_MAX, 0);
1322         allocate_node_data(0);
1323         node_set_online(0);
1324 }
1325
1326 static unsigned long __init bootmem_init(unsigned long phys_base)
1327 {
1328         unsigned long end_pfn;
1329
1330         end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1331         max_pfn = max_low_pfn = end_pfn;
1332         min_low_pfn = (phys_base >> PAGE_SHIFT);
1333
1334         if (bootmem_init_numa() < 0)
1335                 bootmem_init_nonnuma();
1336
1337         /* Dump memblock with node info. */
1338         memblock_dump_all();
1339
1340         /* XXX cpu notifier XXX */
1341
1342         sparse_memory_present_with_active_regions(MAX_NUMNODES);
1343         sparse_init();
1344
1345         return end_pfn;
1346 }
1347
1348 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1349 static int pall_ents __initdata;
1350
1351 #ifdef CONFIG_DEBUG_PAGEALLOC
1352 static unsigned long __ref kernel_map_range(unsigned long pstart,
1353                                             unsigned long pend, pgprot_t prot)
1354 {
1355         unsigned long vstart = PAGE_OFFSET + pstart;
1356         unsigned long vend = PAGE_OFFSET + pend;
1357         unsigned long alloc_bytes = 0UL;
1358
1359         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1360                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1361                             vstart, vend);
1362                 prom_halt();
1363         }
1364
1365         while (vstart < vend) {
1366                 unsigned long this_end, paddr = __pa(vstart);
1367                 pgd_t *pgd = pgd_offset_k(vstart);
1368                 pud_t *pud;
1369                 pmd_t *pmd;
1370                 pte_t *pte;
1371
1372                 pud = pud_offset(pgd, vstart);
1373                 if (pud_none(*pud)) {
1374                         pmd_t *new;
1375
1376                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1377                         alloc_bytes += PAGE_SIZE;
1378                         pud_populate(&init_mm, pud, new);
1379                 }
1380
1381                 pmd = pmd_offset(pud, vstart);
1382                 if (!pmd_present(*pmd)) {
1383                         pte_t *new;
1384
1385                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1386                         alloc_bytes += PAGE_SIZE;
1387                         pmd_populate_kernel(&init_mm, pmd, new);
1388                 }
1389
1390                 pte = pte_offset_kernel(pmd, vstart);
1391                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1392                 if (this_end > vend)
1393                         this_end = vend;
1394
1395                 while (vstart < this_end) {
1396                         pte_val(*pte) = (paddr | pgprot_val(prot));
1397
1398                         vstart += PAGE_SIZE;
1399                         paddr += PAGE_SIZE;
1400                         pte++;
1401                 }
1402         }
1403
1404         return alloc_bytes;
1405 }
1406
1407 extern unsigned int kvmap_linear_patch[1];
1408 #endif /* CONFIG_DEBUG_PAGEALLOC */
1409
1410 static void __init kpte_set_val(unsigned long index, unsigned long val)
1411 {
1412         unsigned long *ptr = kpte_linear_bitmap;
1413
1414         val <<= ((index % (BITS_PER_LONG / 2)) * 2);
1415         ptr += (index / (BITS_PER_LONG / 2));
1416
1417         *ptr |= val;
1418 }
1419
1420 static const unsigned long kpte_shift_min = 28; /* 256MB */
1421 static const unsigned long kpte_shift_max = 34; /* 16GB */
1422 static const unsigned long kpte_shift_incr = 3;
1423
1424 static unsigned long kpte_mark_using_shift(unsigned long start, unsigned long end,
1425                                            unsigned long shift)
1426 {
1427         unsigned long size = (1UL << shift);
1428         unsigned long mask = (size - 1UL);
1429         unsigned long remains = end - start;
1430         unsigned long val;
1431
1432         if (remains < size || (start & mask))
1433                 return start;
1434
1435         /* VAL maps:
1436          *
1437          *      shift 28 --> kern_linear_pte_xor index 1
1438          *      shift 31 --> kern_linear_pte_xor index 2
1439          *      shift 34 --> kern_linear_pte_xor index 3
1440          */
1441         val = ((shift - kpte_shift_min) / kpte_shift_incr) + 1;
1442
1443         remains &= ~mask;
1444         if (shift != kpte_shift_max)
1445                 remains = size;
1446
1447         while (remains) {
1448                 unsigned long index = start >> kpte_shift_min;
1449
1450                 kpte_set_val(index, val);
1451
1452                 start += 1UL << kpte_shift_min;
1453                 remains -= 1UL << kpte_shift_min;
1454         }
1455
1456         return start;
1457 }
1458
1459 static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1460 {
1461         unsigned long smallest_size, smallest_mask;
1462         unsigned long s;
1463
1464         smallest_size = (1UL << kpte_shift_min);
1465         smallest_mask = (smallest_size - 1UL);
1466
1467         while (start < end) {
1468                 unsigned long orig_start = start;
1469
1470                 for (s = kpte_shift_max; s >= kpte_shift_min; s -= kpte_shift_incr) {
1471                         start = kpte_mark_using_shift(start, end, s);
1472
1473                         if (start != orig_start)
1474                                 break;
1475                 }
1476
1477                 if (start == orig_start)
1478                         start = (start + smallest_size) & ~smallest_mask;
1479         }
1480 }
1481
1482 static void __init init_kpte_bitmap(void)
1483 {
1484         unsigned long i;
1485
1486         for (i = 0; i < pall_ents; i++) {
1487                 unsigned long phys_start, phys_end;
1488
1489                 phys_start = pall[i].phys_addr;
1490                 phys_end = phys_start + pall[i].reg_size;
1491
1492                 mark_kpte_bitmap(phys_start, phys_end);
1493         }
1494 }
1495
1496 static void __init kernel_physical_mapping_init(void)
1497 {
1498 #ifdef CONFIG_DEBUG_PAGEALLOC
1499         unsigned long i, mem_alloced = 0UL;
1500
1501         for (i = 0; i < pall_ents; i++) {
1502                 unsigned long phys_start, phys_end;
1503
1504                 phys_start = pall[i].phys_addr;
1505                 phys_end = phys_start + pall[i].reg_size;
1506
1507                 mem_alloced += kernel_map_range(phys_start, phys_end,
1508                                                 PAGE_KERNEL);
1509         }
1510
1511         printk("Allocated %ld bytes for kernel page tables.\n",
1512                mem_alloced);
1513
1514         kvmap_linear_patch[0] = 0x01000000; /* nop */
1515         flushi(&kvmap_linear_patch[0]);
1516
1517         __flush_tlb_all();
1518 #endif
1519 }
1520
1521 #ifdef CONFIG_DEBUG_PAGEALLOC
1522 void kernel_map_pages(struct page *page, int numpages, int enable)
1523 {
1524         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1525         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1526
1527         kernel_map_range(phys_start, phys_end,
1528                          (enable ? PAGE_KERNEL : __pgprot(0)));
1529
1530         flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1531                                PAGE_OFFSET + phys_end);
1532
1533         /* we should perform an IPI and flush all tlbs,
1534          * but that can deadlock->flush only current cpu.
1535          */
1536         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1537                                  PAGE_OFFSET + phys_end);
1538 }
1539 #endif
1540
1541 unsigned long __init find_ecache_flush_span(unsigned long size)
1542 {
1543         int i;
1544
1545         for (i = 0; i < pavail_ents; i++) {
1546                 if (pavail[i].reg_size >= size)
1547                         return pavail[i].phys_addr;
1548         }
1549
1550         return ~0UL;
1551 }
1552
1553 static void __init tsb_phys_patch(void)
1554 {
1555         struct tsb_ldquad_phys_patch_entry *pquad;
1556         struct tsb_phys_patch_entry *p;
1557
1558         pquad = &__tsb_ldquad_phys_patch;
1559         while (pquad < &__tsb_ldquad_phys_patch_end) {
1560                 unsigned long addr = pquad->addr;
1561
1562                 if (tlb_type == hypervisor)
1563                         *(unsigned int *) addr = pquad->sun4v_insn;
1564                 else
1565                         *(unsigned int *) addr = pquad->sun4u_insn;
1566                 wmb();
1567                 __asm__ __volatile__("flush     %0"
1568                                      : /* no outputs */
1569                                      : "r" (addr));
1570
1571                 pquad++;
1572         }
1573
1574         p = &__tsb_phys_patch;
1575         while (p < &__tsb_phys_patch_end) {
1576                 unsigned long addr = p->addr;
1577
1578                 *(unsigned int *) addr = p->insn;
1579                 wmb();
1580                 __asm__ __volatile__("flush     %0"
1581                                      : /* no outputs */
1582                                      : "r" (addr));
1583
1584                 p++;
1585         }
1586 }
1587
1588 /* Don't mark as init, we give this to the Hypervisor.  */
1589 #ifndef CONFIG_DEBUG_PAGEALLOC
1590 #define NUM_KTSB_DESCR  2
1591 #else
1592 #define NUM_KTSB_DESCR  1
1593 #endif
1594 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1595 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1596
1597 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1598 {
1599         pa >>= KTSB_PHYS_SHIFT;
1600
1601         while (start < end) {
1602                 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1603
1604                 ia[0] = (ia[0] & ~0x3fffff) | (pa >> 10);
1605                 __asm__ __volatile__("flush     %0" : : "r" (ia));
1606
1607                 ia[1] = (ia[1] & ~0x3ff) | (pa & 0x3ff);
1608                 __asm__ __volatile__("flush     %0" : : "r" (ia + 1));
1609
1610                 start++;
1611         }
1612 }
1613
1614 static void ktsb_phys_patch(void)
1615 {
1616         extern unsigned int __swapper_tsb_phys_patch;
1617         extern unsigned int __swapper_tsb_phys_patch_end;
1618         unsigned long ktsb_pa;
1619
1620         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1621         patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1622                             &__swapper_tsb_phys_patch_end, ktsb_pa);
1623 #ifndef CONFIG_DEBUG_PAGEALLOC
1624         {
1625         extern unsigned int __swapper_4m_tsb_phys_patch;
1626         extern unsigned int __swapper_4m_tsb_phys_patch_end;
1627         ktsb_pa = (kern_base +
1628                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1629         patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1630                             &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1631         }
1632 #endif
1633 }
1634
1635 static void __init sun4v_ktsb_init(void)
1636 {
1637         unsigned long ktsb_pa;
1638
1639         /* First KTSB for PAGE_SIZE mappings.  */
1640         ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1641
1642         switch (PAGE_SIZE) {
1643         case 8 * 1024:
1644         default:
1645                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1646                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1647                 break;
1648
1649         case 64 * 1024:
1650                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1651                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1652                 break;
1653
1654         case 512 * 1024:
1655                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1656                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1657                 break;
1658
1659         case 4 * 1024 * 1024:
1660                 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1661                 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1662                 break;
1663         }
1664
1665         ktsb_descr[0].assoc = 1;
1666         ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1667         ktsb_descr[0].ctx_idx = 0;
1668         ktsb_descr[0].tsb_base = ktsb_pa;
1669         ktsb_descr[0].resv = 0;
1670
1671 #ifndef CONFIG_DEBUG_PAGEALLOC
1672         /* Second KTSB for 4MB/256MB/2GB/16GB mappings.  */
1673         ktsb_pa = (kern_base +
1674                    ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1675
1676         ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1677         ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
1678                                     HV_PGSZ_MASK_256MB |
1679                                     HV_PGSZ_MASK_2GB |
1680                                     HV_PGSZ_MASK_16GB) &
1681                                    cpu_pgsz_mask);
1682         ktsb_descr[1].assoc = 1;
1683         ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1684         ktsb_descr[1].ctx_idx = 0;
1685         ktsb_descr[1].tsb_base = ktsb_pa;
1686         ktsb_descr[1].resv = 0;
1687 #endif
1688 }
1689
1690 void __cpuinit sun4v_ktsb_register(void)
1691 {
1692         unsigned long pa, ret;
1693
1694         pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1695
1696         ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1697         if (ret != 0) {
1698                 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1699                             "errors with %lx\n", pa, ret);
1700                 prom_halt();
1701         }
1702 }
1703
1704 static void __init sun4u_linear_pte_xor_finalize(void)
1705 {
1706 #ifndef CONFIG_DEBUG_PAGEALLOC
1707         /* This is where we would add Panther support for
1708          * 32MB and 256MB pages.
1709          */
1710 #endif
1711 }
1712
1713 static void __init sun4v_linear_pte_xor_finalize(void)
1714 {
1715 #ifndef CONFIG_DEBUG_PAGEALLOC
1716         if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
1717                 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
1718                         0xfffff80000000000UL;
1719                 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1720                                            _PAGE_P_4V | _PAGE_W_4V);
1721         } else {
1722                 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
1723         }
1724
1725         if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
1726                 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
1727                         0xfffff80000000000UL;
1728                 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1729                                            _PAGE_P_4V | _PAGE_W_4V);
1730         } else {
1731                 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
1732         }
1733
1734         if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
1735                 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
1736                         0xfffff80000000000UL;
1737                 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | _PAGE_CV_4V |
1738                                            _PAGE_P_4V | _PAGE_W_4V);
1739         } else {
1740                 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
1741         }
1742 #endif
1743 }
1744
1745 /* paging_init() sets up the page tables */
1746
1747 static unsigned long last_valid_pfn;
1748 pgd_t swapper_pg_dir[2048];
1749
1750 static void sun4u_pgprot_init(void);
1751 static void sun4v_pgprot_init(void);
1752
1753 void __init paging_init(void)
1754 {
1755         unsigned long end_pfn, shift, phys_base;
1756         unsigned long real_end, i;
1757         int node;
1758
1759         /* These build time checkes make sure that the dcache_dirty_cpu()
1760          * page->flags usage will work.
1761          *
1762          * When a page gets marked as dcache-dirty, we store the
1763          * cpu number starting at bit 32 in the page->flags.  Also,
1764          * functions like clear_dcache_dirty_cpu use the cpu mask
1765          * in 13-bit signed-immediate instruction fields.
1766          */
1767
1768         /*
1769          * Page flags must not reach into upper 32 bits that are used
1770          * for the cpu number
1771          */
1772         BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1773
1774         /*
1775          * The bit fields placed in the high range must not reach below
1776          * the 32 bit boundary. Otherwise we cannot place the cpu field
1777          * at the 32 bit boundary.
1778          */
1779         BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1780                 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1781
1782         BUILD_BUG_ON(NR_CPUS > 4096);
1783
1784         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1785         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1786
1787         /* Invalidate both kernel TSBs.  */
1788         memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1789 #ifndef CONFIG_DEBUG_PAGEALLOC
1790         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1791 #endif
1792
1793         if (tlb_type == hypervisor)
1794                 sun4v_pgprot_init();
1795         else
1796                 sun4u_pgprot_init();
1797
1798         if (tlb_type == cheetah_plus ||
1799             tlb_type == hypervisor) {
1800                 tsb_phys_patch();
1801                 ktsb_phys_patch();
1802         }
1803
1804         if (tlb_type == hypervisor)
1805                 sun4v_patch_tlb_handlers();
1806
1807         /* Find available physical memory...
1808          *
1809          * Read it twice in order to work around a bug in openfirmware.
1810          * The call to grab this table itself can cause openfirmware to
1811          * allocate memory, which in turn can take away some space from
1812          * the list of available memory.  Reading it twice makes sure
1813          * we really do get the final value.
1814          */
1815         read_obp_translations();
1816         read_obp_memory("reg", &pall[0], &pall_ents);
1817         read_obp_memory("available", &pavail[0], &pavail_ents);
1818         read_obp_memory("available", &pavail[0], &pavail_ents);
1819
1820         phys_base = 0xffffffffffffffffUL;
1821         for (i = 0; i < pavail_ents; i++) {
1822                 phys_base = min(phys_base, pavail[i].phys_addr);
1823                 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
1824         }
1825
1826         memblock_reserve(kern_base, kern_size);
1827
1828         find_ramdisk(phys_base);
1829
1830         memblock_enforce_memory_limit(cmdline_memory_size);
1831
1832         memblock_allow_resize();
1833         memblock_dump_all();
1834
1835         set_bit(0, mmu_context_bmap);
1836
1837         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1838
1839         real_end = (unsigned long)_end;
1840         num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1841         printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1842                num_kernel_image_mappings);
1843
1844         /* Set kernel pgd to upper alias so physical page computations
1845          * work.
1846          */
1847         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1848
1849         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1850
1851         /* Now can init the kernel/bad page tables. */
1852         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1853                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1854
1855         inherit_prom_mappings();
1856
1857         init_kpte_bitmap();
1858
1859         /* Ok, we can use our TLB miss and window trap handlers safely.  */
1860         setup_tba();
1861
1862         __flush_tlb_all();
1863
1864         prom_build_devicetree();
1865         of_populate_present_mask();
1866 #ifndef CONFIG_SMP
1867         of_fill_in_cpu_data();
1868 #endif
1869
1870         if (tlb_type == hypervisor) {
1871                 sun4v_mdesc_init();
1872                 mdesc_populate_present_mask(cpu_all_mask);
1873 #ifndef CONFIG_SMP
1874                 mdesc_fill_in_cpu_data(cpu_all_mask);
1875 #endif
1876                 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
1877
1878                 sun4v_linear_pte_xor_finalize();
1879
1880                 sun4v_ktsb_init();
1881                 sun4v_ktsb_register();
1882         } else {
1883                 unsigned long impl, ver;
1884
1885                 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
1886                                  HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
1887
1888                 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
1889                 impl = ((ver >> 32) & 0xffff);
1890                 if (impl == PANTHER_IMPL)
1891                         cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
1892                                           HV_PGSZ_MASK_256MB);
1893
1894                 sun4u_linear_pte_xor_finalize();
1895         }
1896
1897         /* Flush the TLBs and the 4M TSB so that the updated linear
1898          * pte XOR settings are realized for all mappings.
1899          */
1900         __flush_tlb_all();
1901 #ifndef CONFIG_DEBUG_PAGEALLOC
1902         memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1903 #endif
1904         __flush_tlb_all();
1905
1906         /* Setup bootmem... */
1907         last_valid_pfn = end_pfn = bootmem_init(phys_base);
1908
1909         /* Once the OF device tree and MDESC have been setup, we know
1910          * the list of possible cpus.  Therefore we can allocate the
1911          * IRQ stacks.
1912          */
1913         for_each_possible_cpu(i) {
1914                 node = cpu_to_node(i);
1915
1916                 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
1917                                                         THREAD_SIZE,
1918                                                         THREAD_SIZE, 0);
1919                 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
1920                                                         THREAD_SIZE,
1921                                                         THREAD_SIZE, 0);
1922         }
1923
1924         kernel_physical_mapping_init();
1925
1926         {
1927                 unsigned long max_zone_pfns[MAX_NR_ZONES];
1928
1929                 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1930
1931                 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1932
1933                 free_area_init_nodes(max_zone_pfns);
1934         }
1935
1936         printk("Booting Linux...\n");
1937 }
1938
1939 int page_in_phys_avail(unsigned long paddr)
1940 {
1941         int i;
1942
1943         paddr &= PAGE_MASK;
1944
1945         for (i = 0; i < pavail_ents; i++) {
1946                 unsigned long start, end;
1947
1948                 start = pavail[i].phys_addr;
1949                 end = start + pavail[i].reg_size;
1950
1951                 if (paddr >= start && paddr < end)
1952                         return 1;
1953         }
1954         if (paddr >= kern_base && paddr < (kern_base + kern_size))
1955                 return 1;
1956 #ifdef CONFIG_BLK_DEV_INITRD
1957         if (paddr >= __pa(initrd_start) &&
1958             paddr < __pa(PAGE_ALIGN(initrd_end)))
1959                 return 1;
1960 #endif
1961
1962         return 0;
1963 }
1964
1965 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1966 static int pavail_rescan_ents __initdata;
1967
1968 /* Certain OBP calls, such as fetching "available" properties, can
1969  * claim physical memory.  So, along with initializing the valid
1970  * address bitmap, what we do here is refetch the physical available
1971  * memory list again, and make sure it provides at least as much
1972  * memory as 'pavail' does.
1973  */
1974 static void __init setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap)
1975 {
1976         int i;
1977
1978         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1979
1980         for (i = 0; i < pavail_ents; i++) {
1981                 unsigned long old_start, old_end;
1982
1983                 old_start = pavail[i].phys_addr;
1984                 old_end = old_start + pavail[i].reg_size;
1985                 while (old_start < old_end) {
1986                         int n;
1987
1988                         for (n = 0; n < pavail_rescan_ents; n++) {
1989                                 unsigned long new_start, new_end;
1990
1991                                 new_start = pavail_rescan[n].phys_addr;
1992                                 new_end = new_start +
1993                                         pavail_rescan[n].reg_size;
1994
1995                                 if (new_start <= old_start &&
1996                                     new_end >= (old_start + PAGE_SIZE)) {
1997                                         set_bit(old_start >> 22, bitmap);
1998                                         goto do_next_page;
1999                                 }
2000                         }
2001
2002                         prom_printf("mem_init: Lost memory in pavail\n");
2003                         prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
2004                                     pavail[i].phys_addr,
2005                                     pavail[i].reg_size);
2006                         prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
2007                                     pavail_rescan[i].phys_addr,
2008                                     pavail_rescan[i].reg_size);
2009                         prom_printf("mem_init: Cannot continue, aborting.\n");
2010                         prom_halt();
2011
2012                 do_next_page:
2013                         old_start += PAGE_SIZE;
2014                 }
2015         }
2016 }
2017
2018 static void __init patch_tlb_miss_handler_bitmap(void)
2019 {
2020         extern unsigned int valid_addr_bitmap_insn[];
2021         extern unsigned int valid_addr_bitmap_patch[];
2022
2023         valid_addr_bitmap_insn[1] = valid_addr_bitmap_patch[1];
2024         mb();
2025         valid_addr_bitmap_insn[0] = valid_addr_bitmap_patch[0];
2026         flushi(&valid_addr_bitmap_insn[0]);
2027 }
2028
2029 static void __init register_page_bootmem_info(void)
2030 {
2031 #ifdef CONFIG_NEED_MULTIPLE_NODES
2032         int i;
2033
2034         for_each_online_node(i)
2035                 if (NODE_DATA(i)->node_spanned_pages)
2036                         register_page_bootmem_info_node(NODE_DATA(i));
2037 #endif
2038 }
2039 void __init mem_init(void)
2040 {
2041         unsigned long codepages, datapages, initpages;
2042         unsigned long addr, last;
2043
2044         addr = PAGE_OFFSET + kern_base;
2045         last = PAGE_ALIGN(kern_size) + addr;
2046         while (addr < last) {
2047                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
2048                 addr += PAGE_SIZE;
2049         }
2050
2051         setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap);
2052         patch_tlb_miss_handler_bitmap();
2053
2054         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2055
2056         register_page_bootmem_info();
2057         totalram_pages = free_all_bootmem();
2058
2059         /* We subtract one to account for the mem_map_zero page
2060          * allocated below.
2061          */
2062         num_physpages = totalram_pages - 1;
2063
2064         /*
2065          * Set up the zero page, mark it reserved, so that page count
2066          * is not manipulated when freeing the page from user ptes.
2067          */
2068         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2069         if (mem_map_zero == NULL) {
2070                 prom_printf("paging_init: Cannot alloc zero page.\n");
2071                 prom_halt();
2072         }
2073         mark_page_reserved(mem_map_zero);
2074
2075         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
2076         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
2077         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
2078         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
2079         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
2080         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
2081
2082         printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
2083                nr_free_pages() << (PAGE_SHIFT-10),
2084                codepages << (PAGE_SHIFT-10),
2085                datapages << (PAGE_SHIFT-10),
2086                initpages << (PAGE_SHIFT-10),
2087                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
2088
2089         if (tlb_type == cheetah || tlb_type == cheetah_plus)
2090                 cheetah_ecache_flush_init();
2091 }
2092
2093 void free_initmem(void)
2094 {
2095         unsigned long addr, initend;
2096         int do_free = 1;
2097
2098         /* If the physical memory maps were trimmed by kernel command
2099          * line options, don't even try freeing this initmem stuff up.
2100          * The kernel image could have been in the trimmed out region
2101          * and if so the freeing below will free invalid page structs.
2102          */
2103         if (cmdline_memory_size)
2104                 do_free = 0;
2105
2106         /*
2107          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2108          */
2109         addr = PAGE_ALIGN((unsigned long)(__init_begin));
2110         initend = (unsigned long)(__init_end) & PAGE_MASK;
2111         for (; addr < initend; addr += PAGE_SIZE) {
2112                 unsigned long page;
2113
2114                 page = (addr +
2115                         ((unsigned long) __va(kern_base)) -
2116                         ((unsigned long) KERNBASE));
2117                 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2118
2119                 if (do_free)
2120                         free_reserved_page(virt_to_page(page));
2121         }
2122 }
2123
2124 #ifdef CONFIG_BLK_DEV_INITRD
2125 void free_initrd_mem(unsigned long start, unsigned long end)
2126 {
2127         num_physpages += free_reserved_area(start, end, POISON_FREE_INITMEM,
2128                                             "initrd");
2129 }
2130 #endif
2131
2132 #define _PAGE_CACHE_4U  (_PAGE_CP_4U | _PAGE_CV_4U)
2133 #define _PAGE_CACHE_4V  (_PAGE_CP_4V | _PAGE_CV_4V)
2134 #define __DIRTY_BITS_4U  (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2135 #define __DIRTY_BITS_4V  (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2136 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2137 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2138
2139 pgprot_t PAGE_KERNEL __read_mostly;
2140 EXPORT_SYMBOL(PAGE_KERNEL);
2141
2142 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2143 pgprot_t PAGE_COPY __read_mostly;
2144
2145 pgprot_t PAGE_SHARED __read_mostly;
2146 EXPORT_SYMBOL(PAGE_SHARED);
2147
2148 unsigned long pg_iobits __read_mostly;
2149
2150 unsigned long _PAGE_IE __read_mostly;
2151 EXPORT_SYMBOL(_PAGE_IE);
2152
2153 unsigned long _PAGE_E __read_mostly;
2154 EXPORT_SYMBOL(_PAGE_E);
2155
2156 unsigned long _PAGE_CACHE __read_mostly;
2157 EXPORT_SYMBOL(_PAGE_CACHE);
2158
2159 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2160 unsigned long vmemmap_table[VMEMMAP_SIZE];
2161
2162 static long __meminitdata addr_start, addr_end;
2163 static int __meminitdata node_start;
2164
2165 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2166                                int node)
2167 {
2168         unsigned long phys_start = (vstart - VMEMMAP_BASE);
2169         unsigned long phys_end = (vend - VMEMMAP_BASE);
2170         unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2171         unsigned long end = VMEMMAP_ALIGN(phys_end);
2172         unsigned long pte_base;
2173
2174         pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2175                     _PAGE_CP_4U | _PAGE_CV_4U |
2176                     _PAGE_P_4U | _PAGE_W_4U);
2177         if (tlb_type == hypervisor)
2178                 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2179                             _PAGE_CP_4V | _PAGE_CV_4V |
2180                             _PAGE_P_4V | _PAGE_W_4V);
2181
2182         for (; addr < end; addr += VMEMMAP_CHUNK) {
2183                 unsigned long *vmem_pp =
2184                         vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2185                 void *block;
2186
2187                 if (!(*vmem_pp & _PAGE_VALID)) {
2188                         block = vmemmap_alloc_block(1UL << 22, node);
2189                         if (!block)
2190                                 return -ENOMEM;
2191
2192                         *vmem_pp = pte_base | __pa(block);
2193
2194                         /* check to see if we have contiguous blocks */
2195                         if (addr_end != addr || node_start != node) {
2196                                 if (addr_start)
2197                                         printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2198                                                addr_start, addr_end-1, node_start);
2199                                 addr_start = addr;
2200                                 node_start = node;
2201                         }
2202                         addr_end = addr + VMEMMAP_CHUNK;
2203                 }
2204         }
2205         return 0;
2206 }
2207
2208 void __meminit vmemmap_populate_print_last(void)
2209 {
2210         if (addr_start) {
2211                 printk(KERN_DEBUG " [%lx-%lx] on node %d\n",
2212                        addr_start, addr_end-1, node_start);
2213                 addr_start = 0;
2214                 addr_end = 0;
2215                 node_start = 0;
2216         }
2217 }
2218
2219 void vmemmap_free(unsigned long start, unsigned long end)
2220 {
2221 }
2222
2223 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2224
2225 static void prot_init_common(unsigned long page_none,
2226                              unsigned long page_shared,
2227                              unsigned long page_copy,
2228                              unsigned long page_readonly,
2229                              unsigned long page_exec_bit)
2230 {
2231         PAGE_COPY = __pgprot(page_copy);
2232         PAGE_SHARED = __pgprot(page_shared);
2233
2234         protection_map[0x0] = __pgprot(page_none);
2235         protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2236         protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2237         protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2238         protection_map[0x4] = __pgprot(page_readonly);
2239         protection_map[0x5] = __pgprot(page_readonly);
2240         protection_map[0x6] = __pgprot(page_copy);
2241         protection_map[0x7] = __pgprot(page_copy);
2242         protection_map[0x8] = __pgprot(page_none);
2243         protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2244         protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2245         protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2246         protection_map[0xc] = __pgprot(page_readonly);
2247         protection_map[0xd] = __pgprot(page_readonly);
2248         protection_map[0xe] = __pgprot(page_shared);
2249         protection_map[0xf] = __pgprot(page_shared);
2250 }
2251
2252 static void __init sun4u_pgprot_init(void)
2253 {
2254         unsigned long page_none, page_shared, page_copy, page_readonly;
2255         unsigned long page_exec_bit;
2256         int i;
2257
2258         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2259                                 _PAGE_CACHE_4U | _PAGE_P_4U |
2260                                 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2261                                 _PAGE_EXEC_4U);
2262         PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2263                                        _PAGE_CACHE_4U | _PAGE_P_4U |
2264                                        __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2265                                        _PAGE_EXEC_4U | _PAGE_L_4U);
2266
2267         _PAGE_IE = _PAGE_IE_4U;
2268         _PAGE_E = _PAGE_E_4U;
2269         _PAGE_CACHE = _PAGE_CACHE_4U;
2270
2271         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2272                      __ACCESS_BITS_4U | _PAGE_E_4U);
2273
2274 #ifdef CONFIG_DEBUG_PAGEALLOC
2275         kern_linear_pte_xor[0] = _PAGE_VALID ^ 0xfffff80000000000UL;
2276 #else
2277         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2278                 0xfffff80000000000UL;
2279 #endif
2280         kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2281                                    _PAGE_P_4U | _PAGE_W_4U);
2282
2283         for (i = 1; i < 4; i++)
2284                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2285
2286         _PAGE_ALL_SZ_BITS =  (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2287                               _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2288                               _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2289
2290
2291         page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2292         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2293                        __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2294         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2295                        __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2296         page_readonly   = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2297                            __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2298
2299         page_exec_bit = _PAGE_EXEC_4U;
2300
2301         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2302                          page_exec_bit);
2303 }
2304
2305 static void __init sun4v_pgprot_init(void)
2306 {
2307         unsigned long page_none, page_shared, page_copy, page_readonly;
2308         unsigned long page_exec_bit;
2309         int i;
2310
2311         PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2312                                 _PAGE_CACHE_4V | _PAGE_P_4V |
2313                                 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2314                                 _PAGE_EXEC_4V);
2315         PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2316
2317         _PAGE_IE = _PAGE_IE_4V;
2318         _PAGE_E = _PAGE_E_4V;
2319         _PAGE_CACHE = _PAGE_CACHE_4V;
2320
2321 #ifdef CONFIG_DEBUG_PAGEALLOC
2322         kern_linear_pte_xor[0] = _PAGE_VALID ^ 0xfffff80000000000UL;
2323 #else
2324         kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2325                 0xfffff80000000000UL;
2326 #endif
2327         kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2328                                    _PAGE_P_4V | _PAGE_W_4V);
2329
2330         for (i = 1; i < 4; i++)
2331                 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2332
2333         pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2334                      __ACCESS_BITS_4V | _PAGE_E_4V);
2335
2336         _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2337                              _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2338                              _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2339                              _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2340
2341         page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2342         page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2343                        __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2344         page_copy   = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2345                        __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2346         page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2347                          __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2348
2349         page_exec_bit = _PAGE_EXEC_4V;
2350
2351         prot_init_common(page_none, page_shared, page_copy, page_readonly,
2352                          page_exec_bit);
2353 }
2354
2355 unsigned long pte_sz_bits(unsigned long sz)
2356 {
2357         if (tlb_type == hypervisor) {
2358                 switch (sz) {
2359                 case 8 * 1024:
2360                 default:
2361                         return _PAGE_SZ8K_4V;
2362                 case 64 * 1024:
2363                         return _PAGE_SZ64K_4V;
2364                 case 512 * 1024:
2365                         return _PAGE_SZ512K_4V;
2366                 case 4 * 1024 * 1024:
2367                         return _PAGE_SZ4MB_4V;
2368                 }
2369         } else {
2370                 switch (sz) {
2371                 case 8 * 1024:
2372                 default:
2373                         return _PAGE_SZ8K_4U;
2374                 case 64 * 1024:
2375                         return _PAGE_SZ64K_4U;
2376                 case 512 * 1024:
2377                         return _PAGE_SZ512K_4U;
2378                 case 4 * 1024 * 1024:
2379                         return _PAGE_SZ4MB_4U;
2380                 }
2381         }
2382 }
2383
2384 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2385 {
2386         pte_t pte;
2387
2388         pte_val(pte)  = page | pgprot_val(pgprot_noncached(prot));
2389         pte_val(pte) |= (((unsigned long)space) << 32);
2390         pte_val(pte) |= pte_sz_bits(page_size);
2391
2392         return pte;
2393 }
2394
2395 static unsigned long kern_large_tte(unsigned long paddr)
2396 {
2397         unsigned long val;
2398
2399         val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2400                _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2401                _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2402         if (tlb_type == hypervisor)
2403                 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2404                        _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2405                        _PAGE_EXEC_4V | _PAGE_W_4V);
2406
2407         return val | paddr;
2408 }
2409
2410 /* If not locked, zap it. */
2411 void __flush_tlb_all(void)
2412 {
2413         unsigned long pstate;
2414         int i;
2415
2416         __asm__ __volatile__("flushw\n\t"
2417                              "rdpr      %%pstate, %0\n\t"
2418                              "wrpr      %0, %1, %%pstate"
2419                              : "=r" (pstate)
2420                              : "i" (PSTATE_IE));
2421         if (tlb_type == hypervisor) {
2422                 sun4v_mmu_demap_all();
2423         } else if (tlb_type == spitfire) {
2424                 for (i = 0; i < 64; i++) {
2425                         /* Spitfire Errata #32 workaround */
2426                         /* NOTE: Always runs on spitfire, so no
2427                          *       cheetah+ page size encodings.
2428                          */
2429                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2430                                              "flush     %%g6"
2431                                              : /* No outputs */
2432                                              : "r" (0),
2433                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2434
2435                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2436                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2437                                                      "membar #Sync"
2438                                                      : /* no outputs */
2439                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2440                                 spitfire_put_dtlb_data(i, 0x0UL);
2441                         }
2442
2443                         /* Spitfire Errata #32 workaround */
2444                         /* NOTE: Always runs on spitfire, so no
2445                          *       cheetah+ page size encodings.
2446                          */
2447                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
2448                                              "flush     %%g6"
2449                                              : /* No outputs */
2450                                              : "r" (0),
2451                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2452
2453                         if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2454                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2455                                                      "membar #Sync"
2456                                                      : /* no outputs */
2457                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2458                                 spitfire_put_itlb_data(i, 0x0UL);
2459                         }
2460                 }
2461         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2462                 cheetah_flush_dtlb_all();
2463                 cheetah_flush_itlb_all();
2464         }
2465         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
2466                              : : "r" (pstate));
2467 }
2468
2469 static pte_t *get_from_cache(struct mm_struct *mm)
2470 {
2471         struct page *page;
2472         pte_t *ret;
2473
2474         spin_lock(&mm->page_table_lock);
2475         page = mm->context.pgtable_page;
2476         ret = NULL;
2477         if (page) {
2478                 void *p = page_address(page);
2479
2480                 mm->context.pgtable_page = NULL;
2481
2482                 ret = (pte_t *) (p + (PAGE_SIZE / 2));
2483         }
2484         spin_unlock(&mm->page_table_lock);
2485
2486         return ret;
2487 }
2488
2489 static struct page *__alloc_for_cache(struct mm_struct *mm)
2490 {
2491         struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK |
2492                                        __GFP_REPEAT | __GFP_ZERO);
2493
2494         if (page) {
2495                 spin_lock(&mm->page_table_lock);
2496                 if (!mm->context.pgtable_page) {
2497                         atomic_set(&page->_count, 2);
2498                         mm->context.pgtable_page = page;
2499                 }
2500                 spin_unlock(&mm->page_table_lock);
2501         }
2502         return page;
2503 }
2504
2505 pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2506                             unsigned long address)
2507 {
2508         struct page *page;
2509         pte_t *pte;
2510
2511         pte = get_from_cache(mm);
2512         if (pte)
2513                 return pte;
2514
2515         page = __alloc_for_cache(mm);
2516         if (page)
2517                 pte = (pte_t *) page_address(page);
2518
2519         return pte;
2520 }
2521
2522 pgtable_t pte_alloc_one(struct mm_struct *mm,
2523                         unsigned long address)
2524 {
2525         struct page *page;
2526         pte_t *pte;
2527
2528         pte = get_from_cache(mm);
2529         if (pte)
2530                 return pte;
2531
2532         page = __alloc_for_cache(mm);
2533         if (page) {
2534                 pgtable_page_ctor(page);
2535                 pte = (pte_t *) page_address(page);
2536         }
2537
2538         return pte;
2539 }
2540
2541 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2542 {
2543         struct page *page = virt_to_page(pte);
2544         if (put_page_testzero(page))
2545                 free_hot_cold_page(page, 0);
2546 }
2547
2548 static void __pte_free(pgtable_t pte)
2549 {
2550         struct page *page = virt_to_page(pte);
2551         if (put_page_testzero(page)) {
2552                 pgtable_page_dtor(page);
2553                 free_hot_cold_page(page, 0);
2554         }
2555 }
2556
2557 void pte_free(struct mm_struct *mm, pgtable_t pte)
2558 {
2559         __pte_free(pte);
2560 }
2561
2562 void pgtable_free(void *table, bool is_page)
2563 {
2564         if (is_page)
2565                 __pte_free(table);
2566         else
2567                 kmem_cache_free(pgtable_cache, table);
2568 }
2569
2570 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2571 static pmd_t pmd_set_protbits(pmd_t pmd, pgprot_t pgprot, bool for_modify)
2572 {
2573         if (pgprot_val(pgprot) & _PAGE_VALID)
2574                 pmd_val(pmd) |= PMD_HUGE_PRESENT;
2575         if (tlb_type == hypervisor) {
2576                 if (pgprot_val(pgprot) & _PAGE_WRITE_4V)
2577                         pmd_val(pmd) |= PMD_HUGE_WRITE;
2578                 if (pgprot_val(pgprot) & _PAGE_EXEC_4V)
2579                         pmd_val(pmd) |= PMD_HUGE_EXEC;
2580
2581                 if (!for_modify) {
2582                         if (pgprot_val(pgprot) & _PAGE_ACCESSED_4V)
2583                                 pmd_val(pmd) |= PMD_HUGE_ACCESSED;
2584                         if (pgprot_val(pgprot) & _PAGE_MODIFIED_4V)
2585                                 pmd_val(pmd) |= PMD_HUGE_DIRTY;
2586                 }
2587         } else {
2588                 if (pgprot_val(pgprot) & _PAGE_WRITE_4U)
2589                         pmd_val(pmd) |= PMD_HUGE_WRITE;
2590                 if (pgprot_val(pgprot) & _PAGE_EXEC_4U)
2591                         pmd_val(pmd) |= PMD_HUGE_EXEC;
2592
2593                 if (!for_modify) {
2594                         if (pgprot_val(pgprot) & _PAGE_ACCESSED_4U)
2595                                 pmd_val(pmd) |= PMD_HUGE_ACCESSED;
2596                         if (pgprot_val(pgprot) & _PAGE_MODIFIED_4U)
2597                                 pmd_val(pmd) |= PMD_HUGE_DIRTY;
2598                 }
2599         }
2600
2601         return pmd;
2602 }
2603
2604 pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot)
2605 {
2606         pmd_t pmd;
2607
2608         pmd_val(pmd) = (page_nr << ((PAGE_SHIFT - PMD_PADDR_SHIFT)));
2609         pmd_val(pmd) |= PMD_ISHUGE;
2610         pmd = pmd_set_protbits(pmd, pgprot, false);
2611         return pmd;
2612 }
2613
2614 pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
2615 {
2616         pmd_val(pmd) &= ~(PMD_HUGE_PRESENT |
2617                           PMD_HUGE_WRITE |
2618                           PMD_HUGE_EXEC);
2619         pmd = pmd_set_protbits(pmd, newprot, true);
2620         return pmd;
2621 }
2622
2623 pgprot_t pmd_pgprot(pmd_t entry)
2624 {
2625         unsigned long pte = 0;
2626
2627         if (pmd_val(entry) & PMD_HUGE_PRESENT)
2628                 pte |= _PAGE_VALID;
2629
2630         if (tlb_type == hypervisor) {
2631                 if (pmd_val(entry) & PMD_HUGE_PRESENT)
2632                         pte |= _PAGE_PRESENT_4V;
2633                 if (pmd_val(entry) & PMD_HUGE_EXEC)
2634                         pte |= _PAGE_EXEC_4V;
2635                 if (pmd_val(entry) & PMD_HUGE_WRITE)
2636                         pte |= _PAGE_W_4V;
2637                 if (pmd_val(entry) & PMD_HUGE_ACCESSED)
2638                         pte |= _PAGE_ACCESSED_4V;
2639                 if (pmd_val(entry) & PMD_HUGE_DIRTY)
2640                         pte |= _PAGE_MODIFIED_4V;
2641                 pte |= _PAGE_CP_4V|_PAGE_CV_4V;
2642         } else {
2643                 if (pmd_val(entry) & PMD_HUGE_PRESENT)
2644                         pte |= _PAGE_PRESENT_4U;
2645                 if (pmd_val(entry) & PMD_HUGE_EXEC)
2646                         pte |= _PAGE_EXEC_4U;
2647                 if (pmd_val(entry) & PMD_HUGE_WRITE)
2648                         pte |= _PAGE_W_4U;
2649                 if (pmd_val(entry) & PMD_HUGE_ACCESSED)
2650                         pte |= _PAGE_ACCESSED_4U;
2651                 if (pmd_val(entry) & PMD_HUGE_DIRTY)
2652                         pte |= _PAGE_MODIFIED_4U;
2653                 pte |= _PAGE_CP_4U|_PAGE_CV_4U;
2654         }
2655
2656         return __pgprot(pte);
2657 }
2658
2659 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2660                           pmd_t *pmd)
2661 {
2662         unsigned long pte, flags;
2663         struct mm_struct *mm;
2664         pmd_t entry = *pmd;
2665         pgprot_t prot;
2666
2667         if (!pmd_large(entry) || !pmd_young(entry))
2668                 return;
2669
2670         pte = (pmd_val(entry) & ~PMD_HUGE_PROTBITS);
2671         pte <<= PMD_PADDR_SHIFT;
2672         pte |= _PAGE_VALID;
2673
2674         prot = pmd_pgprot(entry);
2675
2676         if (tlb_type == hypervisor)
2677                 pgprot_val(prot) |= _PAGE_SZHUGE_4V;
2678         else
2679                 pgprot_val(prot) |= _PAGE_SZHUGE_4U;
2680
2681         pte |= pgprot_val(prot);
2682
2683         mm = vma->vm_mm;
2684
2685         spin_lock_irqsave(&mm->context.lock, flags);
2686
2687         if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2688                 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, HPAGE_SHIFT,
2689                                         addr, pte);
2690
2691         spin_unlock_irqrestore(&mm->context.lock, flags);
2692 }
2693 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2694
2695 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2696 static void context_reload(void *__data)
2697 {
2698         struct mm_struct *mm = __data;
2699
2700         if (mm == current->mm)
2701                 load_secondary_context(mm);
2702 }
2703
2704 void hugetlb_setup(struct pt_regs *regs)
2705 {
2706         struct mm_struct *mm = current->mm;
2707         struct tsb_config *tp;
2708
2709         if (in_atomic() || !mm) {
2710                 const struct exception_table_entry *entry;
2711
2712                 entry = search_exception_tables(regs->tpc);
2713                 if (entry) {
2714                         regs->tpc = entry->fixup;
2715                         regs->tnpc = regs->tpc + 4;
2716                         return;
2717                 }
2718                 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
2719                 die_if_kernel("HugeTSB in atomic", regs);
2720         }
2721
2722         tp = &mm->context.tsb_block[MM_TSB_HUGE];
2723         if (likely(tp->tsb == NULL))
2724                 tsb_grow(mm, MM_TSB_HUGE, 0);
2725
2726         tsb_context_switch(mm);
2727         smp_tsb_sync(mm);
2728
2729         /* On UltraSPARC-III+ and later, configure the second half of
2730          * the Data-TLB for huge pages.
2731          */
2732         if (tlb_type == cheetah_plus) {
2733                 unsigned long ctx;
2734
2735                 spin_lock(&ctx_alloc_lock);
2736                 ctx = mm->context.sparc64_ctx_val;
2737                 ctx &= ~CTX_PGSZ_MASK;
2738                 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
2739                 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
2740
2741                 if (ctx != mm->context.sparc64_ctx_val) {
2742                         /* When changing the page size fields, we
2743                          * must perform a context flush so that no
2744                          * stale entries match.  This flush must
2745                          * occur with the original context register
2746                          * settings.
2747                          */
2748                         do_flush_tlb_mm(mm);
2749
2750                         /* Reload the context register of all processors
2751                          * also executing in this address space.
2752                          */
2753                         mm->context.sparc64_ctx_val = ctx;
2754                         on_each_cpu(context_reload, mm, 0);
2755                 }
2756                 spin_unlock(&ctx_alloc_lock);
2757         }
2758 }
2759 #endif