arch/sparc/kernel/smp_64.c

   1 /* smp.c: Sparc64 SMP support.
   2  *
   3  * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/kernel.h>
   8 #include <linux/sched.h>
   9 #include <linux/mm.h>
  10 #include <linux/pagemap.h>
  11 #include <linux/threads.h>
  12 #include <linux/smp.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/delay.h>
  16 #include <linux/init.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/fs.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/cache.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/profile.h>
  23 #include <linux/lmb.h>
  24 #include <linux/cpu.h>
  25
  26 #include <asm/head.h>
  27 #include <asm/ptrace.h>
  28 #include <asm/atomic.h>
  29 #include <asm/tlbflush.h>
  30 #include <asm/mmu_context.h>
  31 #include <asm/cpudata.h>
  32 #include <asm/hvtramp.h>
  33 #include <asm/io.h>
  34 #include <asm/timer.h>
  35
  36 #include <asm/irq.h>
  37 #include <asm/irq_regs.h>
  38 #include <asm/page.h>
  39 #include <asm/pgtable.h>
  40 #include <asm/oplib.h>
  41 #include <asm/uaccess.h>
  42 #include <asm/starfire.h>
  43 #include <asm/tlb.h>
  44 #include <asm/sections.h>
  45 #include <asm/prom.h>
  46 #include <asm/mdesc.h>
  47 #include <asm/ldc.h>
  48 #include <asm/hypervisor.h>
  49
  50 int sparc64_multi_core __read_mostly;
  51
  52 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
  53 cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
  54         { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
  55
  56 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
  57 EXPORT_SYMBOL(cpu_core_map);
  58
  59 static cpumask_t smp_commenced_mask;
  60
  61 void smp_info(struct seq_file *m)
  62 {
  63         int i;
  64
  65         seq_printf(m, "State:\n");
  66         for_each_online_cpu(i)
  67                 seq_printf(m, "CPU%d:\t\tonline\n", i);
  68 }
  69
  70 void smp_bogo(struct seq_file *m)
  71 {
  72         int i;
  73
  74         for_each_online_cpu(i)
  75                 seq_printf(m,
  76                            "Cpu%dClkTck\t: %016lx\n",
  77                            i, cpu_data(i).clock_tick);
  78 }
  79
  80 extern void setup_sparc64_timer(void);
  81
  82 static volatile unsigned long callin_flag = 0;
  83
  84 void __cpuinit smp_callin(void)
  85 {
  86         int cpuid = hard_smp_processor_id();
  87
  88         __local_per_cpu_offset = __per_cpu_offset(cpuid);
  89
  90         if (tlb_type == hypervisor)
  91                 sun4v_ktsb_register();
  92
  93         __flush_tlb_all();
  94
  95         setup_sparc64_timer();
  96
  97         if (cheetah_pcache_forced_on)
  98                 cheetah_enable_pcache();
  99
 100         local_irq_enable();
 101
 102         callin_flag = 1;
 103         __asm__ __volatile__("membar #Sync\n\t"
 104                              "flush  %%g6" : : : "memory");
 105
 106         /* Clear this or we will die instantly when we
 107          * schedule back to this idler...
 108          */
 109         current_thread_info()->new_child = 0;
 110
 111         /* Attach to the address space of init_task. */
 112         atomic_inc(&init_mm.mm_count);
 113         current->active_mm = &init_mm;
 114
 115         /* inform the notifiers about the new cpu */
 116         notify_cpu_starting(cpuid);
 117
 118         while (!cpu_isset(cpuid, smp_commenced_mask))
 119                 rmb();
 120
 121         ipi_call_lock_irq();
 122         cpu_set(cpuid, cpu_online_map);
 123         ipi_call_unlock_irq();
 124
 125         /* idle thread is expected to have preempt disabled */
 126         preempt_disable();
 127 }
 128
 129 void cpu_panic(void)
 130 {
 131         printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
 132         panic("SMP bolixed\n");
 133 }
 134
 135 /* This tick register synchronization scheme is taken entirely from
 136  * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
 137  *
 138  * The only change I've made is to rework it so that the master
 139  * initiates the synchonization instead of the slave. -DaveM
 140  */
 141
 142 #define MASTER  0
 143 #define SLAVE   (SMP_CACHE_BYTES/sizeof(unsigned long))
 144
 145 #define NUM_ROUNDS      64      /* magic value */
 146 #define NUM_ITERS       5       /* likewise */
 147
 148 static DEFINE_SPINLOCK(itc_sync_lock);
 149 static unsigned long go[SLAVE + 1];
 150
 151 #define DEBUG_TICK_SYNC 0
 152
 153 static inline long get_delta (long *rt, long *master)
 154 {
 155         unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
 156         unsigned long tcenter, t0, t1, tm;
 157         unsigned long i;
 158
 159         for (i = 0; i < NUM_ITERS; i++) {
 160                 t0 = tick_ops->get_tick();
 161                 go[MASTER] = 1;
 162                 membar_safe("#StoreLoad");
 163                 while (!(tm = go[SLAVE]))
 164                         rmb();
 165                 go[SLAVE] = 0;
 166                 wmb();
 167                 t1 = tick_ops->get_tick();
 168
 169                 if (t1 - t0 < best_t1 - best_t0)
 170                         best_t0 = t0, best_t1 = t1, best_tm = tm;
 171         }
 172
 173         *rt = best_t1 - best_t0;
 174         *master = best_tm - best_t0;
 175
 176         /* average best_t0 and best_t1 without overflow: */
 177         tcenter = (best_t0/2 + best_t1/2);
 178         if (best_t0 % 2 + best_t1 % 2 == 2)
 179                 tcenter++;
 180         return tcenter - best_tm;
 181 }
 182
 183 void smp_synchronize_tick_client(void)
 184 {
 185         long i, delta, adj, adjust_latency = 0, done = 0;
 186         unsigned long flags, rt, master_time_stamp, bound;
 187 #if DEBUG_TICK_SYNC
 188         struct {
 189                 long rt;        /* roundtrip time */
 190                 long master;    /* master's timestamp */
 191                 long diff;      /* difference between midpoint and master's timestamp */
 192                 long lat;       /* estimate of itc adjustment latency */
 193         } t[NUM_ROUNDS];
 194 #endif
 195
 196         go[MASTER] = 1;
 197
 198         while (go[MASTER])
 199                 rmb();
 200
 201         local_irq_save(flags);
 202         {
 203                 for (i = 0; i < NUM_ROUNDS; i++) {
 204                         delta = get_delta(&rt, &master_time_stamp);
 205                         if (delta == 0) {
 206                                 done = 1;       /* let's lock on to this... */
 207                                 bound = rt;
 208                         }
 209
 210                         if (!done) {
 211                                 if (i > 0) {
 212                                         adjust_latency += -delta;
 213                                         adj = -delta + adjust_latency/4;
 214                                 } else
 215                                         adj = -delta;
 216
 217                                 tick_ops->add_tick(adj);
 218                         }
 219 #if DEBUG_TICK_SYNC
 220                         t[i].rt = rt;
 221                         t[i].master = master_time_stamp;
 222                         t[i].diff = delta;
 223                         t[i].lat = adjust_latency/4;
 224 #endif
 225                 }
 226         }
 227         local_irq_restore(flags);
 228
 229 #if DEBUG_TICK_SYNC
 230         for (i = 0; i < NUM_ROUNDS; i++)
 231                 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
 232                        t[i].rt, t[i].master, t[i].diff, t[i].lat);
 233 #endif
 234
 235         printk(KERN_INFO "CPU %d: synchronized TICK with master CPU "
 236                "(last diff %ld cycles, maxerr %lu cycles)\n",
 237                smp_processor_id(), delta, rt);
 238 }
 239
 240 static void smp_start_sync_tick_client(int cpu);
 241
 242 static void smp_synchronize_one_tick(int cpu)
 243 {
 244         unsigned long flags, i;
 245
 246         go[MASTER] = 0;
 247
 248         smp_start_sync_tick_client(cpu);
 249
 250         /* wait for client to be ready */
 251         while (!go[MASTER])
 252                 rmb();
 253
 254         /* now let the client proceed into his loop */
 255         go[MASTER] = 0;
 256         membar_safe("#StoreLoad");
 257
 258         spin_lock_irqsave(&itc_sync_lock, flags);
 259         {
 260                 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
 261                         while (!go[MASTER])
 262                                 rmb();
 263                         go[MASTER] = 0;
 264                         wmb();
 265                         go[SLAVE] = tick_ops->get_tick();
 266                         membar_safe("#StoreLoad");
 267                 }
 268         }
 269         spin_unlock_irqrestore(&itc_sync_lock, flags);
 270 }
 271
 272 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
 273 /* XXX Put this in some common place. XXX */
 274 static unsigned long kimage_addr_to_ra(void *p)
 275 {
 276         unsigned long val = (unsigned long) p;
 277
 278         return kern_base + (val - KERNBASE);
 279 }
 280
 281 static void __cpuinit ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg, void **descrp)
 282 {
 283         extern unsigned long sparc64_ttable_tl0;
 284         extern unsigned long kern_locked_tte_data;
 285         struct hvtramp_descr *hdesc;
 286         unsigned long trampoline_ra;
 287         struct trap_per_cpu *tb;
 288         u64 tte_vaddr, tte_data;
 289         unsigned long hv_err;
 290         int i;
 291
 292         hdesc = kzalloc(sizeof(*hdesc) +
 293                         (sizeof(struct hvtramp_mapping) *
 294                          num_kernel_image_mappings - 1),
 295                         GFP_KERNEL);
 296         if (!hdesc) {
 297                 printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
 298                        "hvtramp_descr.\n");
 299                 return;
 300         }
 301         *descrp = hdesc;
 302
 303         hdesc->cpu = cpu;
 304         hdesc->num_mappings = num_kernel_image_mappings;
 305
 306         tb = &trap_block[cpu];
 307
 308         hdesc->fault_info_va = (unsigned long) &tb->fault_info;
 309         hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
 310
 311         hdesc->thread_reg = thread_reg;
 312
 313         tte_vaddr = (unsigned long) KERNBASE;
 314         tte_data = kern_locked_tte_data;
 315
 316         for (i = 0; i < hdesc->num_mappings; i++) {
 317                 hdesc->maps[i].vaddr = tte_vaddr;
 318                 hdesc->maps[i].tte   = tte_data;
 319                 tte_vaddr += 0x400000;
 320                 tte_data  += 0x400000;
 321         }
 322
 323         trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
 324
 325         hv_err = sun4v_cpu_start(cpu, trampoline_ra,
 326                                  kimage_addr_to_ra(&sparc64_ttable_tl0),
 327                                  __pa(hdesc));
 328         if (hv_err)
 329                 printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
 330                        "gives error %lu\n", hv_err);
 331 }
 332 #endif
 333
 334 extern unsigned long sparc64_cpu_startup;
 335
 336 /* The OBP cpu startup callback truncates the 3rd arg cookie to
 337  * 32-bits (I think) so to be safe we have it read the pointer
 338  * contained here so we work on >4GB machines. -DaveM
 339  */
 340 static struct thread_info *cpu_new_thread = NULL;
 341
 342 static int __cpuinit smp_boot_one_cpu(unsigned int cpu)
 343 {
 344         unsigned long entry =
 345                 (unsigned long)(&sparc64_cpu_startup);
 346         unsigned long cookie =
 347                 (unsigned long)(&cpu_new_thread);
 348         struct task_struct *p;
 349         void *descr = NULL;
 350         int timeout, ret;
 351
 352         p = fork_idle(cpu);
 353         if (IS_ERR(p))
 354                 return PTR_ERR(p);
 355         callin_flag = 0;
 356         cpu_new_thread = task_thread_info(p);
 357
 358         if (tlb_type == hypervisor) {
 359 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
 360                 if (ldom_domaining_enabled)
 361                         ldom_startcpu_cpuid(cpu,
 362                                             (unsigned long) cpu_new_thread,
 363                                             &descr);
 364                 else
 365 #endif
 366                         prom_startcpu_cpuid(cpu, entry, cookie);
 367         } else {
 368                 struct device_node *dp = of_find_node_by_cpuid(cpu);
 369
 370                 prom_startcpu(dp->node, entry, cookie);
 371         }
 372
 373         for (timeout = 0; timeout < 50000; timeout++) {
 374                 if (callin_flag)
 375                         break;
 376                 udelay(100);
 377         }
 378
 379         if (callin_flag) {
 380                 ret = 0;
 381         } else {
 382                 printk("Processor %d is stuck.\n", cpu);
 383                 ret = -ENODEV;
 384         }
 385         cpu_new_thread = NULL;
 386
 387         kfree(descr);
 388
 389         return ret;
 390 }
 391
 392 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
 393 {
 394         u64 result, target;
 395         int stuck, tmp;
 396
 397         if (this_is_starfire) {
 398                 /* map to real upaid */
 399                 cpu = (((cpu & 0x3c) << 1) |
 400                         ((cpu & 0x40) >> 4) |
 401                         (cpu & 0x3));
 402         }
 403
 404         target = (cpu << 14) | 0x70;
 405 again:
 406         /* Ok, this is the real Spitfire Errata #54.
 407          * One must read back from a UDB internal register
 408          * after writes to the UDB interrupt dispatch, but
 409          * before the membar Sync for that write.
 410          * So we use the high UDB control register (ASI 0x7f,
 411          * ADDR 0x20) for the dummy read. -DaveM
 412          */
 413         tmp = 0x40;
 414         __asm__ __volatile__(
 415         "wrpr   %1, %2, %%pstate\n\t"
 416         "stxa   %4, [%0] %3\n\t"
 417         "stxa   %5, [%0+%8] %3\n\t"
 418         "add    %0, %8, %0\n\t"
 419         "stxa   %6, [%0+%8] %3\n\t"
 420         "membar #Sync\n\t"
 421         "stxa   %%g0, [%7] %3\n\t"
 422         "membar #Sync\n\t"
 423         "mov    0x20, %%g1\n\t"
 424         "ldxa   [%%g1] 0x7f, %%g0\n\t"
 425         "membar #Sync"
 426         : "=r" (tmp)
 427         : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
 428           "r" (data0), "r" (data1), "r" (data2), "r" (target),
 429           "r" (0x10), "0" (tmp)
 430         : "g1");
 431
 432         /* NOTE: PSTATE_IE is still clear. */
 433         stuck = 100000;
 434         do {
 435                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 436                         : "=r" (result)
 437                         : "i" (ASI_INTR_DISPATCH_STAT));
 438                 if (result == 0) {
 439                         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 440                                              : : "r" (pstate));
 441                         return;
 442                 }
 443                 stuck -= 1;
 444                 if (stuck == 0)
 445                         break;
 446         } while (result & 0x1);
 447         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 448                              : : "r" (pstate));
 449         if (stuck == 0) {
 450                 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
 451                        smp_processor_id(), result);
 452         } else {
 453                 udelay(2);
 454                 goto again;
 455         }
 456 }
 457
 458 static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 459 {
 460         u64 *mondo, data0, data1, data2;
 461         u16 *cpu_list;
 462         u64 pstate;
 463         int i;
 464
 465         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 466         cpu_list = __va(tb->cpu_list_pa);
 467         mondo = __va(tb->cpu_mondo_block_pa);
 468         data0 = mondo[0];
 469         data1 = mondo[1];
 470         data2 = mondo[2];
 471         for (i = 0; i < cnt; i++)
 472                 spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]);
 473 }
 474
 475 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
 476  * packet, but we have no use for that.  However we do take advantage of
 477  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
 478  */
 479 static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 480 {
 481         int nack_busy_id, is_jbus, need_more;
 482         u64 *mondo, pstate, ver, busy_mask;
 483         u16 *cpu_list;
 484
 485         cpu_list = __va(tb->cpu_list_pa);
 486         mondo = __va(tb->cpu_mondo_block_pa);
 487
 488         /* Unfortunately, someone at Sun had the brilliant idea to make the
 489          * busy/nack fields hard-coded by ITID number for this Ultra-III
 490          * derivative processor.
 491          */
 492         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 493         is_jbus = ((ver >> 32) == __JALAPENO_ID ||
 494                    (ver >> 32) == __SERRANO_ID);
 495
 496         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 497
 498 retry:
 499         need_more = 0;
 500         __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
 501                              : : "r" (pstate), "i" (PSTATE_IE));
 502
 503         /* Setup the dispatch data registers. */
 504         __asm__ __volatile__("stxa      %0, [%3] %6\n\t"
 505                              "stxa      %1, [%4] %6\n\t"
 506                              "stxa      %2, [%5] %6\n\t"
 507                              "membar    #Sync\n\t"
 508                              : /* no outputs */
 509                              : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]),
 510                                "r" (0x40), "r" (0x50), "r" (0x60),
 511                                "i" (ASI_INTR_W));
 512
 513         nack_busy_id = 0;
 514         busy_mask = 0;
 515         {
 516                 int i;
 517
 518                 for (i = 0; i < cnt; i++) {
 519                         u64 target, nr;
 520
 521                         nr = cpu_list[i];
 522                         if (nr == 0xffff)
 523                                 continue;
 524
 525                         target = (nr << 14) | 0x70;
 526                         if (is_jbus) {
 527                                 busy_mask |= (0x1UL << (nr * 2));
 528                         } else {
 529                                 target |= (nack_busy_id << 24);
 530                                 busy_mask |= (0x1UL <<
 531                                               (nack_busy_id * 2));
 532                         }
 533                         __asm__ __volatile__(
 534                                 "stxa   %%g0, [%0] %1\n\t"
 535                                 "membar #Sync\n\t"
 536                                 : /* no outputs */
 537                                 : "r" (target), "i" (ASI_INTR_W));
 538                         nack_busy_id++;
 539                         if (nack_busy_id == 32) {
 540                                 need_more = 1;
 541                                 break;
 542                         }
 543                 }
 544         }
 545
 546         /* Now, poll for completion. */
 547         {
 548                 u64 dispatch_stat, nack_mask;
 549                 long stuck;
 550
 551                 stuck = 100000 * nack_busy_id;
 552                 nack_mask = busy_mask << 1;
 553                 do {
 554                         __asm__ __volatile__("ldxa      [%%g0] %1, %0"
 555                                              : "=r" (dispatch_stat)
 556                                              : "i" (ASI_INTR_DISPATCH_STAT));
 557                         if (!(dispatch_stat & (busy_mask | nack_mask))) {
 558                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 559                                                      : : "r" (pstate));
 560                                 if (unlikely(need_more)) {
 561                                         int i, this_cnt = 0;
 562                                         for (i = 0; i < cnt; i++) {
 563                                                 if (cpu_list[i] == 0xffff)
 564                                                         continue;
 565                                                 cpu_list[i] = 0xffff;
 566                                                 this_cnt++;
 567                                                 if (this_cnt == 32)
 568                                                         break;
 569                                         }
 570                                         goto retry;
 571                                 }
 572                                 return;
 573                         }
 574                         if (!--stuck)
 575                                 break;
 576                 } while (dispatch_stat & busy_mask);
 577
 578                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 579                                      : : "r" (pstate));
 580
 581                 if (dispatch_stat & busy_mask) {
 582                         /* Busy bits will not clear, continue instead
 583                          * of freezing up on this cpu.
 584                          */
 585                         printk("CPU[%d]: mondo stuckage result[%016llx]\n",
 586                                smp_processor_id(), dispatch_stat);
 587                 } else {
 588                         int i, this_busy_nack = 0;
 589
 590                         /* Delay some random time with interrupts enabled
 591                          * to prevent deadlock.
 592                          */
 593                         udelay(2 * nack_busy_id);
 594
 595                         /* Clear out the mask bits for cpus which did not
 596                          * NACK us.
 597                          */
 598                         for (i = 0; i < cnt; i++) {
 599                                 u64 check_mask, nr;
 600
 601                                 nr = cpu_list[i];
 602                                 if (nr == 0xffff)
 603                                         continue;
 604
 605                                 if (is_jbus)
 606                                         check_mask = (0x2UL << (2*nr));
 607                                 else
 608                                         check_mask = (0x2UL <<
 609                                                       this_busy_nack);
 610                                 if ((dispatch_stat & check_mask) == 0)
 611                                         cpu_list[i] = 0xffff;
 612                                 this_busy_nack += 2;
 613                                 if (this_busy_nack == 64)
 614                                         break;
 615                         }
 616
 617                         goto retry;
 618                 }
 619         }
 620 }
 621
 622 /* Multi-cpu list version.  */
 623 static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt)
 624 {
 625         int retries, this_cpu, prev_sent, i, saw_cpu_error;
 626         unsigned long status;
 627         u16 *cpu_list;
 628
 629         this_cpu = smp_processor_id();
 630
 631         cpu_list = __va(tb->cpu_list_pa);
 632
 633         saw_cpu_error = 0;
 634         retries = 0;
 635         prev_sent = 0;
 636         do {
 637                 int forward_progress, n_sent;
 638
 639                 status = sun4v_cpu_mondo_send(cnt,
 640                                               tb->cpu_list_pa,
 641                                               tb->cpu_mondo_block_pa);
 642
 643                 /* HV_EOK means all cpus received the xcall, we're done.  */
 644                 if (likely(status == HV_EOK))
 645                         break;
 646
 647                 /* First, see if we made any forward progress.
 648                  *
 649                  * The hypervisor indicates successful sends by setting
 650                  * cpu list entries to the value 0xffff.
 651                  */
 652                 n_sent = 0;
 653                 for (i = 0; i < cnt; i++) {
 654                         if (likely(cpu_list[i] == 0xffff))
 655                                 n_sent++;
 656                 }
 657
 658                 forward_progress = 0;
 659                 if (n_sent > prev_sent)
 660                         forward_progress = 1;
 661
 662                 prev_sent = n_sent;
 663
 664                 /* If we get a HV_ECPUERROR, then one or more of the cpus
 665                  * in the list are in error state.  Use the cpu_state()
 666                  * hypervisor call to find out which cpus are in error state.
 667                  */
 668                 if (unlikely(status == HV_ECPUERROR)) {
 669                         for (i = 0; i < cnt; i++) {
 670                                 long err;
 671                                 u16 cpu;
 672
 673                                 cpu = cpu_list[i];
 674                                 if (cpu == 0xffff)
 675                                         continue;
 676
 677                                 err = sun4v_cpu_state(cpu);
 678                                 if (err == HV_CPU_STATE_ERROR) {
 679                                         saw_cpu_error = (cpu + 1);
 680                                         cpu_list[i] = 0xffff;
 681                                 }
 682                         }
 683                 } else if (unlikely(status != HV_EWOULDBLOCK))
 684                         goto fatal_mondo_error;
 685
 686                 /* Don't bother rewriting the CPU list, just leave the
 687                  * 0xffff and non-0xffff entries in there and the
 688                  * hypervisor will do the right thing.
 689                  *
 690                  * Only advance timeout state if we didn't make any
 691                  * forward progress.
 692                  */
 693                 if (unlikely(!forward_progress)) {
 694                         if (unlikely(++retries > 10000))
 695                                 goto fatal_mondo_timeout;
 696
 697                         /* Delay a little bit to let other cpus catch up
 698                          * on their cpu mondo queue work.
 699                          */
 700                         udelay(2 * cnt);
 701                 }
 702         } while (1);
 703
 704         if (unlikely(saw_cpu_error))
 705                 goto fatal_mondo_cpu_error;
 706
 707         return;
 708
 709 fatal_mondo_cpu_error:
 710         printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
 711                "(including %d) were in error state\n",
 712                this_cpu, saw_cpu_error - 1);
 713         return;
 714
 715 fatal_mondo_timeout:
 716         printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
 717                " progress after %d retries.\n",
 718                this_cpu, retries);
 719         goto dump_cpu_list_and_out;
 720
 721 fatal_mondo_error:
 722         printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
 723                this_cpu, status);
 724         printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
 725                "mondo_block_pa(%lx)\n",
 726                this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
 727
 728 dump_cpu_list_and_out:
 729         printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
 730         for (i = 0; i < cnt; i++)
 731                 printk("%u ", cpu_list[i]);
 732         printk("]\n");
 733 }
 734
 735 static void (*xcall_deliver_impl)(struct trap_per_cpu *, int);
 736
 737 static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
 738 {
 739         struct trap_per_cpu *tb;
 740         int this_cpu, i, cnt;
 741         unsigned long flags;
 742         u16 *cpu_list;
 743         u64 *mondo;
 744
 745         /* We have to do this whole thing with interrupts fully disabled.
 746          * Otherwise if we send an xcall from interrupt context it will
 747          * corrupt both our mondo block and cpu list state.
 748          *
 749          * One consequence of this is that we cannot use timeout mechanisms
 750          * that depend upon interrupts being delivered locally.  So, for
 751          * example, we cannot sample jiffies and expect it to advance.
 752          *
 753          * Fortunately, udelay() uses %stick/%tick so we can use that.
 754          */
 755         local_irq_save(flags);
 756
 757         this_cpu = smp_processor_id();
 758         tb = &trap_block[this_cpu];
 759
 760         mondo = __va(tb->cpu_mondo_block_pa);
 761         mondo[0] = data0;
 762         mondo[1] = data1;
 763         mondo[2] = data2;
 764         wmb();
 765
 766         cpu_list = __va(tb->cpu_list_pa);
 767
 768         /* Setup the initial cpu list.  */
 769         cnt = 0;
 770         for_each_cpu(i, mask) {
 771                 if (i == this_cpu || !cpu_online(i))
 772                         continue;
 773                 cpu_list[cnt++] = i;
 774         }
 775
 776         if (cnt)
 777                 xcall_deliver_impl(tb, cnt);
 778
 779         local_irq_restore(flags);
 780 }
 781
 782 /* Send cross call to all processors mentioned in MASK_P
 783  * except self.  Really, there are only two cases currently,
 784  * "&cpu_online_map" and "&mm->cpu_vm_mask".
 785  */
 786 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask)
 787 {
 788         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
 789
 790         xcall_deliver(data0, data1, data2, mask);
 791 }
 792
 793 /* Send cross call to all processors except self. */
 794 static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2)
 795 {
 796         smp_cross_call_masked(func, ctx, data1, data2, &cpu_online_map);
 797 }
 798
 799 extern unsigned long xcall_sync_tick;
 800
 801 static void smp_start_sync_tick_client(int cpu)
 802 {
 803         xcall_deliver((u64) &xcall_sync_tick, 0, 0,
 804                       &cpumask_of_cpu(cpu));
 805 }
 806
 807 extern unsigned long xcall_call_function;
 808
 809 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 810 {
 811         xcall_deliver((u64) &xcall_call_function, 0, 0, mask);
 812 }
 813
 814 extern unsigned long xcall_call_function_single;
 815
 816 void arch_send_call_function_single_ipi(int cpu)
 817 {
 818         xcall_deliver((u64) &xcall_call_function_single, 0, 0,
 819                       &cpumask_of_cpu(cpu));
 820 }
 821
 822 void smp_call_function_client(int irq, struct pt_regs *regs)
 823 {
 824         clear_softint(1 << irq);
 825         generic_smp_call_function_interrupt();
 826 }
 827
 828 void smp_call_function_single_client(int irq, struct pt_regs *regs)
 829 {
 830         clear_softint(1 << irq);
 831         generic_smp_call_function_single_interrupt();
 832 }
 833
 834 static void tsb_sync(void *info)
 835 {
 836         struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
 837         struct mm_struct *mm = info;
 838
 839         /* It is not valid to test "currrent->active_mm == mm" here.
 840          *
 841          * The value of "current" is not changed atomically with
 842          * switch_mm().  But that's OK, we just need to check the
 843          * current cpu's trap block PGD physical address.
 844          */
 845         if (tp->pgd_paddr == __pa(mm->pgd))
 846                 tsb_context_switch(mm);
 847 }
 848
 849 void smp_tsb_sync(struct mm_struct *mm)
 850 {
 851         smp_call_function_many(mm_cpumask(mm), tsb_sync, mm, 1);
 852 }
 853
 854 extern unsigned long xcall_flush_tlb_mm;
 855 extern unsigned long xcall_flush_tlb_pending;
 856 extern unsigned long xcall_flush_tlb_kernel_range;
 857 extern unsigned long xcall_fetch_glob_regs;
 858 extern unsigned long xcall_receive_signal;
 859 extern unsigned long xcall_new_mmu_context_version;
 860 #ifdef CONFIG_KGDB
 861 extern unsigned long xcall_kgdb_capture;
 862 #endif
 863
 864 #ifdef DCACHE_ALIASING_POSSIBLE
 865 extern unsigned long xcall_flush_dcache_page_cheetah;
 866 #endif
 867 extern unsigned long xcall_flush_dcache_page_spitfire;
 868
 869 #ifdef CONFIG_DEBUG_DCFLUSH
 870 extern atomic_t dcpage_flushes;
 871 extern atomic_t dcpage_flushes_xcall;
 872 #endif
 873
 874 static inline void __local_flush_dcache_page(struct page *page)
 875 {
 876 #ifdef DCACHE_ALIASING_POSSIBLE
 877         __flush_dcache_page(page_address(page),
 878                             ((tlb_type == spitfire) &&
 879                              page_mapping(page) != NULL));
 880 #else
 881         if (page_mapping(page) != NULL &&
 882             tlb_type == spitfire)
 883                 __flush_icache_page(__pa(page_address(page)));
 884 #endif
 885 }
 886
 887 void smp_flush_dcache_page_impl(struct page *page, int cpu)
 888 {
 889         int this_cpu;
 890
 891         if (tlb_type == hypervisor)
 892                 return;
 893
 894 #ifdef CONFIG_DEBUG_DCFLUSH
 895         atomic_inc(&dcpage_flushes);
 896 #endif
 897
 898         this_cpu = get_cpu();
 899
 900         if (cpu == this_cpu) {
 901                 __local_flush_dcache_page(page);
 902         } else if (cpu_online(cpu)) {
 903                 void *pg_addr = page_address(page);
 904                 u64 data0 = 0;
 905
 906                 if (tlb_type == spitfire) {
 907                         data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 908                         if (page_mapping(page) != NULL)
 909                                 data0 |= ((u64)1 << 32);
 910                 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 911 #ifdef DCACHE_ALIASING_POSSIBLE
 912                         data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 913 #endif
 914                 }
 915                 if (data0) {
 916                         xcall_deliver(data0, __pa(pg_addr),
 917                                       (u64) pg_addr, &cpumask_of_cpu(cpu));
 918 #ifdef CONFIG_DEBUG_DCFLUSH
 919                         atomic_inc(&dcpage_flushes_xcall);
 920 #endif
 921                 }
 922         }
 923
 924         put_cpu();
 925 }
 926
 927 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
 928 {
 929         void *pg_addr;
 930         int this_cpu;
 931         u64 data0;
 932
 933         if (tlb_type == hypervisor)
 934                 return;
 935
 936         this_cpu = get_cpu();
 937
 938 #ifdef CONFIG_DEBUG_DCFLUSH
 939         atomic_inc(&dcpage_flushes);
 940 #endif
 941         data0 = 0;
 942         pg_addr = page_address(page);
 943         if (tlb_type == spitfire) {
 944                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 945                 if (page_mapping(page) != NULL)
 946                         data0 |= ((u64)1 << 32);
 947         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 948 #ifdef DCACHE_ALIASING_POSSIBLE
 949                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 950 #endif
 951         }
 952         if (data0) {
 953                 xcall_deliver(data0, __pa(pg_addr),
 954                               (u64) pg_addr, &cpu_online_map);
 955 #ifdef CONFIG_DEBUG_DCFLUSH
 956                 atomic_inc(&dcpage_flushes_xcall);
 957 #endif
 958         }
 959         __local_flush_dcache_page(page);
 960
 961         put_cpu();
 962 }
 963
 964 void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
 965 {
 966         struct mm_struct *mm;
 967         unsigned long flags;
 968
 969         clear_softint(1 << irq);
 970
 971         /* See if we need to allocate a new TLB context because
 972          * the version of the one we are using is now out of date.
 973          */
 974         mm = current->active_mm;
 975         if (unlikely(!mm || (mm == &init_mm)))
 976                 return;
 977
 978         spin_lock_irqsave(&mm->context.lock, flags);
 979
 980         if (unlikely(!CTX_VALID(mm->context)))
 981                 get_new_mmu_context(mm);
 982
 983         spin_unlock_irqrestore(&mm->context.lock, flags);
 984
 985         load_secondary_context(mm);
 986         __flush_tlb_mm(CTX_HWBITS(mm->context),
 987                        SECONDARY_CONTEXT);
 988 }
 989
 990 void smp_new_mmu_context_version(void)
 991 {
 992         smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
 993 }
 994
 995 #ifdef CONFIG_KGDB
 996 void kgdb_roundup_cpus(unsigned long flags)
 997 {
 998         smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
 999 }
1000 #endif
1001
1002 void smp_fetch_global_regs(void)
1003 {
1004         smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
1005 }
1006
1007 /* We know that the window frames of the user have been flushed
1008  * to the stack before we get here because all callers of us
1009  * are flush_tlb_*() routines, and these run after flush_cache_*()
1010  * which performs the flushw.
1011  *
1012  * The SMP TLB coherency scheme we use works as follows:
1013  *
1014  * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1015  *    space has (potentially) executed on, this is the heuristic
1016  *    we use to avoid doing cross calls.
1017  *
1018  *    Also, for flushing from kswapd and also for clones, we
1019  *    use cpu_vm_mask as the list of cpus to make run the TLB.
1020  *
1021  * 2) TLB context numbers are shared globally across all processors
1022  *    in the system, this allows us to play several games to avoid
1023  *    cross calls.
1024  *
1025  *    One invariant is that when a cpu switches to a process, and
1026  *    that processes tsk->active_mm->cpu_vm_mask does not have the
1027  *    current cpu's bit set, that tlb context is flushed locally.
1028  *
1029  *    If the address space is non-shared (ie. mm->count == 1) we avoid
1030  *    cross calls when we want to flush the currently running process's
1031  *    tlb state.  This is done by clearing all cpu bits except the current
1032  *    processor's in current->mm->cpu_vm_mask and performing the
1033  *    flush locally only.  This will force any subsequent cpus which run
1034  *    this task to flush the context from the local tlb if the process
1035  *    migrates to another cpu (again).
1036  *
1037  * 3) For shared address spaces (threads) and swapping we bite the
1038  *    bullet for most cases and perform the cross call (but only to
1039  *    the cpus listed in cpu_vm_mask).
1040  *
1041  *    The performance gain from "optimizing" away the cross call for threads is
1042  *    questionable (in theory the big win for threads is the massive sharing of
1043  *    address space state across processors).
1044  */
1045
1046 /* This currently is only used by the hugetlb arch pre-fault
1047  * hook on UltraSPARC-III+ and later when changing the pagesize
1048  * bits of the context register for an address space.
1049  */
1050 void smp_flush_tlb_mm(struct mm_struct *mm)
1051 {
1052         u32 ctx = CTX_HWBITS(mm->context);
1053         int cpu = get_cpu();
1054
1055         if (atomic_read(&mm->mm_users) == 1) {
1056                 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1057                 goto local_flush_and_out;
1058         }
1059
1060         smp_cross_call_masked(&xcall_flush_tlb_mm,
1061                               ctx, 0, 0,
1062                               mm_cpumask(mm));
1063
1064 local_flush_and_out:
1065         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1066
1067         put_cpu();
1068 }
1069
1070 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1071 {
1072         u32 ctx = CTX_HWBITS(mm->context);
1073         int cpu = get_cpu();
1074
1075         if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
1076                 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1077         else
1078                 smp_cross_call_masked(&xcall_flush_tlb_pending,
1079                                       ctx, nr, (unsigned long) vaddrs,
1080                                       mm_cpumask(mm));
1081
1082         __flush_tlb_pending(ctx, nr, vaddrs);
1083
1084         put_cpu();
1085 }
1086
1087 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1088 {
1089         start &= PAGE_MASK;
1090         end    = PAGE_ALIGN(end);
1091         if (start != end) {
1092                 smp_cross_call(&xcall_flush_tlb_kernel_range,
1093                                0, start, end);
1094
1095                 __flush_tlb_kernel_range(start, end);
1096         }
1097 }
1098
1099 /* CPU capture. */
1100 /* #define CAPTURE_DEBUG */
1101 extern unsigned long xcall_capture;
1102
1103 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1104 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1105 static unsigned long penguins_are_doing_time;
1106
1107 void smp_capture(void)
1108 {
1109         int result = atomic_add_ret(1, &smp_capture_depth);
1110
1111         if (result == 1) {
1112                 int ncpus = num_online_cpus();
1113
1114 #ifdef CAPTURE_DEBUG
1115                 printk("CPU[%d]: Sending penguins to jail...",
1116                        smp_processor_id());
1117 #endif
1118                 penguins_are_doing_time = 1;
1119                 atomic_inc(&smp_capture_registry);
1120                 smp_cross_call(&xcall_capture, 0, 0, 0);
1121                 while (atomic_read(&smp_capture_registry) != ncpus)
1122                         rmb();
1123 #ifdef CAPTURE_DEBUG
1124                 printk("done\n");
1125 #endif
1126         }
1127 }
1128
1129 void smp_release(void)
1130 {
1131         if (atomic_dec_and_test(&smp_capture_depth)) {
1132 #ifdef CAPTURE_DEBUG
1133                 printk("CPU[%d]: Giving pardon to "
1134                        "imprisoned penguins\n",
1135                        smp_processor_id());
1136 #endif
1137                 penguins_are_doing_time = 0;
1138                 membar_safe("#StoreLoad");
1139                 atomic_dec(&smp_capture_registry);
1140         }
1141 }
1142
1143 /* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE
1144  * set, so they can service tlb flush xcalls...
1145  */
1146 extern void prom_world(int);
1147
1148 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1149 {
1150         clear_softint(1 << irq);
1151
1152         preempt_disable();
1153
1154         __asm__ __volatile__("flushw");
1155         prom_world(1);
1156         atomic_inc(&smp_capture_registry);
1157         membar_safe("#StoreLoad");
1158         while (penguins_are_doing_time)
1159                 rmb();
1160         atomic_dec(&smp_capture_registry);
1161         prom_world(0);
1162
1163         preempt_enable();
1164 }
1165
1166 /* /proc/profile writes can call this, don't __init it please. */
1167 int setup_profiling_timer(unsigned int multiplier)
1168 {
1169         return -EINVAL;
1170 }
1171
1172 void __init smp_prepare_cpus(unsigned int max_cpus)
1173 {
1174 }
1175
1176 void __devinit smp_prepare_boot_cpu(void)
1177 {
1178 }
1179
1180 void __init smp_setup_processor_id(void)
1181 {
1182         if (tlb_type == spitfire)
1183                 xcall_deliver_impl = spitfire_xcall_deliver;
1184         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
1185                 xcall_deliver_impl = cheetah_xcall_deliver;
1186         else
1187                 xcall_deliver_impl = hypervisor_xcall_deliver;
1188 }
1189
1190 void __devinit smp_fill_in_sib_core_maps(void)
1191 {
1192         unsigned int i;
1193
1194         for_each_present_cpu(i) {
1195                 unsigned int j;
1196
1197                 cpus_clear(cpu_core_map[i]);
1198                 if (cpu_data(i).core_id == 0) {
1199                         cpu_set(i, cpu_core_map[i]);
1200                         continue;
1201                 }
1202
1203                 for_each_present_cpu(j) {
1204                         if (cpu_data(i).core_id ==
1205                             cpu_data(j).core_id)
1206                                 cpu_set(j, cpu_core_map[i]);
1207                 }
1208         }
1209
1210         for_each_present_cpu(i) {
1211                 unsigned int j;
1212
1213                 cpus_clear(per_cpu(cpu_sibling_map, i));
1214                 if (cpu_data(i).proc_id == -1) {
1215                         cpu_set(i, per_cpu(cpu_sibling_map, i));
1216                         continue;
1217                 }
1218
1219                 for_each_present_cpu(j) {
1220                         if (cpu_data(i).proc_id ==
1221                             cpu_data(j).proc_id)
1222                                 cpu_set(j, per_cpu(cpu_sibling_map, i));
1223                 }
1224         }
1225 }
1226
1227 int __cpuinit __cpu_up(unsigned int cpu)
1228 {
1229         int ret = smp_boot_one_cpu(cpu);
1230
1231         if (!ret) {
1232                 cpu_set(cpu, smp_commenced_mask);
1233                 while (!cpu_isset(cpu, cpu_online_map))
1234                         mb();
1235                 if (!cpu_isset(cpu, cpu_online_map)) {
1236                         ret = -ENODEV;
1237                 } else {
1238                         /* On SUN4V, writes to %tick and %stick are
1239                          * not allowed.
1240                          */
1241                         if (tlb_type != hypervisor)
1242                                 smp_synchronize_one_tick(cpu);
1243                 }
1244         }
1245         return ret;
1246 }
1247
1248 #ifdef CONFIG_HOTPLUG_CPU
1249 void cpu_play_dead(void)
1250 {
1251         int cpu = smp_processor_id();
1252         unsigned long pstate;
1253
1254         idle_task_exit();
1255
1256         if (tlb_type == hypervisor) {
1257                 struct trap_per_cpu *tb = &trap_block[cpu];
1258
1259                 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
1260                                 tb->cpu_mondo_pa, 0);
1261                 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
1262                                 tb->dev_mondo_pa, 0);
1263                 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
1264                                 tb->resum_mondo_pa, 0);
1265                 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
1266                                 tb->nonresum_mondo_pa, 0);
1267         }
1268
1269         cpu_clear(cpu, smp_commenced_mask);
1270         membar_safe("#Sync");
1271
1272         local_irq_disable();
1273
1274         __asm__ __volatile__(
1275                 "rdpr   %%pstate, %0\n\t"
1276                 "wrpr   %0, %1, %%pstate"
1277                 : "=r" (pstate)
1278                 : "i" (PSTATE_IE));
1279
1280         while (1)
1281                 barrier();
1282 }
1283
1284 int __cpu_disable(void)
1285 {
1286         int cpu = smp_processor_id();
1287         cpuinfo_sparc *c;
1288         int i;
1289
1290         for_each_cpu_mask(i, cpu_core_map[cpu])
1291                 cpu_clear(cpu, cpu_core_map[i]);
1292         cpus_clear(cpu_core_map[cpu]);
1293
1294         for_each_cpu_mask(i, per_cpu(cpu_sibling_map, cpu))
1295                 cpu_clear(cpu, per_cpu(cpu_sibling_map, i));
1296         cpus_clear(per_cpu(cpu_sibling_map, cpu));
1297
1298         c = &cpu_data(cpu);
1299
1300         c->core_id = 0;
1301         c->proc_id = -1;
1302
1303         smp_wmb();
1304
1305         /* Make sure no interrupts point to this cpu.  */
1306         fixup_irqs();
1307
1308         local_irq_enable();
1309         mdelay(1);
1310         local_irq_disable();
1311
1312         ipi_call_lock();
1313         cpu_clear(cpu, cpu_online_map);
1314         ipi_call_unlock();
1315
1316         return 0;
1317 }
1318
1319 void __cpu_die(unsigned int cpu)
1320 {
1321         int i;
1322
1323         for (i = 0; i < 100; i++) {
1324                 smp_rmb();
1325                 if (!cpu_isset(cpu, smp_commenced_mask))
1326                         break;
1327                 msleep(100);
1328         }
1329         if (cpu_isset(cpu, smp_commenced_mask)) {
1330                 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1331         } else {
1332 #if defined(CONFIG_SUN_LDOMS)
1333                 unsigned long hv_err;
1334                 int limit = 100;
1335
1336                 do {
1337                         hv_err = sun4v_cpu_stop(cpu);
1338                         if (hv_err == HV_EOK) {
1339                                 cpu_clear(cpu, cpu_present_map);
1340                                 break;
1341                         }
1342                 } while (--limit > 0);
1343                 if (limit <= 0) {
1344                         printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
1345                                hv_err);
1346                 }
1347 #endif
1348         }
1349 }
1350 #endif
1351
1352 void __init smp_cpus_done(unsigned int max_cpus)
1353 {
1354 }
1355
1356 void smp_send_reschedule(int cpu)
1357 {
1358         xcall_deliver((u64) &xcall_receive_signal, 0, 0,
1359                       &cpumask_of_cpu(cpu));
1360 }
1361
1362 void smp_receive_signal_client(int irq, struct pt_regs *regs)
1363 {
1364         clear_softint(1 << irq);
1365 }
1366
1367 /* This is a nop because we capture all other cpus
1368  * anyways when making the PROM active.
1369  */
1370 void smp_send_stop(void)
1371 {
1372 }
1373
1374 void __init real_setup_per_cpu_areas(void)
1375 {
1376         unsigned long base, shift, paddr, goal, size, i;
1377         char *ptr;
1378
1379         /* Copy section for each CPU (we discard the original) */
1380         goal = PERCPU_ENOUGH_ROOM;
1381
1382         shift = PAGE_SHIFT;
1383         for (size = PAGE_SIZE; size < goal; size <<= 1UL)
1384                 shift++;
1385
1386         paddr = lmb_alloc(size * NR_CPUS, PAGE_SIZE);
1387         if (!paddr) {
1388                 prom_printf("Cannot allocate per-cpu memory.\n");
1389                 prom_halt();
1390         }
1391
1392         ptr = __va(paddr);
1393         base = ptr - __per_cpu_start;
1394
1395         for (i = 0; i < NR_CPUS; i++, ptr += size) {
1396                 __per_cpu_offset(i) = base + (i * size);
1397                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1398         }
1399
1400         /* Setup %g5 for the boot cpu.  */
1401         __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
1402
1403         of_fill_in_cpu_data();
1404         if (tlb_type == hypervisor)
1405                 mdesc_fill_in_cpu_data(CPU_MASK_ALL_PTR);
1406 }