1 /* cache.h: Cache specific code for the Sparc. These include flushing
2 * and direct tag/data line access.
4 * Copyright (C) 1995, 2007 David S. Miller (davem@davemloft.net)
10 #define ARCH_SLAB_MINALIGN __alignof__(unsigned long long)
12 #define L1_CACHE_SHIFT 5
13 #define L1_CACHE_BYTES 32
14 #define L1_CACHE_ALIGN(x) ((((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)))
17 #define SMP_CACHE_BYTES_SHIFT 5
19 #define SMP_CACHE_BYTES_SHIFT 6
22 #define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT)
24 #define __read_mostly __attribute__((__section__(".data..read_mostly")))
29 /* Direct access to the instruction cache is provided through and
30 * alternate address space. The IDC bit must be off in the ICCR on
31 * HyperSparcs for these accesses to work. The code below does not do
32 * any checking, the caller must do so. These routines are for
33 * diagnostics only, but could end up being useful. Use with care.
34 * Also, you are asking for trouble if you execute these in one of the
35 * three instructions following a %asr/%psr access or modification.
38 /* First, cache-tag access. */
39 static inline unsigned int get_icache_tag(int setnum, int tagnum)
41 unsigned int vaddr, retval;
43 vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
44 __asm__ __volatile__("lda [%1] %2, %0\n\t" :
46 "r" (vaddr), "i" (ASI_M_TXTC_TAG));
50 static inline void put_icache_tag(int setnum, int tagnum, unsigned int entry)
54 vaddr = ((setnum&1) << 12) | ((tagnum&0x7f) << 5);
55 __asm__ __volatile__("sta %0, [%1] %2\n\t" : :
56 "r" (entry), "r" (vaddr), "i" (ASI_M_TXTC_TAG) :
60 /* Second cache-data access. The data is returned two-32bit quantities
63 static inline void get_icache_data(int setnum, int tagnum, int subblock,
66 unsigned int value1, value2, vaddr;
68 vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
69 ((subblock&0x3) << 3);
70 __asm__ __volatile__("ldda [%2] %3, %%g2\n\t"
71 "or %%g0, %%g2, %0\n\t"
72 "or %%g0, %%g3, %1\n\t" :
73 "=r" (value1), "=r" (value2) :
74 "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
76 data[0] = value1; data[1] = value2;
79 static inline void put_icache_data(int setnum, int tagnum, int subblock,
82 unsigned int value1, value2, vaddr;
84 vaddr = ((setnum&0x1) << 12) | ((tagnum&0x7f) << 5) |
85 ((subblock&0x3) << 3);
86 value1 = data[0]; value2 = data[1];
87 __asm__ __volatile__("or %%g0, %0, %%g2\n\t"
88 "or %%g0, %1, %%g3\n\t"
89 "stda %%g2, [%2] %3\n\t" : :
90 "r" (value1), "r" (value2),
91 "r" (vaddr), "i" (ASI_M_TXTC_DATA) :
92 "g2", "g3", "memory" /* no joke */);
95 /* Different types of flushes with the ICACHE. Some of the flushes
96 * affect both the ICACHE and the external cache. Others only clear
97 * the ICACHE entries on the cpu itself. V8's (most) allow
98 * granularity of flushes on the packet (element in line), whole line,
99 * and entire cache (ie. all lines) level. The ICACHE only flushes are
100 * ROSS HyperSparc specific and are in ross.h
103 /* Flushes which clear out both the on-chip and external caches */
104 static inline void flush_ei_page(unsigned int addr)
106 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
107 "r" (addr), "i" (ASI_M_FLUSH_PAGE) :
111 static inline void flush_ei_seg(unsigned int addr)
113 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
114 "r" (addr), "i" (ASI_M_FLUSH_SEG) :
118 static inline void flush_ei_region(unsigned int addr)
120 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
121 "r" (addr), "i" (ASI_M_FLUSH_REGION) :
125 static inline void flush_ei_ctx(unsigned int addr)
127 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
128 "r" (addr), "i" (ASI_M_FLUSH_CTX) :
132 static inline void flush_ei_user(unsigned int addr)
134 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
135 "r" (addr), "i" (ASI_M_FLUSH_USER) :
138 #endif /* CONFIG_SPARC32 */
140 #endif /* !(_SPARC_CACHE_H) */