4 * TLB entry wiring helpers for URB-equipped parts.
6 * Copyright (C) 2010 Matt Fleming
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
15 #include <asm/mmu_context.h>
18 * Load the entry for 'addr' into the TLB and wire the entry.
20 void tlb_wire_entry(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
22 unsigned long status, flags;
25 local_irq_save(flags);
27 /* Load the entry into the TLB */
28 __update_tlb(vma, addr, pte);
30 /* ... and wire it up. */
31 status = __raw_readl(MMUCR);
32 urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
36 * Make sure we're not trying to wire the last TLB entry slot.
40 urb = urb % MMUCR_URB_NENTRIES;
42 status |= (urb << MMUCR_URB_SHIFT);
43 __raw_writel(status, MMUCR);
46 local_irq_restore(flags);
50 * Unwire the last wired TLB entry.
52 * It should also be noted that it is not possible to wire and unwire
53 * TLB entries in an arbitrary order. If you wire TLB entry N, followed
54 * by entry N+1, you must unwire entry N+1 first, then entry N. In this
55 * respect, it works like a stack or LIFO queue.
57 void tlb_unwire_entry(void)
59 unsigned long status, flags;
62 local_irq_save(flags);
64 status = __raw_readl(MMUCR);
65 urb = (status & MMUCR_URB) >> MMUCR_URB_SHIFT;
69 * Make sure we're not trying to unwire a TLB entry when none
72 BUG_ON(urb++ == MMUCR_URB_NENTRIES);
74 urb = urb % MMUCR_URB_NENTRIES;
76 status |= (urb << MMUCR_URB_SHIFT);
77 __raw_writel(status, MMUCR);
80 local_irq_restore(flags);