5 select SH_WRITETHROUGH if !CPU_SH2A
21 select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
31 config CPU_SUBTYPE_ST40
34 select CPU_HAS_INTC2_IRQ
40 prompt "Processor sub-type selection"
46 # SH-2 Processor Support
48 config CPU_SUBTYPE_SH7604
49 bool "Support SH7604 processor"
52 config CPU_SUBTYPE_SH7619
53 bool "Support SH7619 processor"
56 # SH-2A Processor Support
58 config CPU_SUBTYPE_SH7206
59 bool "Support SH7206 processor"
61 select CPU_HAS_IPR_IRQ
63 # SH-3 Processor Support
65 config CPU_SUBTYPE_SH7300
66 bool "Support SH7300 processor"
69 config CPU_SUBTYPE_SH7705
70 bool "Support SH7705 processor"
72 select CPU_HAS_IPR_IRQ
73 select CPU_HAS_PINT_IRQ
75 config CPU_SUBTYPE_SH7706
76 bool "Support SH7706 processor"
78 select CPU_HAS_IPR_IRQ
80 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
82 config CPU_SUBTYPE_SH7707
83 bool "Support SH7707 processor"
85 select CPU_HAS_PINT_IRQ
87 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
89 config CPU_SUBTYPE_SH7708
90 bool "Support SH7708 processor"
93 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
94 if you have a 100 Mhz SH-3 HD6417708R CPU.
96 config CPU_SUBTYPE_SH7709
97 bool "Support SH7709 processor"
99 select CPU_HAS_IPR_IRQ
100 select CPU_HAS_PINT_IRQ
102 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
104 config CPU_SUBTYPE_SH7710
105 bool "Support SH7710 processor"
107 select CPU_HAS_IPR_IRQ
109 Select SH7710 if you have a SH3-DSP SH7710 CPU.
111 config CPU_SUBTYPE_SH7712
112 bool "Support SH7712 processor"
114 select CPU_HAS_IPR_IRQ
116 Select SH7712 if you have a SH3-DSP SH7712 CPU.
118 # SH-4 Processor Support
120 config CPU_SUBTYPE_SH7750
121 bool "Support SH7750 processor"
123 select CPU_HAS_IPR_IRQ
125 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
127 config CPU_SUBTYPE_SH7091
128 bool "Support SH7091 processor"
131 Select SH7091 if you have an SH-4 based Sega device (such as
132 the Dreamcast, Naomi, and Naomi 2).
134 config CPU_SUBTYPE_SH7750R
135 bool "Support SH7750R processor"
137 select CPU_HAS_IPR_IRQ
139 config CPU_SUBTYPE_SH7750S
140 bool "Support SH7750S processor"
142 select CPU_HAS_IPR_IRQ
144 config CPU_SUBTYPE_SH7751
145 bool "Support SH7751 processor"
147 select CPU_HAS_IPR_IRQ
149 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
150 or if you have a HD6417751R CPU.
152 config CPU_SUBTYPE_SH7751R
153 bool "Support SH7751R processor"
155 select CPU_HAS_IPR_IRQ
157 config CPU_SUBTYPE_SH7760
158 bool "Support SH7760 processor"
160 select CPU_HAS_INTC2_IRQ
161 select CPU_HAS_IPR_IRQ
163 config CPU_SUBTYPE_SH4_202
164 bool "Support SH4-202 processor"
167 # ST40 Processor Support
169 config CPU_SUBTYPE_ST40STB1
170 bool "Support ST40STB1/ST40RA processors"
171 select CPU_SUBTYPE_ST40
173 Select ST40STB1 if you have a ST40RA CPU.
174 This was previously called the ST40STB1, hence the option name.
176 config CPU_SUBTYPE_ST40GX1
177 bool "Support ST40GX1 processor"
178 select CPU_SUBTYPE_ST40
180 Select ST40GX1 if you have a ST40GX1 CPU.
182 # SH-4A Processor Support
184 config CPU_SUBTYPE_SH7770
185 bool "Support SH7770 processor"
188 config CPU_SUBTYPE_SH7780
189 bool "Support SH7780 processor"
191 select CPU_HAS_INTC2_IRQ
193 config CPU_SUBTYPE_SH7785
194 bool "Support SH7785 processor"
197 select CPU_HAS_INTC2_IRQ
199 # SH4AL-DSP Processor Support
201 config CPU_SUBTYPE_SH73180
202 bool "Support SH73180 processor"
205 config CPU_SUBTYPE_SH7343
206 bool "Support SH7343 processor"
209 config CPU_SUBTYPE_SH7722
210 bool "Support SH7722 processor"
213 select CPU_HAS_IPR_IRQ
217 menu "Memory management options"
223 bool "Support for memory management hardware"
227 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
228 boot on these systems, this option must not be set.
230 On other systems (such as the SH-3 and 4) where an MMU exists,
231 turning this off will boot the kernel on these machines with the
232 MMU implicitly switched off.
236 default "0x80000000" if MMU
240 hex "Physical memory start address"
243 Computers built with Hitachi SuperH processors always
244 map the ROM starting at address zero. But the processor
245 does not specify the range that RAM takes.
247 The physical memory (RAM) start address will be automatically
248 set to 08000000. Other platforms, such as the Solution Engine
249 boards typically map RAM at 0C000000.
251 Tweak this only when porting to a new machine which does not
252 already have a defconfig. Changing it from the known correct
253 value on any of the known systems will only lead to disaster.
256 hex "Physical memory size"
259 This sets the default memory size assumed by your SH kernel. It can
260 be overridden as normal by the 'mem=' argument on the kernel command
261 line. If unsure, consult your board specifications or just leave it
262 as 0x00400000 which was the default value before this became
266 bool "Support 32-bit physical addressing through PMB"
267 depends on CPU_SH4A && MMU && (!X2TLB || BROKEN)
270 If you say Y here, physical addressing will be extended to
271 32-bits through the SH-4A PMB. If this is not set, legacy
272 29-bit physical addressing will be used.
275 bool "Enable extended TLB mode"
276 depends on CPU_SHX2 && MMU && EXPERIMENTAL
278 Selecting this option will enable the extended mode of the SH-X2
279 TLB. For legacy SH-X behaviour and interoperability, say N. For
280 all of the fun new features and a willingless to submit bug reports,
284 bool "Support vsyscall page"
288 This will enable support for the kernel mapping a vDSO page
289 in process space, and subsequently handing down the entry point
290 to the libc through the ELF auxiliary vector.
292 From the kernel side this is used for the signal trampoline.
293 For systems with an MMU that can afford to give up a page,
294 (the default value) say Y.
299 depends on NEED_MULTIPLE_NODES
301 config ARCH_FLATMEM_ENABLE
304 config ARCH_SPARSEMEM_ENABLE
306 select SPARSEMEM_STATIC
308 config ARCH_SPARSEMEM_DEFAULT
311 config MAX_ACTIVE_REGIONS
315 config ARCH_POPULATES_NODE_MAP
318 config ARCH_SELECT_MEMORY_MODEL
322 prompt "Kernel page size"
323 default PAGE_SIZE_4KB
328 This is the default page size used by all SuperH CPUs.
332 depends on EXPERIMENTAL && X2TLB
334 This enables 8kB pages as supported by SH-X2 and later MMUs.
336 config PAGE_SIZE_64KB
338 depends on EXPERIMENTAL && CPU_SH4
340 This enables support for 64kB pages, possible on all SH-4
341 CPUs and later. Highly experimental, not recommended.
346 prompt "HugeTLB page size"
347 depends on HUGETLB_PAGE && CPU_SH4 && MMU
348 default HUGETLB_PAGE_SIZE_64K
350 config HUGETLB_PAGE_SIZE_64K
353 config HUGETLB_PAGE_SIZE_256K
357 config HUGETLB_PAGE_SIZE_1MB
360 config HUGETLB_PAGE_SIZE_4MB
364 config HUGETLB_PAGE_SIZE_64MB
374 menu "Cache configuration"
376 config SH7705_CACHE_32KB
377 bool "Enable 32KB cache size for SH7705"
378 depends on CPU_SUBTYPE_SH7705
381 config SH_DIRECT_MAPPED
382 bool "Use direct-mapped caching"
385 Selecting this option will configure the caches to be direct-mapped,
386 even if the cache supports a 2 or 4-way mode. This is useful primarily
387 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
388 SH4-202, SH4-501, etc.)
390 Turn this option off for platforms that do not have a direct-mapped
391 cache, and you have no need to run the caches in such a configuration.
393 config SH_WRITETHROUGH
394 bool "Use write-through caching"
396 Selecting this option will configure the caches in write-through
397 mode, as opposed to the default write-back configuration.
399 Since there's sill some aliasing issues on SH-4, this option will
400 unfortunately still require the majority of flushing functions to
401 be implemented to deal with aliasing.
406 bool "Operand Cache RAM (OCRAM) support"
408 Selecting this option will automatically tear down the number of
409 sets in the dcache by half, which in turn exposes a memory range.
411 The addresses for the OC RAM base will vary according to the
412 processor version. Consult vendor documentation for specifics.