5 select SH_WRITETHROUGH if !CPU_SH2A
21 select CPU_HAS_PTEA if (!CPU_SUBTYPE_ST40 && !CPU_SH4A) || CPU_SHX2
31 config CPU_SUBTYPE_ST40
34 select CPU_HAS_INTC2_IRQ
40 prompt "Processor sub-type selection"
46 # SH-2 Processor Support
48 config CPU_SUBTYPE_SH7604
49 bool "Support SH7604 processor"
52 config CPU_SUBTYPE_SH7619
53 bool "Support SH7619 processor"
56 # SH-2A Processor Support
58 config CPU_SUBTYPE_SH7206
59 bool "Support SH7206 processor"
62 # SH-3 Processor Support
64 config CPU_SUBTYPE_SH7300
65 bool "Support SH7300 processor"
68 config CPU_SUBTYPE_SH7705
69 bool "Support SH7705 processor"
71 select CPU_HAS_IPR_IRQ
72 select CPU_HAS_PINT_IRQ
74 config CPU_SUBTYPE_SH7706
75 bool "Support SH7706 processor"
77 select CPU_HAS_IPR_IRQ
79 Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
81 config CPU_SUBTYPE_SH7707
82 bool "Support SH7707 processor"
84 select CPU_HAS_PINT_IRQ
86 Select SH7707 if you have a 60 Mhz SH-3 HD6417707 CPU.
88 config CPU_SUBTYPE_SH7708
89 bool "Support SH7708 processor"
92 Select SH7708 if you have a 60 Mhz SH-3 HD6417708S or
93 if you have a 100 Mhz SH-3 HD6417708R CPU.
95 config CPU_SUBTYPE_SH7709
96 bool "Support SH7709 processor"
98 select CPU_HAS_IPR_IRQ
99 select CPU_HAS_PINT_IRQ
101 Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
103 config CPU_SUBTYPE_SH7710
104 bool "Support SH7710 processor"
106 select CPU_HAS_IPR_IRQ
108 Select SH7710 if you have a SH3-DSP SH7710 CPU.
110 config CPU_SUBTYPE_SH7712
111 bool "Support SH7712 processor"
113 select CPU_HAS_IPR_IRQ
115 Select SH7712 if you have a SH3-DSP SH7712 CPU.
117 # SH-4 Processor Support
119 config CPU_SUBTYPE_SH7750
120 bool "Support SH7750 processor"
122 select CPU_HAS_IPR_IRQ
124 Select SH7750 if you have a 200 Mhz SH-4 HD6417750 CPU.
126 config CPU_SUBTYPE_SH7091
127 bool "Support SH7091 processor"
130 Select SH7091 if you have an SH-4 based Sega device (such as
131 the Dreamcast, Naomi, and Naomi 2).
133 config CPU_SUBTYPE_SH7750R
134 bool "Support SH7750R processor"
136 select CPU_HAS_IPR_IRQ
138 config CPU_SUBTYPE_SH7750S
139 bool "Support SH7750S processor"
141 select CPU_HAS_IPR_IRQ
143 config CPU_SUBTYPE_SH7751
144 bool "Support SH7751 processor"
146 select CPU_HAS_IPR_IRQ
148 Select SH7751 if you have a 166 Mhz SH-4 HD6417751 CPU,
149 or if you have a HD6417751R CPU.
151 config CPU_SUBTYPE_SH7751R
152 bool "Support SH7751R processor"
154 select CPU_HAS_IPR_IRQ
156 config CPU_SUBTYPE_SH7760
157 bool "Support SH7760 processor"
159 select CPU_HAS_INTC2_IRQ
160 select CPU_HAS_IPR_IRQ
162 config CPU_SUBTYPE_SH4_202
163 bool "Support SH4-202 processor"
166 # ST40 Processor Support
168 config CPU_SUBTYPE_ST40STB1
169 bool "Support ST40STB1/ST40RA processors"
170 select CPU_SUBTYPE_ST40
172 Select ST40STB1 if you have a ST40RA CPU.
173 This was previously called the ST40STB1, hence the option name.
175 config CPU_SUBTYPE_ST40GX1
176 bool "Support ST40GX1 processor"
177 select CPU_SUBTYPE_ST40
179 Select ST40GX1 if you have a ST40GX1 CPU.
181 # SH-4A Processor Support
183 config CPU_SUBTYPE_SH7770
184 bool "Support SH7770 processor"
187 config CPU_SUBTYPE_SH7780
188 bool "Support SH7780 processor"
190 select CPU_HAS_INTC2_IRQ
192 config CPU_SUBTYPE_SH7785
193 bool "Support SH7785 processor"
196 select CPU_HAS_INTC2_IRQ
198 # SH4AL-DSP Processor Support
200 config CPU_SUBTYPE_SH73180
201 bool "Support SH73180 processor"
204 config CPU_SUBTYPE_SH7343
205 bool "Support SH7343 processor"
208 config CPU_SUBTYPE_SH7722
209 bool "Support SH7722 processor"
212 select CPU_HAS_IPR_IRQ
216 menu "Memory management options"
222 bool "Support for memory management hardware"
226 Some SH processors (such as SH-2/SH-2A) lack an MMU. In order to
227 boot on these systems, this option must not be set.
229 On other systems (such as the SH-3 and 4) where an MMU exists,
230 turning this off will boot the kernel on these machines with the
231 MMU implicitly switched off.
235 default "0x80000000" if MMU
239 hex "Physical memory start address"
242 Computers built with Hitachi SuperH processors always
243 map the ROM starting at address zero. But the processor
244 does not specify the range that RAM takes.
246 The physical memory (RAM) start address will be automatically
247 set to 08000000. Other platforms, such as the Solution Engine
248 boards typically map RAM at 0C000000.
250 Tweak this only when porting to a new machine which does not
251 already have a defconfig. Changing it from the known correct
252 value on any of the known systems will only lead to disaster.
255 hex "Physical memory size"
258 This sets the default memory size assumed by your SH kernel. It can
259 be overridden as normal by the 'mem=' argument on the kernel command
260 line. If unsure, consult your board specifications or just leave it
261 as 0x00400000 which was the default value before this became
265 bool "Support 32-bit physical addressing through PMB"
266 depends on CPU_SH4A && MMU && (!X2TLB || BROKEN)
269 If you say Y here, physical addressing will be extended to
270 32-bits through the SH-4A PMB. If this is not set, legacy
271 29-bit physical addressing will be used.
274 bool "Enable extended TLB mode"
275 depends on CPU_SHX2 && MMU && EXPERIMENTAL
277 Selecting this option will enable the extended mode of the SH-X2
278 TLB. For legacy SH-X behaviour and interoperability, say N. For
279 all of the fun new features and a willingless to submit bug reports,
283 bool "Support vsyscall page"
287 This will enable support for the kernel mapping a vDSO page
288 in process space, and subsequently handing down the entry point
289 to the libc through the ELF auxiliary vector.
291 From the kernel side this is used for the signal trampoline.
292 For systems with an MMU that can afford to give up a page,
293 (the default value) say Y.
298 depends on NEED_MULTIPLE_NODES
300 config ARCH_FLATMEM_ENABLE
303 config MAX_ACTIVE_REGIONS
307 config ARCH_POPULATES_NODE_MAP
311 prompt "Kernel page size"
312 default PAGE_SIZE_4KB
317 This is the default page size used by all SuperH CPUs.
321 depends on EXPERIMENTAL && X2TLB
323 This enables 8kB pages as supported by SH-X2 and later MMUs.
325 config PAGE_SIZE_64KB
327 depends on EXPERIMENTAL && CPU_SH4
329 This enables support for 64kB pages, possible on all SH-4
330 CPUs and later. Highly experimental, not recommended.
335 prompt "HugeTLB page size"
336 depends on HUGETLB_PAGE && CPU_SH4 && MMU
337 default HUGETLB_PAGE_SIZE_64K
339 config HUGETLB_PAGE_SIZE_64K
342 config HUGETLB_PAGE_SIZE_256K
346 config HUGETLB_PAGE_SIZE_1MB
349 config HUGETLB_PAGE_SIZE_4MB
353 config HUGETLB_PAGE_SIZE_64MB
363 menu "Cache configuration"
365 config SH7705_CACHE_32KB
366 bool "Enable 32KB cache size for SH7705"
367 depends on CPU_SUBTYPE_SH7705
370 config SH_DIRECT_MAPPED
371 bool "Use direct-mapped caching"
374 Selecting this option will configure the caches to be direct-mapped,
375 even if the cache supports a 2 or 4-way mode. This is useful primarily
376 for debugging on platforms with 2 and 4-way caches (SH7750R/SH7751R,
377 SH4-202, SH4-501, etc.)
379 Turn this option off for platforms that do not have a direct-mapped
380 cache, and you have no need to run the caches in such a configuration.
382 config SH_WRITETHROUGH
383 bool "Use write-through caching"
385 Selecting this option will configure the caches in write-through
386 mode, as opposed to the default write-back configuration.
388 Since there's sill some aliasing issues on SH-4, this option will
389 unfortunately still require the majority of flushing functions to
390 be implemented to deal with aliasing.
395 bool "Operand Cache RAM (OCRAM) support"
397 Selecting this option will automatically tear down the number of
398 sets in the dcache by half, which in turn exposes a memory range.
400 The addresses for the OC RAM base will vary according to the
401 processor version. Consult vendor documentation for specifics.