2 * 'traps.c' handles hardware traps and faults after we have saved some
5 * SuperH version: Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf
7 * Copyright (C) 2000 David Howells
8 * Copyright (C) 2002 - 2007 Paul Mundt
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
14 #include <linux/kernel.h>
15 #include <linux/ptrace.h>
16 #include <linux/hardirq.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/module.h>
20 #include <linux/kallsyms.h>
22 #include <linux/bug.h>
23 #include <linux/debug_locks.h>
24 #include <linux/kdebug.h>
25 #include <linux/kexec.h>
26 #include <linux/limits.h>
27 #include <asm/system.h>
28 #include <asm/uaccess.h>
30 #include <asm/kprobes.h>
33 # define TRAP_RESERVED_INST 4
34 # define TRAP_ILLEGAL_SLOT_INST 6
35 # define TRAP_ADDRESS_ERROR 9
36 # ifdef CONFIG_CPU_SH2A
38 # define TRAP_FPU_ERROR 13
39 # define TRAP_DIVZERO_ERROR 17
40 # define TRAP_DIVOVF_ERROR 18
43 #define TRAP_RESERVED_INST 12
44 #define TRAP_ILLEGAL_SLOT_INST 13
47 static void dump_mem(const char *str, unsigned long bottom, unsigned long top)
52 printk("%s(0x%08lx to 0x%08lx)\n", str, bottom, top);
54 for (p = bottom & ~31; p < top; ) {
55 printk("%04lx: ", p & 0xffff);
57 for (i = 0; i < 8; i++, p += 4) {
60 if (p < bottom || p >= top)
63 if (__get_user(val, (unsigned int __user *)p)) {
74 static DEFINE_SPINLOCK(die_lock);
76 void die(const char * str, struct pt_regs * regs, long err)
78 static int die_counter;
83 spin_lock_irq(&die_lock);
86 printk("%s: %04lx [#%d]\n", str, err & 0xffff, ++die_counter);
91 printk("Process: %s (pid: %d, stack limit = %p)\n", current->comm,
92 task_pid_nr(current), task_stack_page(current) + 1);
94 if (!user_mode(regs) || in_interrupt())
95 dump_mem("Stack: ", regs->regs[15], THREAD_SIZE +
96 (unsigned long)task_stack_page(current));
98 notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV);
101 add_taint(TAINT_DIE);
102 spin_unlock_irq(&die_lock);
104 if (kexec_should_crash(current))
108 panic("Fatal exception in interrupt");
111 panic("Fatal exception");
117 static inline void die_if_kernel(const char *str, struct pt_regs *regs,
120 if (!user_mode(regs))
125 * try and fix up kernelspace address errors
126 * - userspace errors just cause EFAULT to be returned, resulting in SEGV
127 * - kernel/userspace interfaces cause a jump to an appropriate handler
128 * - other kernel errors are bad
130 static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
132 if (!user_mode(regs)) {
133 const struct exception_table_entry *fixup;
134 fixup = search_exception_tables(regs->pc);
136 regs->pc = fixup->fixup;
144 static inline void sign_extend(unsigned int count, unsigned char *dst)
146 #ifdef __LITTLE_ENDIAN__
147 if ((count == 1) && dst[0] & 0x80) {
152 if ((count == 2) && dst[1] & 0x80) {
157 if ((count == 1) && dst[3] & 0x80) {
162 if ((count == 2) && dst[2] & 0x80) {
169 static struct mem_access user_mem_access = {
175 * handle an instruction that does an unaligned memory access by emulating the
177 * - note that PC _may not_ point to the faulting instruction
178 * (if that instruction is in a branch delay slot)
179 * - return 0 if emulation okay, -EFAULT on existential error
181 static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs,
182 struct mem_access *ma)
184 int ret, index, count;
185 unsigned long *rm, *rn;
186 unsigned char *src, *dst;
187 unsigned char __user *srcu, *dstu;
189 index = (instruction>>8)&15; /* 0x0F00 */
190 rn = ®s->regs[index];
192 index = (instruction>>4)&15; /* 0x00F0 */
193 rm = ®s->regs[index];
195 count = 1<<(instruction&3);
198 switch (instruction>>12) {
199 case 0: /* mov.[bwl] to/from memory via r0+rn */
200 if (instruction & 8) {
202 srcu = (unsigned char __user *)*rm;
203 srcu += regs->regs[0];
204 dst = (unsigned char *)rn;
205 *(unsigned long *)dst = 0;
207 #if !defined(__LITTLE_ENDIAN__)
210 if (ma->from(dst, srcu, count))
213 sign_extend(count, dst);
216 src = (unsigned char *)rm;
217 #if !defined(__LITTLE_ENDIAN__)
220 dstu = (unsigned char __user *)*rn;
221 dstu += regs->regs[0];
223 if (ma->to(dstu, src, count))
229 case 1: /* mov.l Rm,@(disp,Rn) */
230 src = (unsigned char*) rm;
231 dstu = (unsigned char __user *)*rn;
232 dstu += (instruction&0x000F)<<2;
234 if (ma->to(dstu, src, 4))
239 case 2: /* mov.[bwl] to memory, possibly with pre-decrement */
242 src = (unsigned char*) rm;
243 dstu = (unsigned char __user *)*rn;
244 #if !defined(__LITTLE_ENDIAN__)
247 if (ma->to(dstu, src, count))
252 case 5: /* mov.l @(disp,Rm),Rn */
253 srcu = (unsigned char __user *)*rm;
254 srcu += (instruction & 0x000F) << 2;
255 dst = (unsigned char *)rn;
256 *(unsigned long *)dst = 0;
258 if (ma->from(dst, srcu, 4))
263 case 6: /* mov.[bwl] from memory, possibly with post-increment */
264 srcu = (unsigned char __user *)*rm;
267 dst = (unsigned char*) rn;
268 *(unsigned long*)dst = 0;
270 #if !defined(__LITTLE_ENDIAN__)
273 if (ma->from(dst, srcu, count))
275 sign_extend(count, dst);
280 switch ((instruction&0xFF00)>>8) {
281 case 0x81: /* mov.w R0,@(disp,Rn) */
282 src = (unsigned char *) ®s->regs[0];
283 #if !defined(__LITTLE_ENDIAN__)
286 dstu = (unsigned char __user *)*rm; /* called Rn in the spec */
287 dstu += (instruction & 0x000F) << 1;
289 if (ma->to(dstu, src, 2))
294 case 0x85: /* mov.w @(disp,Rm),R0 */
295 srcu = (unsigned char __user *)*rm;
296 srcu += (instruction & 0x000F) << 1;
297 dst = (unsigned char *) ®s->regs[0];
298 *(unsigned long *)dst = 0;
300 #if !defined(__LITTLE_ENDIAN__)
303 if (ma->from(dst, srcu, 2))
314 /* Argh. Address not only misaligned but also non-existent.
315 * Raise an EFAULT and see if it's trapped
317 die_if_no_fixup("Fault in unaligned fixup", regs, 0);
322 * emulate the instruction in the delay slot
323 * - fetches the instruction from PC+2
325 static inline int handle_delayslot(struct pt_regs *regs,
326 insn_size_t old_instruction,
327 struct mem_access *ma)
329 insn_size_t instruction;
330 void __user *addr = (void __user *)(regs->pc +
331 instruction_size(old_instruction));
333 if (copy_from_user(&instruction, addr, sizeof(instruction))) {
334 /* the instruction-fetch faulted */
339 die("delay-slot-insn faulting in handle_unaligned_delayslot",
343 return handle_unaligned_ins(instruction, regs, ma);
347 * handle an instruction that does an unaligned memory access
348 * - have to be careful of branch delay-slot instructions that fault
350 * - if the branch would be taken PC points to the branch
351 * - if the branch would not be taken, PC points to delay-slot
353 * - PC always points to delayed branch
354 * - return 0 if handled, -EFAULT if failed (may not return if in kernel)
357 /* Macros to determine offset from current PC for branch instructions */
358 /* Explicit type coercion is used to force sign extension where needed */
359 #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4)
360 #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4)
363 * XXX: SH-2A needs this too, but it needs an overhaul thanks to mixed 32-bit
367 static int handle_unaligned_notify_count = 10;
369 int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs,
370 struct mem_access *ma)
375 index = (instruction>>8)&15; /* 0x0F00 */
376 rm = regs->regs[index];
378 /* shout about the first ten userspace fixups */
379 if (user_mode(regs) && handle_unaligned_notify_count>0) {
380 handle_unaligned_notify_count--;
382 printk(KERN_NOTICE "Fixing up unaligned userspace access "
383 "in \"%s\" pid=%d pc=0x%p ins=0x%04hx\n",
384 current->comm, task_pid_nr(current),
385 (void *)regs->pc, instruction);
389 switch (instruction&0xF000) {
391 if (instruction==0x000B) {
393 ret = handle_delayslot(regs, instruction, ma);
397 else if ((instruction&0x00FF)==0x0023) {
399 ret = handle_delayslot(regs, instruction, ma);
403 else if ((instruction&0x00FF)==0x0003) {
405 ret = handle_delayslot(regs, instruction, ma);
407 regs->pr = regs->pc + 4;
412 /* mov.[bwl] to/from memory via r0+rn */
417 case 0x1000: /* mov.l Rm,@(disp,Rn) */
420 case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */
424 if ((instruction&0x00FF)==0x002B) {
426 ret = handle_delayslot(regs, instruction, ma);
430 else if ((instruction&0x00FF)==0x000B) {
432 ret = handle_delayslot(regs, instruction, ma);
434 regs->pr = regs->pc + 4;
439 /* mov.[bwl] to/from memory via r0+rn */
444 case 0x5000: /* mov.l @(disp,Rm),Rn */
447 case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */
450 case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */
451 switch (instruction&0x0F00) {
452 case 0x0100: /* mov.w R0,@(disp,Rm) */
454 case 0x0500: /* mov.w @(disp,Rm),R0 */
456 case 0x0B00: /* bf lab - no delayslot*/
458 case 0x0F00: /* bf/s lab */
459 ret = handle_delayslot(regs, instruction, ma);
461 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
462 if ((regs->sr & 0x00000001) != 0)
463 regs->pc += 4; /* next after slot */
466 regs->pc += SH_PC_8BIT_OFFSET(instruction);
469 case 0x0900: /* bt lab - no delayslot */
471 case 0x0D00: /* bt/s lab */
472 ret = handle_delayslot(regs, instruction, ma);
474 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
475 if ((regs->sr & 0x00000001) == 0)
476 regs->pc += 4; /* next after slot */
479 regs->pc += SH_PC_8BIT_OFFSET(instruction);
485 case 0xA000: /* bra label */
486 ret = handle_delayslot(regs, instruction, ma);
488 regs->pc += SH_PC_12BIT_OFFSET(instruction);
491 case 0xB000: /* bsr label */
492 ret = handle_delayslot(regs, instruction, ma);
494 regs->pr = regs->pc + 4;
495 regs->pc += SH_PC_12BIT_OFFSET(instruction);
501 /* handle non-delay-slot instruction */
503 ret = handle_unaligned_ins(instruction, regs, ma);
505 regs->pc += instruction_size(instruction);
510 * Handle various address error exceptions:
511 * - instruction address error:
513 * PC >= 0x80000000 in user mode
514 * - data address error (read and write)
515 * misaligned data access
516 * access to >= 0x80000000 is user mode
517 * Unfortuntaly we can't distinguish between instruction address error
518 * and data address errors caused by read accesses.
520 asmlinkage void do_address_error(struct pt_regs *regs,
521 unsigned long writeaccess,
522 unsigned long address)
524 unsigned long error_code = 0;
527 insn_size_t instruction;
530 /* Intentional ifdef */
531 #ifdef CONFIG_CPU_HAS_SR_RB
532 error_code = lookup_exception_vector();
537 if (user_mode(regs)) {
538 int si_code = BUS_ADRERR;
542 /* bad PC is not something we can fix */
544 si_code = BUS_ADRALN;
549 if (copy_from_user(&instruction, (void __user *)(regs->pc),
550 sizeof(instruction))) {
551 /* Argh. Fault on the instruction itself.
552 This should never happen non-SMP
558 tmp = handle_unaligned_access(instruction, regs,
565 printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned "
566 "access (PC %lx PR %lx)\n", current->comm, regs->pc,
569 info.si_signo = SIGBUS;
571 info.si_code = si_code;
572 info.si_addr = (void __user *)address;
573 force_sig_info(SIGBUS, &info, current);
576 die("unaligned program counter", regs, error_code);
579 if (copy_from_user(&instruction, (void __user *)(regs->pc),
580 sizeof(instruction))) {
581 /* Argh. Fault on the instruction itself.
582 This should never happen non-SMP
585 die("insn faulting in do_address_error", regs, 0);
588 handle_unaligned_access(instruction, regs, &user_mem_access);
595 * SH-DSP support gerg@snapgear.com.
597 int is_dsp_inst(struct pt_regs *regs)
599 unsigned short inst = 0;
602 * Safe guard if DSP mode is already enabled or we're lacking
603 * the DSP altogether.
605 if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP))
608 get_user(inst, ((unsigned short *) regs->pc));
612 /* Check for any type of DSP or support instruction */
613 if ((inst == 0xf000) || (inst == 0x4000))
619 #define is_dsp_inst(regs) (0)
620 #endif /* CONFIG_SH_DSP */
622 #ifdef CONFIG_CPU_SH2A
623 asmlinkage void do_divide_error(unsigned long r4, unsigned long r5,
624 unsigned long r6, unsigned long r7,
625 struct pt_regs __regs)
630 case TRAP_DIVZERO_ERROR:
631 info.si_code = FPE_INTDIV;
633 case TRAP_DIVOVF_ERROR:
634 info.si_code = FPE_INTOVF;
638 force_sig_info(SIGFPE, &info, current);
642 asmlinkage void do_reserved_inst(unsigned long r4, unsigned long r5,
643 unsigned long r6, unsigned long r7,
644 struct pt_regs __regs)
646 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
647 unsigned long error_code;
648 struct task_struct *tsk = current;
650 #ifdef CONFIG_SH_FPU_EMU
651 unsigned short inst = 0;
654 get_user(inst, (unsigned short*)regs->pc);
656 err = do_fpu_inst(inst, regs);
658 regs->pc += instruction_size(inst);
661 /* not a FPU inst. */
665 /* Check if it's a DSP instruction */
666 if (is_dsp_inst(regs)) {
667 /* Enable DSP mode, and restart instruction. */
670 tsk->thread.dsp_status.status |= SR_DSP;
675 error_code = lookup_exception_vector();
678 force_sig(SIGILL, tsk);
679 die_if_no_fixup("reserved instruction", regs, error_code);
682 #ifdef CONFIG_SH_FPU_EMU
683 static int emulate_branch(unsigned short inst, struct pt_regs *regs)
686 * bfs: 8fxx: PC+=d*2+4;
687 * bts: 8dxx: PC+=d*2+4;
688 * bra: axxx: PC+=D*2+4;
689 * bsr: bxxx: PC+=D*2+4 after PR=PC+4;
690 * braf:0x23: PC+=Rn*2+4;
691 * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4;
693 * jsr: 4x0b: PC=Rn after PR=PC+4;
696 if (((inst & 0xf000) == 0xb000) || /* bsr */
697 ((inst & 0xf0ff) == 0x0003) || /* bsrf */
698 ((inst & 0xf0ff) == 0x400b)) /* jsr */
699 regs->pr = regs->pc + 4;
701 if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */
702 regs->pc += SH_PC_8BIT_OFFSET(inst);
706 if ((inst & 0xe000) == 0xa000) { /* bra, bsr */
707 regs->pc += SH_PC_12BIT_OFFSET(inst);
711 if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */
712 regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4;
716 if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */
717 regs->pc = regs->regs[(inst & 0x0f00) >> 8];
721 if ((inst & 0xffff) == 0x000b) { /* rts */
730 asmlinkage void do_illegal_slot_inst(unsigned long r4, unsigned long r5,
731 unsigned long r6, unsigned long r7,
732 struct pt_regs __regs)
734 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
736 struct task_struct *tsk = current;
738 if (kprobe_handle_illslot(regs->pc) == 0)
741 #ifdef CONFIG_SH_FPU_EMU
742 get_user(inst, (unsigned short *)regs->pc + 1);
743 if (!do_fpu_inst(inst, regs)) {
744 get_user(inst, (unsigned short *)regs->pc);
745 if (!emulate_branch(inst, regs))
747 /* fault in branch.*/
749 /* not a FPU inst. */
752 inst = lookup_exception_vector();
755 force_sig(SIGILL, tsk);
756 die_if_no_fixup("illegal slot instruction", regs, inst);
759 asmlinkage void do_exception_error(unsigned long r4, unsigned long r5,
760 unsigned long r6, unsigned long r7,
761 struct pt_regs __regs)
763 struct pt_regs *regs = RELOC_HIDE(&__regs, 0);
766 ex = lookup_exception_vector();
767 die_if_kernel("exception", regs, ex);
770 #if defined(CONFIG_SH_STANDARD_BIOS)
771 void *gdb_vbr_vector;
773 static inline void __init gdb_vbr_init(void)
775 register unsigned long vbr;
778 * Read the old value of the VBR register to initialise
779 * the vector through which debug and BIOS traps are
780 * delegated by the Linux trap handler.
782 asm volatile("stc vbr, %0" : "=r" (vbr));
784 gdb_vbr_vector = (void *)(vbr + 0x100);
785 printk("Setting GDB trap vector to 0x%08lx\n",
786 (unsigned long)gdb_vbr_vector);
790 void __cpuinit per_cpu_trap_init(void)
792 extern void *vbr_base;
794 #ifdef CONFIG_SH_STANDARD_BIOS
795 if (raw_smp_processor_id() == 0)
799 /* NOTE: The VBR value should be at P1
800 (or P2, virtural "fixed" address space).
801 It's definitely should not in physical address. */
803 asm volatile("ldc %0, vbr"
809 void *set_exception_table_vec(unsigned int vec, void *handler)
811 extern void *exception_handling_table[];
814 old_handler = exception_handling_table[vec];
815 exception_handling_table[vec] = handler;
819 void __init trap_init(void)
821 set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst);
822 set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst);
824 #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \
825 defined(CONFIG_SH_FPU_EMU)
827 * For SH-4 lacking an FPU, treat floating point instructions as
828 * reserved. They'll be handled in the math-emu case, or faulted on
831 set_exception_table_evt(0x800, do_reserved_inst);
832 set_exception_table_evt(0x820, do_illegal_slot_inst);
833 #elif defined(CONFIG_SH_FPU)
834 #ifdef CONFIG_CPU_SUBTYPE_SHX3
835 set_exception_table_evt(0xd80, fpu_state_restore_trap_handler);
836 set_exception_table_evt(0xda0, fpu_state_restore_trap_handler);
838 set_exception_table_evt(0x800, fpu_state_restore_trap_handler);
839 set_exception_table_evt(0x820, fpu_state_restore_trap_handler);
843 #ifdef CONFIG_CPU_SH2
844 set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler);
846 #ifdef CONFIG_CPU_SH2A
847 set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error);
848 set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error);
850 set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler);
855 set_exception_table_vec(TRAP_UBC, break_point_trap);
858 /* Setup VBR for boot cpu */
862 void show_stack(struct task_struct *tsk, unsigned long *sp)
869 sp = (unsigned long *)current_stack_pointer;
871 sp = (unsigned long *)tsk->thread.sp;
873 stack = (unsigned long)sp;
874 dump_mem("Stack: ", stack, THREAD_SIZE +
875 (unsigned long)task_stack_page(tsk));
876 show_trace(tsk, sp, NULL);
879 void dump_stack(void)
881 show_stack(NULL, NULL);
883 EXPORT_SYMBOL(dump_stack);