arch/sh/kernel/cpu/sh4a/setup-sh7785.c

   1 /*
   2  * SH7785 Setup
   3  *
   4  *  Copyright (C) 2007  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/io.h>
  15 #include <linux/mm.h>
  16 #include <linux/sh_timer.h>
  17
  18 #include <asm/dmaengine.h>
  19 #include <asm/mmzone.h>
  20
  21 #include <cpu/dma-register.h>
  22
  23 static struct plat_sci_port scif0_platform_data = {
  24         .mapbase        = 0xffea0000,
  25         .flags          = UPF_BOOT_AUTOCONF,
  26         .type           = PORT_SCIF,
  27         .irqs           = { 40, 40, 40, 40 },
  28 };
  29
  30 static struct platform_device scif0_device = {
  31         .name           = "sh-sci",
  32         .id             = 0,
  33         .dev            = {
  34                 .platform_data  = &scif0_platform_data,
  35         },
  36 };
  37
  38 static struct plat_sci_port scif1_platform_data = {
  39         .mapbase        = 0xffeb0000,
  40         .flags          = UPF_BOOT_AUTOCONF,
  41         .type           = PORT_SCIF,
  42         .irqs           = { 44, 44, 44, 44 },
  43 };
  44
  45 static struct platform_device scif1_device = {
  46         .name           = "sh-sci",
  47         .id             = 1,
  48         .dev            = {
  49                 .platform_data  = &scif1_platform_data,
  50         },
  51 };
  52
  53 static struct plat_sci_port scif2_platform_data = {
  54         .mapbase        = 0xffec0000,
  55         .flags          = UPF_BOOT_AUTOCONF,
  56         .type           = PORT_SCIF,
  57         .irqs           = { 60, 60, 60, 60 },
  58 };
  59
  60 static struct platform_device scif2_device = {
  61         .name           = "sh-sci",
  62         .id             = 2,
  63         .dev            = {
  64                 .platform_data  = &scif2_platform_data,
  65         },
  66 };
  67
  68 static struct plat_sci_port scif3_platform_data = {
  69         .mapbase        = 0xffed0000,
  70         .flags          = UPF_BOOT_AUTOCONF,
  71         .type           = PORT_SCIF,
  72         .irqs           = { 61, 61, 61, 61 },
  73 };
  74
  75 static struct platform_device scif3_device = {
  76         .name           = "sh-sci",
  77         .id             = 3,
  78         .dev            = {
  79                 .platform_data  = &scif3_platform_data,
  80         },
  81 };
  82
  83 static struct plat_sci_port scif4_platform_data = {
  84         .mapbase        = 0xffee0000,
  85         .flags          = UPF_BOOT_AUTOCONF,
  86         .type           = PORT_SCIF,
  87         .irqs           = { 62, 62, 62, 62 },
  88 };
  89
  90 static struct platform_device scif4_device = {
  91         .name           = "sh-sci",
  92         .id             = 4,
  93         .dev            = {
  94                 .platform_data  = &scif4_platform_data,
  95         },
  96 };
  97
  98 static struct plat_sci_port scif5_platform_data = {
  99         .mapbase        = 0xffef0000,
 100         .flags          = UPF_BOOT_AUTOCONF,
 101         .type           = PORT_SCIF,
 102         .irqs           = { 63, 63, 63, 63 },
 103 };
 104
 105 static struct platform_device scif5_device = {
 106         .name           = "sh-sci",
 107         .id             = 5,
 108         .dev            = {
 109                 .platform_data  = &scif5_platform_data,
 110         },
 111 };
 112
 113 static struct sh_timer_config tmu0_platform_data = {
 114         .channel_offset = 0x04,
 115         .timer_bit = 0,
 116         .clk = "tmu012_fck",
 117         .clockevent_rating = 200,
 118 };
 119
 120 static struct resource tmu0_resources[] = {
 121         [0] = {
 122                 .start  = 0xffd80008,
 123                 .end    = 0xffd80013,
 124                 .flags  = IORESOURCE_MEM,
 125         },
 126         [1] = {
 127                 .start  = 28,
 128                 .flags  = IORESOURCE_IRQ,
 129         },
 130 };
 131
 132 static struct platform_device tmu0_device = {
 133         .name           = "sh_tmu",
 134         .id             = 0,
 135         .dev = {
 136                 .platform_data  = &tmu0_platform_data,
 137         },
 138         .resource       = tmu0_resources,
 139         .num_resources  = ARRAY_SIZE(tmu0_resources),
 140 };
 141
 142 static struct sh_timer_config tmu1_platform_data = {
 143         .channel_offset = 0x10,
 144         .timer_bit = 1,
 145         .clk = "tmu012_fck",
 146         .clocksource_rating = 200,
 147 };
 148
 149 static struct resource tmu1_resources[] = {
 150         [0] = {
 151                 .start  = 0xffd80014,
 152                 .end    = 0xffd8001f,
 153                 .flags  = IORESOURCE_MEM,
 154         },
 155         [1] = {
 156                 .start  = 29,
 157                 .flags  = IORESOURCE_IRQ,
 158         },
 159 };
 160
 161 static struct platform_device tmu1_device = {
 162         .name           = "sh_tmu",
 163         .id             = 1,
 164         .dev = {
 165                 .platform_data  = &tmu1_platform_data,
 166         },
 167         .resource       = tmu1_resources,
 168         .num_resources  = ARRAY_SIZE(tmu1_resources),
 169 };
 170
 171 static struct sh_timer_config tmu2_platform_data = {
 172         .channel_offset = 0x1c,
 173         .timer_bit = 2,
 174         .clk = "tmu012_fck",
 175 };
 176
 177 static struct resource tmu2_resources[] = {
 178         [0] = {
 179                 .start  = 0xffd80020,
 180                 .end    = 0xffd8002f,
 181                 .flags  = IORESOURCE_MEM,
 182         },
 183         [1] = {
 184                 .start  = 30,
 185                 .flags  = IORESOURCE_IRQ,
 186         },
 187 };
 188
 189 static struct platform_device tmu2_device = {
 190         .name           = "sh_tmu",
 191         .id             = 2,
 192         .dev = {
 193                 .platform_data  = &tmu2_platform_data,
 194         },
 195         .resource       = tmu2_resources,
 196         .num_resources  = ARRAY_SIZE(tmu2_resources),
 197 };
 198
 199 static struct sh_timer_config tmu3_platform_data = {
 200         .channel_offset = 0x04,
 201         .timer_bit = 0,
 202         .clk = "tmu345_fck",
 203 };
 204
 205 static struct resource tmu3_resources[] = {
 206         [0] = {
 207                 .start  = 0xffdc0008,
 208                 .end    = 0xffdc0013,
 209                 .flags  = IORESOURCE_MEM,
 210         },
 211         [1] = {
 212                 .start  = 96,
 213                 .flags  = IORESOURCE_IRQ,
 214         },
 215 };
 216
 217 static struct platform_device tmu3_device = {
 218         .name           = "sh_tmu",
 219         .id             = 3,
 220         .dev = {
 221                 .platform_data  = &tmu3_platform_data,
 222         },
 223         .resource       = tmu3_resources,
 224         .num_resources  = ARRAY_SIZE(tmu3_resources),
 225 };
 226
 227 static struct sh_timer_config tmu4_platform_data = {
 228         .channel_offset = 0x10,
 229         .timer_bit = 1,
 230         .clk = "tmu345_fck",
 231 };
 232
 233 static struct resource tmu4_resources[] = {
 234         [0] = {
 235                 .start  = 0xffdc0014,
 236                 .end    = 0xffdc001f,
 237                 .flags  = IORESOURCE_MEM,
 238         },
 239         [1] = {
 240                 .start  = 97,
 241                 .flags  = IORESOURCE_IRQ,
 242         },
 243 };
 244
 245 static struct platform_device tmu4_device = {
 246         .name           = "sh_tmu",
 247         .id             = 4,
 248         .dev = {
 249                 .platform_data  = &tmu4_platform_data,
 250         },
 251         .resource       = tmu4_resources,
 252         .num_resources  = ARRAY_SIZE(tmu4_resources),
 253 };
 254
 255 static struct sh_timer_config tmu5_platform_data = {
 256         .channel_offset = 0x1c,
 257         .timer_bit = 2,
 258         .clk = "tmu345_fck",
 259 };
 260
 261 static struct resource tmu5_resources[] = {
 262         [0] = {
 263                 .start  = 0xffdc0020,
 264                 .end    = 0xffdc002b,
 265                 .flags  = IORESOURCE_MEM,
 266         },
 267         [1] = {
 268                 .start  = 98,
 269                 .flags  = IORESOURCE_IRQ,
 270         },
 271 };
 272
 273 static struct platform_device tmu5_device = {
 274         .name           = "sh_tmu",
 275         .id             = 5,
 276         .dev = {
 277                 .platform_data  = &tmu5_platform_data,
 278         },
 279         .resource       = tmu5_resources,
 280         .num_resources  = ARRAY_SIZE(tmu5_resources),
 281 };
 282
 283 /* DMA */
 284 static struct sh_dmae_channel sh7785_dmae0_channels[] = {
 285         {
 286                 .offset = 0,
 287                 .dmars = 0,
 288                 .dmars_bit = 0,
 289         }, {
 290                 .offset = 0x10,
 291                 .dmars = 0,
 292                 .dmars_bit = 8,
 293         }, {
 294                 .offset = 0x20,
 295                 .dmars = 4,
 296                 .dmars_bit = 0,
 297         }, {
 298                 .offset = 0x30,
 299                 .dmars = 4,
 300                 .dmars_bit = 8,
 301         }, {
 302                 .offset = 0x50,
 303                 .dmars = 8,
 304                 .dmars_bit = 0,
 305         }, {
 306                 .offset = 0x60,
 307                 .dmars = 8,
 308                 .dmars_bit = 8,
 309         }
 310 };
 311
 312 static struct sh_dmae_channel sh7785_dmae1_channels[] = {
 313         {
 314                 .offset = 0,
 315         }, {
 316                 .offset = 0x10,
 317         }, {
 318                 .offset = 0x20,
 319         }, {
 320                 .offset = 0x30,
 321         }, {
 322                 .offset = 0x50,
 323         }, {
 324                 .offset = 0x60,
 325         }
 326 };
 327
 328 static unsigned int ts_shift[] = TS_SHIFT;
 329
 330 static struct sh_dmae_pdata dma0_platform_data = {
 331         .channel        = sh7785_dmae0_channels,
 332         .channel_num    = ARRAY_SIZE(sh7785_dmae0_channels),
 333         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 334         .ts_low_mask    = CHCR_TS_LOW_MASK,
 335         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 336         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 337         .ts_shift       = ts_shift,
 338         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 339         .dmaor_init     = DMAOR_INIT,
 340 };
 341
 342 static struct sh_dmae_pdata dma1_platform_data = {
 343         .channel        = sh7785_dmae1_channels,
 344         .channel_num    = ARRAY_SIZE(sh7785_dmae1_channels),
 345         .ts_low_shift   = CHCR_TS_LOW_SHIFT,
 346         .ts_low_mask    = CHCR_TS_LOW_MASK,
 347         .ts_high_shift  = CHCR_TS_HIGH_SHIFT,
 348         .ts_high_mask   = CHCR_TS_HIGH_MASK,
 349         .ts_shift       = ts_shift,
 350         .ts_shift_num   = ARRAY_SIZE(ts_shift),
 351         .dmaor_init     = DMAOR_INIT,
 352 };
 353
 354 static struct resource sh7785_dmae0_resources[] = {
 355         [0] = {
 356                 /* Channel registers and DMAOR */
 357                 .start  = 0xfc808020,
 358                 .end    = 0xfc80808f,
 359                 .flags  = IORESOURCE_MEM,
 360         },
 361         [1] = {
 362                 /* DMARSx */
 363                 .start  = 0xfc809000,
 364                 .end    = 0xfc80900b,
 365                 .flags  = IORESOURCE_MEM,
 366         },
 367         {
 368                 /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */
 369                 .start  = 33,
 370                 .end    = 33,
 371                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 372         },
 373 };
 374
 375 static struct resource sh7785_dmae1_resources[] = {
 376         [0] = {
 377                 /* Channel registers and DMAOR */
 378                 .start  = 0xfcc08020,
 379                 .end    = 0xfcc0808f,
 380                 .flags  = IORESOURCE_MEM,
 381         },
 382         /* DMAC1 has no DMARS */
 383         {
 384                 /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */
 385                 .start  = 52,
 386                 .end    = 52,
 387                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
 388         },
 389 };
 390
 391 static struct platform_device dma0_device = {
 392         .name           = "sh-dma-engine",
 393         .id             = 0,
 394         .resource       = sh7785_dmae0_resources,
 395         .num_resources  = ARRAY_SIZE(sh7785_dmae0_resources),
 396         .dev            = {
 397                 .platform_data  = &dma0_platform_data,
 398         },
 399 };
 400
 401 static struct platform_device dma1_device = {
 402         .name           = "sh-dma-engine",
 403         .id             = 1,
 404         .resource       = sh7785_dmae1_resources,
 405         .num_resources  = ARRAY_SIZE(sh7785_dmae1_resources),
 406         .dev            = {
 407                 .platform_data  = &dma1_platform_data,
 408         },
 409 };
 410
 411 static struct platform_device *sh7785_devices[] __initdata = {
 412         &scif0_device,
 413         &scif1_device,
 414         &scif2_device,
 415         &scif3_device,
 416         &scif4_device,
 417         &scif5_device,
 418         &tmu0_device,
 419         &tmu1_device,
 420         &tmu2_device,
 421         &tmu3_device,
 422         &tmu4_device,
 423         &tmu5_device,
 424         &dma0_device,
 425         &dma1_device,
 426 };
 427
 428 static int __init sh7785_devices_setup(void)
 429 {
 430         return platform_add_devices(sh7785_devices,
 431                                     ARRAY_SIZE(sh7785_devices));
 432 }
 433 arch_initcall(sh7785_devices_setup);
 434
 435 static struct platform_device *sh7785_early_devices[] __initdata = {
 436         &scif0_device,
 437         &scif1_device,
 438         &scif2_device,
 439         &scif3_device,
 440         &scif4_device,
 441         &scif5_device,
 442         &tmu0_device,
 443         &tmu1_device,
 444         &tmu2_device,
 445         &tmu3_device,
 446         &tmu4_device,
 447         &tmu5_device,
 448 };
 449
 450 void __init plat_early_device_setup(void)
 451 {
 452         early_platform_add_devices(sh7785_early_devices,
 453                                    ARRAY_SIZE(sh7785_early_devices));
 454 }
 455
 456 enum {
 457         UNUSED = 0,
 458
 459         /* interrupt sources */
 460
 461         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 462         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 463         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 464         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 465
 466         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 467         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 468         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 469         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 470
 471         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 472         WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 473         HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
 474         SCIF2, SCIF3, SCIF4, SCIF5,
 475         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
 476         SIOF, MMCIF, DU, GDTA,
 477         TMU3, TMU4, TMU5,
 478         SSI0, SSI1,
 479         HAC0, HAC1,
 480         FLCTL, GPIO,
 481
 482         /* interrupt groups */
 483
 484         TMU012, TMU345
 485 };
 486
 487 static struct intc_vect vectors[] __initdata = {
 488         INTC_VECT(WDT, 0x560),
 489         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 490         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 491         INTC_VECT(HUDI, 0x600),
 492         INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
 493         INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
 494         INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
 495         INTC_VECT(DMAC0, 0x6e0),
 496         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 497         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 498         INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
 499         INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
 500         INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
 501         INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
 502         INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
 503         INTC_VECT(DMAC1, 0x940),
 504         INTC_VECT(HSPI, 0x960),
 505         INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
 506         INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
 507         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 508         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 509         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 510         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 511         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 512         INTC_VECT(SIOF, 0xc00),
 513         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 514         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 515         INTC_VECT(DU, 0xd80),
 516         INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
 517         INTC_VECT(GDTA, 0xde0),
 518         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 519         INTC_VECT(TMU5, 0xe40),
 520         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
 521         INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
 522         INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
 523         INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
 524         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 525         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 526 };
 527
 528 static struct intc_group groups[] __initdata = {
 529         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 530         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 531 };
 532
 533 static struct intc_mask_reg mask_registers[] __initdata = {
 534         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 535           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 536
 537         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 538           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 539             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 540             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 541             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 542             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 543             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 544             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 545             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 546
 547         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 548           { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
 549             FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 550             PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
 551             SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
 552 };
 553
 554 static struct intc_prio_reg prio_registers[] __initdata = {
 555         { 0xffd00010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
 556                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
 557         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 558                                                  TMU2, TMU2_TICPI } },
 559         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
 560         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
 561                                                  SCIF2, SCIF3 } },
 562         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
 563         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
 564         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
 565                                                  PCISERR, PCIINTA } },
 566         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
 567                                                  PCIINTD, PCIC5 } },
 568         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
 569         { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
 570         { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
 571 };
 572
 573 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
 574                          mask_registers, prio_registers, NULL);
 575
 576 /* Support for external interrupt pins in IRQ mode */
 577
 578 static struct intc_vect vectors_irq0123[] __initdata = {
 579         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 580         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 581 };
 582
 583 static struct intc_vect vectors_irq4567[] __initdata = {
 584         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 585         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 586 };
 587
 588 static struct intc_sense_reg sense_registers[] __initdata = {
 589         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 590                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 591 };
 592
 593 static struct intc_mask_reg ack_registers[] __initdata = {
 594         { 0xffd00024, 0, 32, /* INTREQ */
 595           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 596 };
 597
 598 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
 599                              vectors_irq0123, NULL, mask_registers,
 600                              prio_registers, sense_registers, ack_registers);
 601
 602 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
 603                              vectors_irq4567, NULL, mask_registers,
 604                              prio_registers, sense_registers, ack_registers);
 605
 606 /* External interrupt pins in IRL mode */
 607
 608 static struct intc_vect vectors_irl0123[] __initdata = {
 609         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 610         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 611         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 612         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 613         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 614         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 615         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 616         INTC_VECT(IRL0_HHHL, 0x3c0),
 617 };
 618
 619 static struct intc_vect vectors_irl4567[] __initdata = {
 620         INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
 621         INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
 622         INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
 623         INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
 624         INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
 625         INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
 626         INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
 627         INTC_VECT(IRL4_HHHL, 0xcc0),
 628 };
 629
 630 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
 631                          NULL, mask_registers, NULL, NULL);
 632
 633 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
 634                          NULL, mask_registers, NULL, NULL);
 635
 636 #define INTC_ICR0       0xffd00000
 637 #define INTC_INTMSK0    0xffd00044
 638 #define INTC_INTMSK1    0xffd00048
 639 #define INTC_INTMSK2    0xffd40080
 640 #define INTC_INTMSKCLR1 0xffd00068
 641 #define INTC_INTMSKCLR2 0xffd40084
 642
 643 void __init plat_irq_setup(void)
 644 {
 645         /* disable IRQ3-0 + IRQ7-4 */
 646         __raw_writel(0xff000000, INTC_INTMSK0);
 647
 648         /* disable IRL3-0 + IRL7-4 */
 649         __raw_writel(0xc0000000, INTC_INTMSK1);
 650         __raw_writel(0xfffefffe, INTC_INTMSK2);
 651
 652         /* select IRL mode for IRL3-0 + IRL7-4 */
 653         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 654
 655         /* disable holding function, ie enable "SH-4 Mode" */
 656         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 657
 658         register_intc_controller(&intc_desc);
 659 }
 660
 661 void __init plat_irq_setup_pins(int mode)
 662 {
 663         switch (mode) {
 664         case IRQ_MODE_IRQ7654:
 665                 /* select IRQ mode for IRL7-4 */
 666                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 667                 register_intc_controller(&intc_desc_irq4567);
 668                 break;
 669         case IRQ_MODE_IRQ3210:
 670                 /* select IRQ mode for IRL3-0 */
 671                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 672                 register_intc_controller(&intc_desc_irq0123);
 673                 break;
 674         case IRQ_MODE_IRL7654:
 675                 /* enable IRL7-4 but don't provide any masking */
 676                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 677                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 678                 break;
 679         case IRQ_MODE_IRL3210:
 680                 /* enable IRL0-3 but don't provide any masking */
 681                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 682                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 683                 break;
 684         case IRQ_MODE_IRL7654_MASK:
 685                 /* enable IRL7-4 and mask using cpu intc controller */
 686                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 687                 register_intc_controller(&intc_desc_irl4567);
 688                 break;
 689         case IRQ_MODE_IRL3210_MASK:
 690                 /* enable IRL0-3 and mask using cpu intc controller */
 691                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 692                 register_intc_controller(&intc_desc_irl0123);
 693                 break;
 694         default:
 695                 BUG();
 696         }
 697 }
 698
 699 void __init plat_mem_setup(void)
 700 {
 701         /* Register the URAM space as Node 1 */
 702         setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
 703 }