arch/sh/kernel/cpu/sh4a/setup-sh7785.c

   1 /*
   2  * SH7785 Setup
   3  *
   4  *  Copyright (C) 2007  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/io.h>
  15 #include <linux/mm.h>
  16 #include <linux/sh_timer.h>
  17 #include <asm/mmzone.h>
  18
  19 static struct plat_sci_port scif0_platform_data = {
  20         .mapbase        = 0xffea0000,
  21         .flags          = UPF_BOOT_AUTOCONF,
  22         .type           = PORT_SCIF,
  23         .irqs           = { 40, 40, 40, 40 },
  24         .clk            = "scif_fck",
  25 };
  26
  27 static struct platform_device scif0_device = {
  28         .name           = "sh-sci",
  29         .id             = 0,
  30         .dev            = {
  31                 .platform_data  = &scif0_platform_data,
  32         },
  33 };
  34
  35 static struct plat_sci_port scif1_platform_data = {
  36         .mapbase        = 0xffeb0000,
  37         .flags          = UPF_BOOT_AUTOCONF,
  38         .type           = PORT_SCIF,
  39         .irqs           = { 44, 44, 44, 44 },
  40         .clk            = "scif_fck",
  41 };
  42
  43 static struct platform_device scif1_device = {
  44         .name           = "sh-sci",
  45         .id             = 1,
  46         .dev            = {
  47                 .platform_data  = &scif1_platform_data,
  48         },
  49 };
  50
  51 static struct plat_sci_port scif2_platform_data = {
  52         .mapbase        = 0xffec0000,
  53         .flags          = UPF_BOOT_AUTOCONF,
  54         .type           = PORT_SCIF,
  55         .irqs           = { 60, 60, 60, 60 },
  56         .clk            = "scif_fck",
  57 };
  58
  59 static struct platform_device scif2_device = {
  60         .name           = "sh-sci",
  61         .id             = 2,
  62         .dev            = {
  63                 .platform_data  = &scif2_platform_data,
  64         },
  65 };
  66
  67 static struct plat_sci_port scif3_platform_data = {
  68         .mapbase        = 0xffed0000,
  69         .flags          = UPF_BOOT_AUTOCONF,
  70         .type           = PORT_SCIF,
  71         .irqs           = { 61, 61, 61, 61 },
  72         .clk            = "scif_fck",
  73 };
  74
  75 static struct platform_device scif3_device = {
  76         .name           = "sh-sci",
  77         .id             = 3,
  78         .dev            = {
  79                 .platform_data  = &scif3_platform_data,
  80         },
  81 };
  82
  83 static struct plat_sci_port scif4_platform_data = {
  84         .mapbase        = 0xffee0000,
  85         .flags          = UPF_BOOT_AUTOCONF,
  86         .type           = PORT_SCIF,
  87         .irqs           = { 62, 62, 62, 62 },
  88         .clk            = "scif_fck",
  89 };
  90
  91 static struct platform_device scif4_device = {
  92         .name           = "sh-sci",
  93         .id             = 4,
  94         .dev            = {
  95                 .platform_data  = &scif4_platform_data,
  96         },
  97 };
  98
  99 static struct plat_sci_port scif5_platform_data = {
 100         .mapbase        = 0xffef0000,
 101         .flags          = UPF_BOOT_AUTOCONF,
 102         .type           = PORT_SCIF,
 103         .irqs           = { 63, 63, 63, 63 },
 104         .clk            = "scif_fck",
 105 };
 106
 107 static struct platform_device scif5_device = {
 108         .name           = "sh-sci",
 109         .id             = 5,
 110         .dev            = {
 111                 .platform_data  = &scif5_platform_data,
 112         },
 113 };
 114
 115 static struct sh_timer_config tmu0_platform_data = {
 116         .name = "TMU0",
 117         .channel_offset = 0x04,
 118         .timer_bit = 0,
 119         .clk = "tmu012_fck",
 120         .clockevent_rating = 200,
 121 };
 122
 123 static struct resource tmu0_resources[] = {
 124         [0] = {
 125                 .name   = "TMU0",
 126                 .start  = 0xffd80008,
 127                 .end    = 0xffd80013,
 128                 .flags  = IORESOURCE_MEM,
 129         },
 130         [1] = {
 131                 .start  = 28,
 132                 .flags  = IORESOURCE_IRQ,
 133         },
 134 };
 135
 136 static struct platform_device tmu0_device = {
 137         .name           = "sh_tmu",
 138         .id             = 0,
 139         .dev = {
 140                 .platform_data  = &tmu0_platform_data,
 141         },
 142         .resource       = tmu0_resources,
 143         .num_resources  = ARRAY_SIZE(tmu0_resources),
 144 };
 145
 146 static struct sh_timer_config tmu1_platform_data = {
 147         .name = "TMU1",
 148         .channel_offset = 0x10,
 149         .timer_bit = 1,
 150         .clk = "tmu012_fck",
 151         .clocksource_rating = 200,
 152 };
 153
 154 static struct resource tmu1_resources[] = {
 155         [0] = {
 156                 .name   = "TMU1",
 157                 .start  = 0xffd80014,
 158                 .end    = 0xffd8001f,
 159                 .flags  = IORESOURCE_MEM,
 160         },
 161         [1] = {
 162                 .start  = 29,
 163                 .flags  = IORESOURCE_IRQ,
 164         },
 165 };
 166
 167 static struct platform_device tmu1_device = {
 168         .name           = "sh_tmu",
 169         .id             = 1,
 170         .dev = {
 171                 .platform_data  = &tmu1_platform_data,
 172         },
 173         .resource       = tmu1_resources,
 174         .num_resources  = ARRAY_SIZE(tmu1_resources),
 175 };
 176
 177 static struct sh_timer_config tmu2_platform_data = {
 178         .name = "TMU2",
 179         .channel_offset = 0x1c,
 180         .timer_bit = 2,
 181         .clk = "tmu012_fck",
 182 };
 183
 184 static struct resource tmu2_resources[] = {
 185         [0] = {
 186                 .name   = "TMU2",
 187                 .start  = 0xffd80020,
 188                 .end    = 0xffd8002f,
 189                 .flags  = IORESOURCE_MEM,
 190         },
 191         [1] = {
 192                 .start  = 30,
 193                 .flags  = IORESOURCE_IRQ,
 194         },
 195 };
 196
 197 static struct platform_device tmu2_device = {
 198         .name           = "sh_tmu",
 199         .id             = 2,
 200         .dev = {
 201                 .platform_data  = &tmu2_platform_data,
 202         },
 203         .resource       = tmu2_resources,
 204         .num_resources  = ARRAY_SIZE(tmu2_resources),
 205 };
 206
 207 static struct sh_timer_config tmu3_platform_data = {
 208         .name = "TMU3",
 209         .channel_offset = 0x04,
 210         .timer_bit = 0,
 211         .clk = "tmu345_fck",
 212 };
 213
 214 static struct resource tmu3_resources[] = {
 215         [0] = {
 216                 .name   = "TMU3",
 217                 .start  = 0xffdc0008,
 218                 .end    = 0xffdc0013,
 219                 .flags  = IORESOURCE_MEM,
 220         },
 221         [1] = {
 222                 .start  = 96,
 223                 .flags  = IORESOURCE_IRQ,
 224         },
 225 };
 226
 227 static struct platform_device tmu3_device = {
 228         .name           = "sh_tmu",
 229         .id             = 3,
 230         .dev = {
 231                 .platform_data  = &tmu3_platform_data,
 232         },
 233         .resource       = tmu3_resources,
 234         .num_resources  = ARRAY_SIZE(tmu3_resources),
 235 };
 236
 237 static struct sh_timer_config tmu4_platform_data = {
 238         .name = "TMU4",
 239         .channel_offset = 0x10,
 240         .timer_bit = 1,
 241         .clk = "tmu345_fck",
 242 };
 243
 244 static struct resource tmu4_resources[] = {
 245         [0] = {
 246                 .name   = "TMU4",
 247                 .start  = 0xffdc0014,
 248                 .end    = 0xffdc001f,
 249                 .flags  = IORESOURCE_MEM,
 250         },
 251         [1] = {
 252                 .start  = 97,
 253                 .flags  = IORESOURCE_IRQ,
 254         },
 255 };
 256
 257 static struct platform_device tmu4_device = {
 258         .name           = "sh_tmu",
 259         .id             = 4,
 260         .dev = {
 261                 .platform_data  = &tmu4_platform_data,
 262         },
 263         .resource       = tmu4_resources,
 264         .num_resources  = ARRAY_SIZE(tmu4_resources),
 265 };
 266
 267 static struct sh_timer_config tmu5_platform_data = {
 268         .name = "TMU5",
 269         .channel_offset = 0x1c,
 270         .timer_bit = 2,
 271         .clk = "tmu345_fck",
 272 };
 273
 274 static struct resource tmu5_resources[] = {
 275         [0] = {
 276                 .name   = "TMU5",
 277                 .start  = 0xffdc0020,
 278                 .end    = 0xffdc002b,
 279                 .flags  = IORESOURCE_MEM,
 280         },
 281         [1] = {
 282                 .start  = 98,
 283                 .flags  = IORESOURCE_IRQ,
 284         },
 285 };
 286
 287 static struct platform_device tmu5_device = {
 288         .name           = "sh_tmu",
 289         .id             = 5,
 290         .dev = {
 291                 .platform_data  = &tmu5_platform_data,
 292         },
 293         .resource       = tmu5_resources,
 294         .num_resources  = ARRAY_SIZE(tmu5_resources),
 295 };
 296
 297 static struct platform_device *sh7785_devices[] __initdata = {
 298         &scif0_device,
 299         &scif1_device,
 300         &scif2_device,
 301         &scif3_device,
 302         &scif4_device,
 303         &scif5_device,
 304         &tmu0_device,
 305         &tmu1_device,
 306         &tmu2_device,
 307         &tmu3_device,
 308         &tmu4_device,
 309         &tmu5_device,
 310 };
 311
 312 static int __init sh7785_devices_setup(void)
 313 {
 314         return platform_add_devices(sh7785_devices,
 315                                     ARRAY_SIZE(sh7785_devices));
 316 }
 317 arch_initcall(sh7785_devices_setup);
 318
 319 static struct platform_device *sh7785_early_devices[] __initdata = {
 320         &scif0_device,
 321         &scif1_device,
 322         &scif2_device,
 323         &scif3_device,
 324         &scif4_device,
 325         &scif5_device,
 326         &tmu0_device,
 327         &tmu1_device,
 328         &tmu2_device,
 329         &tmu3_device,
 330         &tmu4_device,
 331         &tmu5_device,
 332 };
 333
 334 void __init plat_early_device_setup(void)
 335 {
 336         early_platform_add_devices(sh7785_early_devices,
 337                                    ARRAY_SIZE(sh7785_early_devices));
 338 }
 339
 340 enum {
 341         UNUSED = 0,
 342
 343         /* interrupt sources */
 344
 345         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 346         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 347         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 348         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 349
 350         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 351         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 352         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 353         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 354
 355         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 356         WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
 357         HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
 358         SCIF2, SCIF3, SCIF4, SCIF5,
 359         PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
 360         SIOF, MMCIF, DU, GDTA,
 361         TMU3, TMU4, TMU5,
 362         SSI0, SSI1,
 363         HAC0, HAC1,
 364         FLCTL, GPIO,
 365
 366         /* interrupt groups */
 367
 368         TMU012, TMU345
 369 };
 370
 371 static struct intc_vect vectors[] __initdata = {
 372         INTC_VECT(WDT, 0x560),
 373         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 374         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 375         INTC_VECT(HUDI, 0x600),
 376         INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
 377         INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
 378         INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
 379         INTC_VECT(DMAC0, 0x6e0),
 380         INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
 381         INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
 382         INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
 383         INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
 384         INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
 385         INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
 386         INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
 387         INTC_VECT(DMAC1, 0x940),
 388         INTC_VECT(HSPI, 0x960),
 389         INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
 390         INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
 391         INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
 392         INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
 393         INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
 394         INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
 395         INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
 396         INTC_VECT(SIOF, 0xc00),
 397         INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
 398         INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
 399         INTC_VECT(DU, 0xd80),
 400         INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
 401         INTC_VECT(GDTA, 0xde0),
 402         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 403         INTC_VECT(TMU5, 0xe40),
 404         INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
 405         INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
 406         INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
 407         INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
 408         INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
 409         INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
 410 };
 411
 412 static struct intc_group groups[] __initdata = {
 413         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 414         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 415 };
 416
 417 static struct intc_mask_reg mask_registers[] __initdata = {
 418         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 419           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 420
 421         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 422           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 423             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 424             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 425             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 426             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 427             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 428             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 429             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 430
 431         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 432           { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
 433             FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
 434             PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
 435             SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
 436 };
 437
 438 static struct intc_prio_reg prio_registers[] __initdata = {
 439         { 0xffd00010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
 440                                                  IRQ4, IRQ5, IRQ6, IRQ7 } },
 441         { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
 442                                                  TMU2, TMU2_TICPI } },
 443         { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
 444         { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
 445                                                  SCIF2, SCIF3 } },
 446         { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
 447         { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
 448         { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
 449                                                  PCISERR, PCIINTA } },
 450         { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
 451                                                  PCIINTD, PCIC5 } },
 452         { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
 453         { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
 454         { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
 455 };
 456
 457 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
 458                          mask_registers, prio_registers, NULL);
 459
 460 /* Support for external interrupt pins in IRQ mode */
 461
 462 static struct intc_vect vectors_irq0123[] __initdata = {
 463         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 464         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 465 };
 466
 467 static struct intc_vect vectors_irq4567[] __initdata = {
 468         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 469         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 470 };
 471
 472 static struct intc_sense_reg sense_registers[] __initdata = {
 473         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 474                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 475 };
 476
 477 static struct intc_mask_reg ack_registers[] __initdata = {
 478         { 0xffd00024, 0, 32, /* INTREQ */
 479           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 480 };
 481
 482 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
 483                              vectors_irq0123, NULL, mask_registers,
 484                              prio_registers, sense_registers, ack_registers);
 485
 486 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
 487                              vectors_irq4567, NULL, mask_registers,
 488                              prio_registers, sense_registers, ack_registers);
 489
 490 /* External interrupt pins in IRL mode */
 491
 492 static struct intc_vect vectors_irl0123[] __initdata = {
 493         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 494         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 495         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 496         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 497         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 498         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 499         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 500         INTC_VECT(IRL0_HHHL, 0x3c0),
 501 };
 502
 503 static struct intc_vect vectors_irl4567[] __initdata = {
 504         INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
 505         INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
 506         INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
 507         INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
 508         INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
 509         INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
 510         INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
 511         INTC_VECT(IRL4_HHHL, 0xcc0),
 512 };
 513
 514 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
 515                          NULL, mask_registers, NULL, NULL);
 516
 517 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
 518                          NULL, mask_registers, NULL, NULL);
 519
 520 #define INTC_ICR0       0xffd00000
 521 #define INTC_INTMSK0    0xffd00044
 522 #define INTC_INTMSK1    0xffd00048
 523 #define INTC_INTMSK2    0xffd40080
 524 #define INTC_INTMSKCLR1 0xffd00068
 525 #define INTC_INTMSKCLR2 0xffd40084
 526
 527 void __init plat_irq_setup(void)
 528 {
 529         /* disable IRQ3-0 + IRQ7-4 */
 530         ctrl_outl(0xff000000, INTC_INTMSK0);
 531
 532         /* disable IRL3-0 + IRL7-4 */
 533         ctrl_outl(0xc0000000, INTC_INTMSK1);
 534         ctrl_outl(0xfffefffe, INTC_INTMSK2);
 535
 536         /* select IRL mode for IRL3-0 + IRL7-4 */
 537         ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 538
 539         /* disable holding function, ie enable "SH-4 Mode" */
 540         ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 541
 542         register_intc_controller(&intc_desc);
 543 }
 544
 545 void __init plat_irq_setup_pins(int mode)
 546 {
 547         switch (mode) {
 548         case IRQ_MODE_IRQ7654:
 549                 /* select IRQ mode for IRL7-4 */
 550                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 551                 register_intc_controller(&intc_desc_irq4567);
 552                 break;
 553         case IRQ_MODE_IRQ3210:
 554                 /* select IRQ mode for IRL3-0 */
 555                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 556                 register_intc_controller(&intc_desc_irq0123);
 557                 break;
 558         case IRQ_MODE_IRL7654:
 559                 /* enable IRL7-4 but don't provide any masking */
 560                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 561                 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
 562                 break;
 563         case IRQ_MODE_IRL3210:
 564                 /* enable IRL0-3 but don't provide any masking */
 565                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 566                 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
 567                 break;
 568         case IRQ_MODE_IRL7654_MASK:
 569                 /* enable IRL7-4 and mask using cpu intc controller */
 570                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 571                 register_intc_controller(&intc_desc_irl4567);
 572                 break;
 573         case IRQ_MODE_IRL3210_MASK:
 574                 /* enable IRL0-3 and mask using cpu intc controller */
 575                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 576                 register_intc_controller(&intc_desc_irl0123);
 577                 break;
 578         default:
 579                 BUG();
 580         }
 581 }
 582
 583 void __init plat_mem_setup(void)
 584 {
 585         /* Register the URAM space as Node 1 */
 586         setup_bootmem_node(1, 0xe55f0000, 0xe5610000);
 587 }