4 * Copyright (C) 2007 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
16 #include <linux/sh_timer.h>
18 #include <asm/dmaengine.h>
19 #include <asm/mmzone.h>
21 #include <cpu/dma-register.h>
23 static struct plat_sci_port scif0_platform_data = {
24 .mapbase = 0xffea0000,
25 .flags = UPF_BOOT_AUTOCONF,
27 .irqs = { 40, 40, 40, 40 },
30 static struct platform_device scif0_device = {
34 .platform_data = &scif0_platform_data,
38 static struct plat_sci_port scif1_platform_data = {
39 .mapbase = 0xffeb0000,
40 .flags = UPF_BOOT_AUTOCONF,
42 .irqs = { 44, 44, 44, 44 },
45 static struct platform_device scif1_device = {
49 .platform_data = &scif1_platform_data,
53 static struct plat_sci_port scif2_platform_data = {
54 .mapbase = 0xffec0000,
55 .flags = UPF_BOOT_AUTOCONF,
57 .irqs = { 60, 60, 60, 60 },
60 static struct platform_device scif2_device = {
64 .platform_data = &scif2_platform_data,
68 static struct plat_sci_port scif3_platform_data = {
69 .mapbase = 0xffed0000,
70 .flags = UPF_BOOT_AUTOCONF,
72 .irqs = { 61, 61, 61, 61 },
75 static struct platform_device scif3_device = {
79 .platform_data = &scif3_platform_data,
83 static struct plat_sci_port scif4_platform_data = {
84 .mapbase = 0xffee0000,
85 .flags = UPF_BOOT_AUTOCONF,
87 .irqs = { 62, 62, 62, 62 },
90 static struct platform_device scif4_device = {
94 .platform_data = &scif4_platform_data,
98 static struct plat_sci_port scif5_platform_data = {
99 .mapbase = 0xffef0000,
100 .flags = UPF_BOOT_AUTOCONF,
102 .irqs = { 63, 63, 63, 63 },
105 static struct platform_device scif5_device = {
109 .platform_data = &scif5_platform_data,
113 static struct sh_timer_config tmu0_platform_data = {
114 .channel_offset = 0x04,
117 .clockevent_rating = 200,
120 static struct resource tmu0_resources[] = {
124 .flags = IORESOURCE_MEM,
128 .flags = IORESOURCE_IRQ,
132 static struct platform_device tmu0_device = {
136 .platform_data = &tmu0_platform_data,
138 .resource = tmu0_resources,
139 .num_resources = ARRAY_SIZE(tmu0_resources),
142 static struct sh_timer_config tmu1_platform_data = {
143 .channel_offset = 0x10,
146 .clocksource_rating = 200,
149 static struct resource tmu1_resources[] = {
153 .flags = IORESOURCE_MEM,
157 .flags = IORESOURCE_IRQ,
161 static struct platform_device tmu1_device = {
165 .platform_data = &tmu1_platform_data,
167 .resource = tmu1_resources,
168 .num_resources = ARRAY_SIZE(tmu1_resources),
171 static struct sh_timer_config tmu2_platform_data = {
172 .channel_offset = 0x1c,
177 static struct resource tmu2_resources[] = {
181 .flags = IORESOURCE_MEM,
185 .flags = IORESOURCE_IRQ,
189 static struct platform_device tmu2_device = {
193 .platform_data = &tmu2_platform_data,
195 .resource = tmu2_resources,
196 .num_resources = ARRAY_SIZE(tmu2_resources),
199 static struct sh_timer_config tmu3_platform_data = {
200 .channel_offset = 0x04,
205 static struct resource tmu3_resources[] = {
209 .flags = IORESOURCE_MEM,
213 .flags = IORESOURCE_IRQ,
217 static struct platform_device tmu3_device = {
221 .platform_data = &tmu3_platform_data,
223 .resource = tmu3_resources,
224 .num_resources = ARRAY_SIZE(tmu3_resources),
227 static struct sh_timer_config tmu4_platform_data = {
228 .channel_offset = 0x10,
233 static struct resource tmu4_resources[] = {
237 .flags = IORESOURCE_MEM,
241 .flags = IORESOURCE_IRQ,
245 static struct platform_device tmu4_device = {
249 .platform_data = &tmu4_platform_data,
251 .resource = tmu4_resources,
252 .num_resources = ARRAY_SIZE(tmu4_resources),
255 static struct sh_timer_config tmu5_platform_data = {
256 .channel_offset = 0x1c,
261 static struct resource tmu5_resources[] = {
265 .flags = IORESOURCE_MEM,
269 .flags = IORESOURCE_IRQ,
273 static struct platform_device tmu5_device = {
277 .platform_data = &tmu5_platform_data,
279 .resource = tmu5_resources,
280 .num_resources = ARRAY_SIZE(tmu5_resources),
284 static struct sh_dmae_channel sh7785_dmae0_channels[] = {
312 static struct sh_dmae_channel sh7785_dmae1_channels[] = {
328 static unsigned int ts_shift[] = TS_SHIFT;
330 static struct sh_dmae_pdata dma0_platform_data = {
331 .channel = sh7785_dmae0_channels,
332 .channel_num = ARRAY_SIZE(sh7785_dmae0_channels),
333 .ts_low_shift = CHCR_TS_LOW_SHIFT,
334 .ts_low_mask = CHCR_TS_LOW_MASK,
335 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
336 .ts_high_mask = CHCR_TS_HIGH_MASK,
337 .ts_shift = ts_shift,
338 .ts_shift_num = ARRAY_SIZE(ts_shift),
339 .dmaor_init = DMAOR_INIT,
342 static struct sh_dmae_pdata dma1_platform_data = {
343 .channel = sh7785_dmae1_channels,
344 .channel_num = ARRAY_SIZE(sh7785_dmae1_channels),
345 .ts_low_shift = CHCR_TS_LOW_SHIFT,
346 .ts_low_mask = CHCR_TS_LOW_MASK,
347 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
348 .ts_high_mask = CHCR_TS_HIGH_MASK,
349 .ts_shift = ts_shift,
350 .ts_shift_num = ARRAY_SIZE(ts_shift),
351 .dmaor_init = DMAOR_INIT,
354 static struct resource sh7785_dmae0_resources[] = {
356 /* Channel registers and DMAOR */
359 .flags = IORESOURCE_MEM,
365 .flags = IORESOURCE_MEM,
368 /* Real DMA error IRQ is 39, and channel IRQs are 33-38 */
371 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
375 static struct resource sh7785_dmae1_resources[] = {
377 /* Channel registers and DMAOR */
380 .flags = IORESOURCE_MEM,
382 /* DMAC1 has no DMARS */
384 /* Real DMA error IRQ is 58, and channel IRQs are 52-57 */
387 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
391 static struct platform_device dma0_device = {
392 .name = "sh-dma-engine",
394 .resource = sh7785_dmae0_resources,
395 .num_resources = ARRAY_SIZE(sh7785_dmae0_resources),
397 .platform_data = &dma0_platform_data,
401 static struct platform_device dma1_device = {
402 .name = "sh-dma-engine",
404 .resource = sh7785_dmae1_resources,
405 .num_resources = ARRAY_SIZE(sh7785_dmae1_resources),
407 .platform_data = &dma1_platform_data,
411 static struct platform_device *sh7785_devices[] __initdata = {
428 static int __init sh7785_devices_setup(void)
430 return platform_add_devices(sh7785_devices,
431 ARRAY_SIZE(sh7785_devices));
433 arch_initcall(sh7785_devices_setup);
435 static struct platform_device *sh7785_early_devices[] __initdata = {
450 void __init plat_early_device_setup(void)
452 early_platform_add_devices(sh7785_early_devices,
453 ARRAY_SIZE(sh7785_early_devices));
459 /* interrupt sources */
461 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
462 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
463 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
464 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
466 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
467 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
468 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
469 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
471 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
472 WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
473 HUDI, DMAC0, SCIF0, SCIF1, DMAC1, HSPI,
474 SCIF2, SCIF3, SCIF4, SCIF5,
475 PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
476 SIOF, MMCIF, DU, GDTA,
482 /* interrupt groups */
487 static struct intc_vect vectors[] __initdata = {
488 INTC_VECT(WDT, 0x560),
489 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
490 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
491 INTC_VECT(HUDI, 0x600),
492 INTC_VECT(DMAC0, 0x620), INTC_VECT(DMAC0, 0x640),
493 INTC_VECT(DMAC0, 0x660), INTC_VECT(DMAC0, 0x680),
494 INTC_VECT(DMAC0, 0x6a0), INTC_VECT(DMAC0, 0x6c0),
495 INTC_VECT(DMAC0, 0x6e0),
496 INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
497 INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
498 INTC_VECT(SCIF1, 0x780), INTC_VECT(SCIF1, 0x7a0),
499 INTC_VECT(SCIF1, 0x7c0), INTC_VECT(SCIF1, 0x7e0),
500 INTC_VECT(DMAC1, 0x880), INTC_VECT(DMAC1, 0x8a0),
501 INTC_VECT(DMAC1, 0x8c0), INTC_VECT(DMAC1, 0x8e0),
502 INTC_VECT(DMAC1, 0x900), INTC_VECT(DMAC1, 0x920),
503 INTC_VECT(DMAC1, 0x940),
504 INTC_VECT(HSPI, 0x960),
505 INTC_VECT(SCIF2, 0x980), INTC_VECT(SCIF3, 0x9a0),
506 INTC_VECT(SCIF4, 0x9c0), INTC_VECT(SCIF5, 0x9e0),
507 INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
508 INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
509 INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
510 INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
511 INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
512 INTC_VECT(SIOF, 0xc00),
513 INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
514 INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
515 INTC_VECT(DU, 0xd80),
516 INTC_VECT(GDTA, 0xda0), INTC_VECT(GDTA, 0xdc0),
517 INTC_VECT(GDTA, 0xde0),
518 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
519 INTC_VECT(TMU5, 0xe40),
520 INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0),
521 INTC_VECT(HAC0, 0xec0), INTC_VECT(HAC1, 0xee0),
522 INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
523 INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
524 INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
525 INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
528 static struct intc_group groups[] __initdata = {
529 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
530 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
533 static struct intc_mask_reg mask_registers[] __initdata = {
534 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
535 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
537 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
538 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
539 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
540 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
541 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
542 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
543 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
544 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
545 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
547 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
548 { 0, 0, 0, GDTA, DU, SSI0, SSI1, GPIO,
549 FLCTL, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
550 PCIINTA, PCISERR, HAC1, HAC0, DMAC1, DMAC0, HUDI, WDT,
551 SCIF5, SCIF4, SCIF3, SCIF2, SCIF1, SCIF0, TMU345, TMU012 } },
554 static struct intc_prio_reg prio_registers[] __initdata = {
555 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
556 IRQ4, IRQ5, IRQ6, IRQ7 } },
557 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
558 TMU2, TMU2_TICPI } },
559 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, } },
560 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1,
562 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { SCIF4, SCIF5, WDT, } },
563 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { HUDI, DMAC0, DMAC1, } },
564 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { HAC0, HAC1,
565 PCISERR, PCIINTA } },
566 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { PCIINTB, PCIINTC,
568 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SIOF, HSPI, MMCIF, } },
569 { 0xffd40020, 0, 32, 8, /* INT2PRI8 */ { FLCTL, GPIO, SSI0, SSI1, } },
570 { 0xffd40024, 0, 32, 8, /* INT2PRI9 */ { DU, GDTA, } },
573 static DECLARE_INTC_DESC(intc_desc, "sh7785", vectors, groups,
574 mask_registers, prio_registers, NULL);
576 /* Support for external interrupt pins in IRQ mode */
578 static struct intc_vect vectors_irq0123[] __initdata = {
579 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
580 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
583 static struct intc_vect vectors_irq4567[] __initdata = {
584 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
585 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
588 static struct intc_sense_reg sense_registers[] __initdata = {
589 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
590 IRQ4, IRQ5, IRQ6, IRQ7 } },
593 static struct intc_mask_reg ack_registers[] __initdata = {
594 { 0xffd00024, 0, 32, /* INTREQ */
595 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
598 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7785-irq0123",
599 vectors_irq0123, NULL, mask_registers,
600 prio_registers, sense_registers, ack_registers);
602 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7785-irq4567",
603 vectors_irq4567, NULL, mask_registers,
604 prio_registers, sense_registers, ack_registers);
606 /* External interrupt pins in IRL mode */
608 static struct intc_vect vectors_irl0123[] __initdata = {
609 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
610 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
611 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
612 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
613 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
614 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
615 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
616 INTC_VECT(IRL0_HHHL, 0x3c0),
619 static struct intc_vect vectors_irl4567[] __initdata = {
620 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
621 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
622 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
623 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
624 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
625 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
626 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
627 INTC_VECT(IRL4_HHHL, 0xcc0),
630 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7785-irl0123", vectors_irl0123,
631 NULL, mask_registers, NULL, NULL);
633 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
634 NULL, mask_registers, NULL, NULL);
636 #define INTC_ICR0 0xffd00000
637 #define INTC_INTMSK0 0xffd00044
638 #define INTC_INTMSK1 0xffd00048
639 #define INTC_INTMSK2 0xffd40080
640 #define INTC_INTMSKCLR1 0xffd00068
641 #define INTC_INTMSKCLR2 0xffd40084
643 void __init plat_irq_setup(void)
645 /* disable IRQ3-0 + IRQ7-4 */
646 __raw_writel(0xff000000, INTC_INTMSK0);
648 /* disable IRL3-0 + IRL7-4 */
649 __raw_writel(0xc0000000, INTC_INTMSK1);
650 __raw_writel(0xfffefffe, INTC_INTMSK2);
652 /* select IRL mode for IRL3-0 + IRL7-4 */
653 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
655 /* disable holding function, ie enable "SH-4 Mode" */
656 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
658 register_intc_controller(&intc_desc);
661 void __init plat_irq_setup_pins(int mode)
664 case IRQ_MODE_IRQ7654:
665 /* select IRQ mode for IRL7-4 */
666 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
667 register_intc_controller(&intc_desc_irq4567);
669 case IRQ_MODE_IRQ3210:
670 /* select IRQ mode for IRL3-0 */
671 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
672 register_intc_controller(&intc_desc_irq0123);
674 case IRQ_MODE_IRL7654:
675 /* enable IRL7-4 but don't provide any masking */
676 __raw_writel(0x40000000, INTC_INTMSKCLR1);
677 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
679 case IRQ_MODE_IRL3210:
680 /* enable IRL0-3 but don't provide any masking */
681 __raw_writel(0x80000000, INTC_INTMSKCLR1);
682 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
684 case IRQ_MODE_IRL7654_MASK:
685 /* enable IRL7-4 and mask using cpu intc controller */
686 __raw_writel(0x40000000, INTC_INTMSKCLR1);
687 register_intc_controller(&intc_desc_irl4567);
689 case IRQ_MODE_IRL3210_MASK:
690 /* enable IRL0-3 and mask using cpu intc controller */
691 __raw_writel(0x80000000, INTC_INTMSKCLR1);
692 register_intc_controller(&intc_desc_irl0123);
699 void __init plat_mem_setup(void)
701 /* Register the URAM space as Node 1 */
702 setup_bootmem_node(1, 0xe55f0000, 0xe5610000);