4 * Copyright (C) 2009, 2011 Renesas Solutions Corp.
6 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/platform_device.h>
13 #include <linux/init.h>
14 #include <linux/serial.h>
15 #include <linux/serial_sci.h>
18 #include <linux/sh_timer.h>
19 #include <linux/sh_dma.h>
21 #include <cpu/dma-register.h>
22 #include <cpu/sh7757.h>
24 static struct plat_sci_port scif2_platform_data = {
25 .mapbase = 0xfe4b0000, /* SCIF2 */
26 .flags = UPF_BOOT_AUTOCONF,
27 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
28 .scbrr_algo_id = SCBRR_ALGO_2,
30 .irqs = { 40, 40, 40, 40 },
33 static struct platform_device scif2_device = {
37 .platform_data = &scif2_platform_data,
41 static struct plat_sci_port scif3_platform_data = {
42 .mapbase = 0xfe4c0000, /* SCIF3 */
43 .flags = UPF_BOOT_AUTOCONF,
44 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
45 .scbrr_algo_id = SCBRR_ALGO_2,
47 .irqs = { 76, 76, 76, 76 },
50 static struct platform_device scif3_device = {
54 .platform_data = &scif3_platform_data,
58 static struct plat_sci_port scif4_platform_data = {
59 .mapbase = 0xfe4d0000, /* SCIF4 */
60 .flags = UPF_BOOT_AUTOCONF,
61 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
62 .scbrr_algo_id = SCBRR_ALGO_2,
64 .irqs = { 104, 104, 104, 104 },
67 static struct platform_device scif4_device = {
71 .platform_data = &scif4_platform_data,
75 static struct sh_timer_config tmu0_platform_data = {
76 .channel_offset = 0x04,
78 .clockevent_rating = 200,
81 static struct resource tmu0_resources[] = {
85 .flags = IORESOURCE_MEM,
89 .flags = IORESOURCE_IRQ,
93 static struct platform_device tmu0_device = {
97 .platform_data = &tmu0_platform_data,
99 .resource = tmu0_resources,
100 .num_resources = ARRAY_SIZE(tmu0_resources),
103 static struct sh_timer_config tmu1_platform_data = {
104 .channel_offset = 0x10,
106 .clocksource_rating = 200,
109 static struct resource tmu1_resources[] = {
113 .flags = IORESOURCE_MEM,
117 .flags = IORESOURCE_IRQ,
121 static struct platform_device tmu1_device = {
125 .platform_data = &tmu1_platform_data,
127 .resource = tmu1_resources,
128 .num_resources = ARRAY_SIZE(tmu1_resources),
131 static struct resource spi0_resources[] = {
135 .flags = IORESOURCE_MEM,
139 .flags = IORESOURCE_IRQ,
144 static const struct sh_dmae_slave_config sh7757_dmae0_slaves[] = {
146 .slave_id = SHDMA_SLAVE_SDHI_TX,
148 .chcr = SM_INC | 0x800 | 0x40000000 |
149 TS_INDEX2VAL(XMIT_SZ_16BIT),
153 .slave_id = SHDMA_SLAVE_SDHI_RX,
155 .chcr = DM_INC | 0x800 | 0x40000000 |
156 TS_INDEX2VAL(XMIT_SZ_16BIT),
160 .slave_id = SHDMA_SLAVE_MMCIF_TX,
162 .chcr = SM_INC | 0x800 | 0x40000000 |
163 TS_INDEX2VAL(XMIT_SZ_32BIT),
167 .slave_id = SHDMA_SLAVE_MMCIF_RX,
169 .chcr = DM_INC | 0x800 | 0x40000000 |
170 TS_INDEX2VAL(XMIT_SZ_32BIT),
175 static const struct sh_dmae_slave_config sh7757_dmae1_slaves[] = {
177 .slave_id = SHDMA_SLAVE_SCIF2_TX,
179 .chcr = SM_INC | 0x800 | 0x40000000 |
180 TS_INDEX2VAL(XMIT_SZ_8BIT),
184 .slave_id = SHDMA_SLAVE_SCIF2_RX,
186 .chcr = SM_INC | 0x800 | 0x40000000 |
187 TS_INDEX2VAL(XMIT_SZ_8BIT),
191 .slave_id = SHDMA_SLAVE_SCIF3_TX,
193 .chcr = SM_INC | 0x800 | 0x40000000 |
194 TS_INDEX2VAL(XMIT_SZ_8BIT),
198 .slave_id = SHDMA_SLAVE_SCIF3_RX,
200 .chcr = SM_INC | 0x800 | 0x40000000 |
201 TS_INDEX2VAL(XMIT_SZ_8BIT),
205 .slave_id = SHDMA_SLAVE_SCIF4_TX,
207 .chcr = SM_INC | 0x800 | 0x40000000 |
208 TS_INDEX2VAL(XMIT_SZ_8BIT),
212 .slave_id = SHDMA_SLAVE_SCIF4_RX,
214 .chcr = SM_INC | 0x800 | 0x40000000 |
215 TS_INDEX2VAL(XMIT_SZ_8BIT),
220 static const struct sh_dmae_slave_config sh7757_dmae2_slaves[] = {
222 .slave_id = SHDMA_SLAVE_RIIC0_TX,
224 .chcr = SM_INC | 0x800 | 0x40000000 |
225 TS_INDEX2VAL(XMIT_SZ_8BIT),
229 .slave_id = SHDMA_SLAVE_RIIC0_RX,
231 .chcr = SM_INC | 0x800 | 0x40000000 |
232 TS_INDEX2VAL(XMIT_SZ_8BIT),
236 .slave_id = SHDMA_SLAVE_RIIC1_TX,
238 .chcr = SM_INC | 0x800 | 0x40000000 |
239 TS_INDEX2VAL(XMIT_SZ_8BIT),
243 .slave_id = SHDMA_SLAVE_RIIC1_RX,
245 .chcr = SM_INC | 0x800 | 0x40000000 |
246 TS_INDEX2VAL(XMIT_SZ_8BIT),
250 .slave_id = SHDMA_SLAVE_RIIC2_TX,
252 .chcr = SM_INC | 0x800 | 0x40000000 |
253 TS_INDEX2VAL(XMIT_SZ_8BIT),
257 .slave_id = SHDMA_SLAVE_RIIC2_RX,
259 .chcr = SM_INC | 0x800 | 0x40000000 |
260 TS_INDEX2VAL(XMIT_SZ_8BIT),
264 .slave_id = SHDMA_SLAVE_RIIC3_TX,
266 .chcr = SM_INC | 0x800 | 0x40000000 |
267 TS_INDEX2VAL(XMIT_SZ_8BIT),
271 .slave_id = SHDMA_SLAVE_RIIC3_RX,
273 .chcr = SM_INC | 0x800 | 0x40000000 |
274 TS_INDEX2VAL(XMIT_SZ_8BIT),
278 .slave_id = SHDMA_SLAVE_RIIC4_TX,
280 .chcr = SM_INC | 0x800 | 0x40000000 |
281 TS_INDEX2VAL(XMIT_SZ_8BIT),
285 .slave_id = SHDMA_SLAVE_RIIC4_RX,
287 .chcr = SM_INC | 0x800 | 0x40000000 |
288 TS_INDEX2VAL(XMIT_SZ_8BIT),
293 static const struct sh_dmae_slave_config sh7757_dmae3_slaves[] = {
295 .slave_id = SHDMA_SLAVE_RIIC5_TX,
297 .chcr = SM_INC | 0x800 | 0x40000000 |
298 TS_INDEX2VAL(XMIT_SZ_8BIT),
302 .slave_id = SHDMA_SLAVE_RIIC5_RX,
304 .chcr = SM_INC | 0x800 | 0x40000000 |
305 TS_INDEX2VAL(XMIT_SZ_8BIT),
309 .slave_id = SHDMA_SLAVE_RIIC6_TX,
311 .chcr = SM_INC | 0x800 | 0x40000000 |
312 TS_INDEX2VAL(XMIT_SZ_8BIT),
316 .slave_id = SHDMA_SLAVE_RIIC6_RX,
318 .chcr = SM_INC | 0x800 | 0x40000000 |
319 TS_INDEX2VAL(XMIT_SZ_8BIT),
323 .slave_id = SHDMA_SLAVE_RIIC7_TX,
325 .chcr = SM_INC | 0x800 | 0x40000000 |
326 TS_INDEX2VAL(XMIT_SZ_8BIT),
330 .slave_id = SHDMA_SLAVE_RIIC7_RX,
332 .chcr = SM_INC | 0x800 | 0x40000000 |
333 TS_INDEX2VAL(XMIT_SZ_8BIT),
337 .slave_id = SHDMA_SLAVE_RIIC8_TX,
339 .chcr = SM_INC | 0x800 | 0x40000000 |
340 TS_INDEX2VAL(XMIT_SZ_8BIT),
344 .slave_id = SHDMA_SLAVE_RIIC8_RX,
346 .chcr = SM_INC | 0x800 | 0x40000000 |
347 TS_INDEX2VAL(XMIT_SZ_8BIT),
351 .slave_id = SHDMA_SLAVE_RIIC9_TX,
353 .chcr = SM_INC | 0x800 | 0x40000000 |
354 TS_INDEX2VAL(XMIT_SZ_8BIT),
358 .slave_id = SHDMA_SLAVE_RIIC9_RX,
360 .chcr = SM_INC | 0x800 | 0x40000000 |
361 TS_INDEX2VAL(XMIT_SZ_8BIT),
366 static const struct sh_dmae_channel sh7757_dmae_channels[] = {
394 static const unsigned int ts_shift[] = TS_SHIFT;
396 static struct sh_dmae_pdata dma0_platform_data = {
397 .slave = sh7757_dmae0_slaves,
398 .slave_num = ARRAY_SIZE(sh7757_dmae0_slaves),
399 .channel = sh7757_dmae_channels,
400 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
401 .ts_low_shift = CHCR_TS_LOW_SHIFT,
402 .ts_low_mask = CHCR_TS_LOW_MASK,
403 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
404 .ts_high_mask = CHCR_TS_HIGH_MASK,
405 .ts_shift = ts_shift,
406 .ts_shift_num = ARRAY_SIZE(ts_shift),
407 .dmaor_init = DMAOR_INIT,
410 static struct sh_dmae_pdata dma1_platform_data = {
411 .slave = sh7757_dmae1_slaves,
412 .slave_num = ARRAY_SIZE(sh7757_dmae1_slaves),
413 .channel = sh7757_dmae_channels,
414 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
415 .ts_low_shift = CHCR_TS_LOW_SHIFT,
416 .ts_low_mask = CHCR_TS_LOW_MASK,
417 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
418 .ts_high_mask = CHCR_TS_HIGH_MASK,
419 .ts_shift = ts_shift,
420 .ts_shift_num = ARRAY_SIZE(ts_shift),
421 .dmaor_init = DMAOR_INIT,
424 static struct sh_dmae_pdata dma2_platform_data = {
425 .slave = sh7757_dmae2_slaves,
426 .slave_num = ARRAY_SIZE(sh7757_dmae2_slaves),
427 .channel = sh7757_dmae_channels,
428 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
429 .ts_low_shift = CHCR_TS_LOW_SHIFT,
430 .ts_low_mask = CHCR_TS_LOW_MASK,
431 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
432 .ts_high_mask = CHCR_TS_HIGH_MASK,
433 .ts_shift = ts_shift,
434 .ts_shift_num = ARRAY_SIZE(ts_shift),
435 .dmaor_init = DMAOR_INIT,
438 static struct sh_dmae_pdata dma3_platform_data = {
439 .slave = sh7757_dmae3_slaves,
440 .slave_num = ARRAY_SIZE(sh7757_dmae3_slaves),
441 .channel = sh7757_dmae_channels,
442 .channel_num = ARRAY_SIZE(sh7757_dmae_channels),
443 .ts_low_shift = CHCR_TS_LOW_SHIFT,
444 .ts_low_mask = CHCR_TS_LOW_MASK,
445 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
446 .ts_high_mask = CHCR_TS_HIGH_MASK,
447 .ts_shift = ts_shift,
448 .ts_shift_num = ARRAY_SIZE(ts_shift),
449 .dmaor_init = DMAOR_INIT,
453 static struct resource sh7757_dmae0_resources[] = {
455 /* Channel registers and DMAOR */
458 .flags = IORESOURCE_MEM,
464 .flags = IORESOURCE_MEM,
469 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
473 /* channel 6 to 11 */
474 static struct resource sh7757_dmae1_resources[] = {
476 /* Channel registers and DMAOR */
479 .flags = IORESOURCE_MEM,
485 .flags = IORESOURCE_MEM,
491 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
494 /* IRQ for channels 4 */
497 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
500 /* IRQ for channels 5 */
503 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
506 /* IRQ for channels 6 */
509 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
512 /* IRQ for channels 7 */
515 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
518 /* IRQ for channels 8 */
521 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
524 /* IRQ for channels 9 */
527 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
530 /* IRQ for channels 10 */
533 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
536 /* IRQ for channels 11 */
539 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
543 /* channel 12 to 17 */
544 static struct resource sh7757_dmae2_resources[] = {
546 /* Channel registers and DMAOR */
549 .flags = IORESOURCE_MEM,
555 .flags = IORESOURCE_MEM,
561 .flags = IORESOURCE_IRQ,
564 /* IRQ for channels 12 to 16 */
567 .flags = IORESOURCE_IRQ,
570 /* IRQ for channel 17 */
573 .flags = IORESOURCE_IRQ,
577 /* channel 18 to 23 */
578 static struct resource sh7757_dmae3_resources[] = {
580 /* Channel registers and DMAOR */
583 .flags = IORESOURCE_MEM,
589 .flags = IORESOURCE_MEM,
595 .flags = IORESOURCE_IRQ,
598 /* IRQ for channels 18 to 22 */
601 .flags = IORESOURCE_IRQ,
604 /* IRQ for channel 23 */
607 .flags = IORESOURCE_IRQ,
611 static struct platform_device dma0_device = {
612 .name = "sh-dma-engine",
614 .resource = sh7757_dmae0_resources,
615 .num_resources = ARRAY_SIZE(sh7757_dmae0_resources),
617 .platform_data = &dma0_platform_data,
621 static struct platform_device dma1_device = {
622 .name = "sh-dma-engine",
624 .resource = sh7757_dmae1_resources,
625 .num_resources = ARRAY_SIZE(sh7757_dmae1_resources),
627 .platform_data = &dma1_platform_data,
631 static struct platform_device dma2_device = {
632 .name = "sh-dma-engine",
634 .resource = sh7757_dmae2_resources,
635 .num_resources = ARRAY_SIZE(sh7757_dmae2_resources),
637 .platform_data = &dma2_platform_data,
641 static struct platform_device dma3_device = {
642 .name = "sh-dma-engine",
644 .resource = sh7757_dmae3_resources,
645 .num_resources = ARRAY_SIZE(sh7757_dmae3_resources),
647 .platform_data = &dma3_platform_data,
651 static struct platform_device spi0_device = {
656 .coherent_dma_mask = 0xffffffff,
658 .num_resources = ARRAY_SIZE(spi0_resources),
659 .resource = spi0_resources,
662 static struct platform_device *sh7757_devices[] __initdata = {
675 static int __init sh7757_devices_setup(void)
677 return platform_add_devices(sh7757_devices,
678 ARRAY_SIZE(sh7757_devices));
680 arch_initcall(sh7757_devices_setup);
682 static struct platform_device *sh7757_early_devices[] __initdata = {
690 void __init plat_early_device_setup(void)
692 early_platform_add_devices(sh7757_early_devices,
693 ARRAY_SIZE(sh7757_early_devices));
699 /* interrupt sources */
701 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
702 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
703 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
704 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
706 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
707 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
708 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
709 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
710 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
713 IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15,
714 TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
717 DMAC0_5, DMAC6_7, DMAC8_11,
718 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4,
724 LPC, LPC5, LPC6, LPC7, LPC8,
725 PECI0, PECI1, PECI2, PECI3, PECI4, PECI5,
729 IIC0_0, IIC0_1, IIC0_2, IIC0_3,
730 IIC1_0, IIC1_1, IIC1_2, IIC1_3,
731 IIC2_0, IIC2_1, IIC2_2, IIC2_3,
732 IIC3_0, IIC3_1, IIC3_2, IIC3_3,
733 IIC4_0, IIC4_1, IIC4_2, IIC4_3,
734 IIC5_0, IIC5_1, IIC5_2, IIC5_3,
735 IIC6_0, IIC6_1, IIC6_2, IIC6_3,
736 IIC7_0, IIC7_1, IIC7_2, IIC7_3,
737 IIC8_0, IIC8_1, IIC8_2, IIC8_3,
738 IIC9_0, IIC9_1, IIC9_2, IIC9_3,
746 DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19,
747 DMINT20, DMINT21, DMINT22, DMINT23,
751 WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B,
752 GETHER0, GETHER1, GETHER2,
757 /* interrupt groups */
762 static struct intc_vect vectors[] __initdata = {
763 INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
764 INTC_VECT(SDHI, 0x4c0),
765 INTC_VECT(DVC, 0x4e0),
766 INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
767 INTC_VECT(IRQ10, 0x540),
768 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
769 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
770 INTC_VECT(HUDI, 0x600),
771 INTC_VECT(ARC4, 0x620),
772 INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660),
773 INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0),
774 INTC_VECT(DMAC0_5, 0x6c0),
775 INTC_VECT(IRQ11, 0x6e0),
776 INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
777 INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
778 INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0),
779 INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0),
780 INTC_VECT(USB0, 0x840),
781 INTC_VECT(IRQ12, 0x880),
782 INTC_VECT(JMC, 0x8a0),
783 INTC_VECT(SPI1, 0x8c0),
784 INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
785 INTC_VECT(USB1, 0x920),
786 INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
787 INTC_VECT(TMR45, 0xa40),
788 INTC_VECT(FRT, 0xa80),
789 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
790 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
791 INTC_VECT(LPC, 0xb20),
792 INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
793 INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
794 INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
795 INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20),
796 INTC_VECT(PECI2, 0xc40),
797 INTC_VECT(IRQ15, 0xc60),
798 INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
799 INTC_VECT(SPI0, 0xcc0),
800 INTC_VECT(ADC1, 0xce0),
801 INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20),
802 INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60),
803 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
804 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
805 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
806 INTC_VECT(TMU5, 0xe40),
807 INTC_VECT(ADC0, 0xe60),
808 INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
809 INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
810 INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
811 INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
812 INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
813 INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
814 INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
815 INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
816 INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
817 INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
818 INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
819 INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
820 INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
821 INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
822 INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
823 INTC_VECT(IIC6_2, 0x1920),
824 INTC_VECT(ONFICTL, 0x1960),
825 INTC_VECT(IIC6_3, 0x1980),
826 INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
827 INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
828 INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
829 INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
830 INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
831 INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
832 INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80),
833 INTC_VECT(ECCU, 0x1cc0),
834 INTC_VECT(PCIC, 0x1ce0),
835 INTC_VECT(G200, 0x1d00),
836 INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0),
837 INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0),
838 INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0),
839 INTC_VECT(PECI5, 0x1f00),
840 INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0),
841 INTC_VECT(SGPIO, 0x1fc0),
842 INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420),
843 INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460),
844 INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0),
845 INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520),
846 INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560),
847 INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600),
848 INTC_VECT(DDRECC, 0x2620),
849 INTC_VECT(TSIP, 0x2640),
850 INTC_VECT(PCIE_BRIDGE, 0x27c0),
851 INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820),
852 INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860),
853 INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0),
854 INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0),
855 INTC_VECT(WDT8B, 0x2900),
856 INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980),
857 INTC_VECT(GETHER2, 0x29a0),
858 INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20),
859 INTC_VECT(PBIC, 0x2a40),
860 INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80),
861 INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40),
862 INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80),
863 INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20),
866 static struct intc_group groups[] __initdata = {
867 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
868 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
871 static struct intc_mask_reg mask_registers[] __initdata = {
872 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
873 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
875 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
876 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
877 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
878 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
879 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
880 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
881 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
882 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
883 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
885 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
886 { 0, 0, 0, 0, 0, 0, 0, 0,
887 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
888 TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5,
889 HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012
892 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
893 { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
894 IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
895 ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1,
896 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
899 { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
900 { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0,
901 0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
902 IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
903 IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2
906 { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */
907 { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2,
908 IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
909 PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3,
910 IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
913 { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */
914 { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0,
915 0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC,
916 PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP,
917 DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22
920 { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */
921 { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0,
922 DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0,
923 0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8,
924 DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17
928 #define INTPRI 0xffd00010
929 #define INT2PRI0 0xffd40000
930 #define INT2PRI1 0xffd40004
931 #define INT2PRI2 0xffd40008
932 #define INT2PRI3 0xffd4000c
933 #define INT2PRI4 0xffd40010
934 #define INT2PRI5 0xffd40014
935 #define INT2PRI6 0xffd40018
936 #define INT2PRI7 0xffd4001c
937 #define INT2PRI8 0xffd400a0
938 #define INT2PRI9 0xffd400a4
939 #define INT2PRI10 0xffd400a8
940 #define INT2PRI11 0xffd400ac
941 #define INT2PRI12 0xffd400b0
942 #define INT2PRI13 0xffd400b4
943 #define INT2PRI14 0xffd400b8
944 #define INT2PRI15 0xffd400bc
945 #define INT2PRI16 0xffd10000
946 #define INT2PRI17 0xffd10004
947 #define INT2PRI18 0xffd10008
948 #define INT2PRI19 0xffd1000c
949 #define INT2PRI20 0xffd10010
950 #define INT2PRI21 0xffd10014
951 #define INT2PRI22 0xffd10018
952 #define INT2PRI23 0xffd1001c
953 #define INT2PRI24 0xffd100a0
954 #define INT2PRI25 0xffd100a4
955 #define INT2PRI26 0xffd100a8
956 #define INT2PRI27 0xffd100ac
957 #define INT2PRI28 0xffd100b0
958 #define INT2PRI29 0xffd100b4
959 #define INT2PRI30 0xffd100b8
960 #define INT2PRI31 0xffd100bc
961 #define INT2PRI32 0xffd20000
962 #define INT2PRI33 0xffd20004
963 #define INT2PRI34 0xffd20008
964 #define INT2PRI35 0xffd2000c
965 #define INT2PRI36 0xffd20010
966 #define INT2PRI37 0xffd20014
967 #define INT2PRI38 0xffd20018
968 #define INT2PRI39 0xffd2001c
969 #define INT2PRI40 0xffd200a0
970 #define INT2PRI41 0xffd200a4
971 #define INT2PRI42 0xffd200a8
972 #define INT2PRI43 0xffd200ac
973 #define INT2PRI44 0xffd200b0
974 #define INT2PRI45 0xffd200b4
975 #define INT2PRI46 0xffd200b8
976 #define INT2PRI47 0xffd200bc
978 static struct intc_prio_reg prio_registers[] __initdata = {
979 { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
980 IRQ4, IRQ5, IRQ6, IRQ7 } },
982 { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
983 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
984 { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } },
985 { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } },
986 { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
987 { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
988 { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } },
989 { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
990 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
991 { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
992 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } },
993 { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } },
994 { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
995 { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
997 { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
998 { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } },
999 { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
1000 { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
1001 { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
1002 { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
1003 { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } },
1004 { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } },
1005 { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } },
1006 { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
1007 { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } },
1008 { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } },
1009 { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } },
1010 { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
1011 { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } },
1012 { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
1013 { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } },
1014 { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } },
1015 { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } },
1016 { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } },
1017 { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } },
1018 { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } },
1019 { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } },
1020 { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } },
1021 { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } },
1022 { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } },
1023 { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } },
1024 { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } },
1025 { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } },
1026 { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } },
1027 { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } },
1028 { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } },
1031 static struct intc_sense_reg sense_registers_irq8to15[] __initdata = {
1032 { 0xffd100f8, 32, 2, /* ICR2 */ { IRQ15, IRQ14, IRQ13, IRQ12,
1033 IRQ11, IRQ10, IRQ9, IRQ8 } },
1036 static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
1037 mask_registers, prio_registers,
1038 sense_registers_irq8to15);
1040 /* Support for external interrupt pins in IRQ mode */
1041 static struct intc_vect vectors_irq0123[] __initdata = {
1042 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
1043 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
1046 static struct intc_vect vectors_irq4567[] __initdata = {
1047 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
1048 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
1051 static struct intc_sense_reg sense_registers[] __initdata = {
1052 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
1053 IRQ4, IRQ5, IRQ6, IRQ7 } },
1056 static struct intc_mask_reg ack_registers[] __initdata = {
1057 { 0xffd00024, 0, 32, /* INTREQ */
1058 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1061 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
1062 vectors_irq0123, NULL, mask_registers,
1063 prio_registers, sense_registers, ack_registers);
1065 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
1066 vectors_irq4567, NULL, mask_registers,
1067 prio_registers, sense_registers, ack_registers);
1069 /* External interrupt pins in IRL mode */
1070 static struct intc_vect vectors_irl0123[] __initdata = {
1071 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
1072 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
1073 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
1074 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
1075 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
1076 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
1077 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
1078 INTC_VECT(IRL0_HHHL, 0x3c0),
1081 static struct intc_vect vectors_irl4567[] __initdata = {
1082 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
1083 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
1084 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
1085 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
1086 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
1087 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
1088 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
1089 INTC_VECT(IRL4_HHHL, 0xcc0),
1092 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
1093 NULL, mask_registers, NULL, NULL);
1095 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
1096 NULL, mask_registers, NULL, NULL);
1098 #define INTC_ICR0 0xffd00000
1099 #define INTC_INTMSK0 0xffd00044
1100 #define INTC_INTMSK1 0xffd00048
1101 #define INTC_INTMSK2 0xffd40080
1102 #define INTC_INTMSKCLR1 0xffd00068
1103 #define INTC_INTMSKCLR2 0xffd40084
1105 void __init plat_irq_setup(void)
1107 /* disable IRQ3-0 + IRQ7-4 */
1108 __raw_writel(0xff000000, INTC_INTMSK0);
1110 /* disable IRL3-0 + IRL7-4 */
1111 __raw_writel(0xc0000000, INTC_INTMSK1);
1112 __raw_writel(0xfffefffe, INTC_INTMSK2);
1114 /* select IRL mode for IRL3-0 + IRL7-4 */
1115 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
1117 /* disable holding function, ie enable "SH-4 Mode" */
1118 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
1120 register_intc_controller(&intc_desc);
1123 void __init plat_irq_setup_pins(int mode)
1126 case IRQ_MODE_IRQ7654:
1127 /* select IRQ mode for IRL7-4 */
1128 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
1129 register_intc_controller(&intc_desc_irq4567);
1131 case IRQ_MODE_IRQ3210:
1132 /* select IRQ mode for IRL3-0 */
1133 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
1134 register_intc_controller(&intc_desc_irq0123);
1136 case IRQ_MODE_IRL7654:
1137 /* enable IRL7-4 but don't provide any masking */
1138 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1139 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
1141 case IRQ_MODE_IRL3210:
1142 /* enable IRL0-3 but don't provide any masking */
1143 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1144 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
1146 case IRQ_MODE_IRL7654_MASK:
1147 /* enable IRL7-4 and mask using cpu intc controller */
1148 __raw_writel(0x40000000, INTC_INTMSKCLR1);
1149 register_intc_controller(&intc_desc_irl4567);
1151 case IRQ_MODE_IRL3210_MASK:
1152 /* enable IRL0-3 and mask using cpu intc controller */
1153 __raw_writel(0x80000000, INTC_INTMSKCLR1);
1154 register_intc_controller(&intc_desc_irl0123);
1161 void __init plat_mem_setup(void)