arch/sh/kernel/cpu/sh4a/setup-sh7757.c

   1 /*
   2  * SH7757 Setup
   3  *
   4  * Copyright (C) 2009  Renesas Solutions Corp.
   5  *
   6  *  based on setup-sh7785.c : Copyright (C) 2007  Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/platform_device.h>
  13 #include <linux/init.h>
  14 #include <linux/serial.h>
  15 #include <linux/serial_sci.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/sh_timer.h>
  19
  20 static struct sh_timer_config tmu0_platform_data = {
  21         .name = "TMU0",
  22         .channel_offset = 0x04,
  23         .timer_bit = 0,
  24         .clk = "peripheral_clk",
  25         .clockevent_rating = 200,
  26 };
  27
  28 static struct resource tmu0_resources[] = {
  29         [0] = {
  30                 .name   = "TMU0",
  31                 .start  = 0xfe430008,
  32                 .end    = 0xfe430013,
  33                 .flags  = IORESOURCE_MEM,
  34         },
  35         [1] = {
  36                 .start  = 28,
  37                 .flags  = IORESOURCE_IRQ,
  38         },
  39 };
  40
  41 static struct platform_device tmu0_device = {
  42         .name           = "sh_tmu",
  43         .id             = 0,
  44         .dev = {
  45                 .platform_data  = &tmu0_platform_data,
  46         },
  47         .resource       = tmu0_resources,
  48         .num_resources  = ARRAY_SIZE(tmu0_resources),
  49 };
  50
  51 static struct sh_timer_config tmu1_platform_data = {
  52         .name = "TMU1",
  53         .channel_offset = 0x10,
  54         .timer_bit = 1,
  55         .clk = "peripheral_clk",
  56         .clocksource_rating = 200,
  57 };
  58
  59 static struct resource tmu1_resources[] = {
  60         [0] = {
  61                 .name   = "TMU1",
  62                 .start  = 0xfe430014,
  63                 .end    = 0xfe43001f,
  64                 .flags  = IORESOURCE_MEM,
  65         },
  66         [1] = {
  67                 .start  = 29,
  68                 .flags  = IORESOURCE_IRQ,
  69         },
  70 };
  71
  72 static struct platform_device tmu1_device = {
  73         .name           = "sh_tmu",
  74         .id             = 1,
  75         .dev = {
  76                 .platform_data  = &tmu1_platform_data,
  77         },
  78         .resource       = tmu1_resources,
  79         .num_resources  = ARRAY_SIZE(tmu1_resources),
  80 };
  81
  82 static struct plat_sci_port sci_platform_data[] = {
  83         {
  84                 .mapbase        = 0xfe4b0000,           /* SCIF2 */
  85                 .flags          = UPF_BOOT_AUTOCONF,
  86                 .type           = PORT_SCIF,
  87                 .irqs           = { 40, 40, 40, 40 },
  88         }, {
  89                 .mapbase        = 0xfe4c0000,           /* SCIF3 */
  90                 .flags          = UPF_BOOT_AUTOCONF,
  91                 .type           = PORT_SCIF,
  92                 .irqs           = { 76, 76, 76, 76 },
  93         }, {
  94                 .mapbase        = 0xfe4d0000,           /* SCIF4 */
  95                 .flags          = UPF_BOOT_AUTOCONF,
  96                 .type           = PORT_SCIF,
  97                 .irqs           = { 104, 104, 104, 104 },
  98         }, {
  99                 .flags = 0,
 100         }
 101 };
 102
 103 static struct platform_device sci_device = {
 104         .name           = "sh-sci",
 105         .id             = -1,
 106         .dev            = {
 107                 .platform_data  = sci_platform_data,
 108         },
 109 };
 110
 111 static struct platform_device *sh7757_devices[] __initdata = {
 112         &tmu0_device,
 113         &tmu1_device,
 114         &sci_device,
 115 };
 116
 117 static int __init sh7757_devices_setup(void)
 118 {
 119         return platform_add_devices(sh7757_devices,
 120                                     ARRAY_SIZE(sh7757_devices));
 121 }
 122 arch_initcall(sh7757_devices_setup);
 123
 124 enum {
 125         UNUSED = 0,
 126
 127         /* interrupt sources */
 128
 129         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 130         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 131         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 132         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 133
 134         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 135         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 136         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 137         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 138         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 139
 140         SDHI,
 141         DVC,
 142         IRQ8, IRQ9, IRQ10,
 143         WDT0,
 144         TMU0, TMU1, TMU2, TMU2_TICPI,
 145         HUDI,
 146
 147         ARC4,
 148         DMAC0,
 149         IRQ11,
 150         SCIF2,
 151         DMAC1_6,
 152         USB0,
 153         IRQ12,
 154         JMC,
 155         SPI1,
 156         IRQ13, IRQ14,
 157         USB1,
 158         TMR01, TMR23, TMR45,
 159         WDT1,
 160         FRT,
 161         LPC,
 162         SCIF0, SCIF1, SCIF3,
 163         PECI0I, PECI1I, PECI2I,
 164         IRQ15,
 165         ETHERC,
 166         SPI0,
 167         ADC1,
 168         DMAC1_8,
 169         SIM,
 170         TMU3, TMU4, TMU5,
 171         ADC0,
 172         SCIF4,
 173         IIC0_0, IIC0_1, IIC0_2, IIC0_3,
 174         IIC1_0, IIC1_1, IIC1_2, IIC1_3,
 175         IIC2_0, IIC2_1, IIC2_2, IIC2_3,
 176         IIC3_0, IIC3_1, IIC3_2, IIC3_3,
 177         IIC4_0, IIC4_1, IIC4_2, IIC4_3,
 178         IIC5_0, IIC5_1, IIC5_2, IIC5_3,
 179         IIC6_0, IIC6_1, IIC6_2, IIC6_3,
 180         IIC7_0, IIC7_1, IIC7_2, IIC7_3,
 181         IIC8_0, IIC8_1, IIC8_2, IIC8_3,
 182         IIC9_0, IIC9_1, IIC9_2, IIC9_3,
 183         PCIINTA,
 184         PCIE,
 185         SGPIO,
 186
 187         /* interrupt groups */
 188
 189         TMU012, TMU345,
 190 };
 191
 192 static struct intc_vect vectors[] __initdata = {
 193         INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
 194         INTC_VECT(SDHI, 0x4c0),
 195         INTC_VECT(DVC, 0x4e0),
 196         INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
 197         INTC_VECT(IRQ10, 0x540),
 198         INTC_VECT(WDT0, 0x560),
 199         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 200         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 201         INTC_VECT(HUDI, 0x600),
 202         INTC_VECT(ARC4, 0x620),
 203         INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
 204         INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
 205         INTC_VECT(DMAC0, 0x6c0),
 206         INTC_VECT(IRQ11, 0x6e0),
 207         INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
 208         INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
 209         INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
 210         INTC_VECT(DMAC1_6, 0x7c0), INTC_VECT(DMAC1_6, 0x7e0),
 211         INTC_VECT(USB0, 0x840),
 212         INTC_VECT(IRQ12, 0x880),
 213         INTC_VECT(JMC, 0x8a0),
 214         INTC_VECT(SPI1, 0x8c0),
 215         INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
 216         INTC_VECT(USB1, 0x920),
 217         INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
 218         INTC_VECT(TMR45, 0xa40),
 219         INTC_VECT(WDT1, 0xa60),
 220         INTC_VECT(FRT, 0xa80),
 221         INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
 222         INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
 223         INTC_VECT(LPC, 0xb20),
 224         INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
 225         INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
 226         INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
 227         INTC_VECT(PECI0I, 0xc00), INTC_VECT(PECI1I, 0xc20),
 228         INTC_VECT(PECI2I, 0xc40),
 229         INTC_VECT(IRQ15, 0xc60),
 230         INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
 231         INTC_VECT(SPI0, 0xcc0),
 232         INTC_VECT(ADC1, 0xce0),
 233         INTC_VECT(DMAC1_8, 0xd00), INTC_VECT(DMAC1_8, 0xd20),
 234         INTC_VECT(DMAC1_8, 0xd40), INTC_VECT(DMAC1_8, 0xd60),
 235         INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
 236         INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
 237         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 238         INTC_VECT(TMU5, 0xe40),
 239         INTC_VECT(ADC0, 0xe60),
 240         INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
 241         INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
 242         INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
 243         INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
 244         INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
 245         INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
 246         INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
 247         INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
 248         INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
 249         INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
 250         INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
 251         INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
 252         INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
 253         INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
 254         INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
 255         INTC_VECT(IIC6_2, 0x1920), INTC_VECT(IIC6_3, 0x1980),
 256         INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
 257         INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
 258         INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
 259         INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
 260         INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
 261         INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
 262         INTC_VECT(PCIINTA, 0x1ce0),
 263         INTC_VECT(PCIE, 0x1e00),
 264         INTC_VECT(SGPIO, 0x1f80),
 265         INTC_VECT(SGPIO, 0x1fa0),
 266 };
 267
 268 static struct intc_group groups[] __initdata = {
 269         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 270         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 271 };
 272
 273 static struct intc_mask_reg mask_registers[] __initdata = {
 274         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 275           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 276
 277         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 278           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 279             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 280             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 281             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 282             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 283             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 284             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 285             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 286
 287         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 288           { 0, 0, 0, 0, 0, 0, 0, 0,
 289             0, DMAC1_8, 0, PECI0I, LPC, FRT, WDT1, TMR45,
 290             TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0,
 291             HUDI, 0, WDT0, SCIF3, SCIF2, SDHI, TMU345, TMU012
 292              } },
 293
 294         { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
 295           { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
 296             IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
 297             ADC1, 0, DMAC1_6, ADC0, SPI0, SIM, PECI2I, PECI1I,
 298             ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
 299              } },
 300
 301         { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
 302           { IIC4_1, IIC4_2, IIC5_0, 0, 0, 0, SGPIO, 0,
 303             0, 0, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
 304             IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
 305             IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, PCIE, IIC2_2
 306              } },
 307
 308         { 0xffd100d0, 0xff1400d4, 32, /* INT2MSKR3 / INT2MSKCR4 */
 309           { 0, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, 0, 0,
 310             IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
 311             PCIINTA, 0, IIC4_0, 0, 0, 0, 0, IIC9_3,
 312             IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
 313              } },
 314 };
 315
 316 #define INTPRI          0xffd00010
 317 #define INT2PRI0        0xffd40000
 318 #define INT2PRI1        0xffd40004
 319 #define INT2PRI2        0xffd40008
 320 #define INT2PRI3        0xffd4000c
 321 #define INT2PRI4        0xffd40010
 322 #define INT2PRI5        0xffd40014
 323 #define INT2PRI6        0xffd40018
 324 #define INT2PRI7        0xffd4001c
 325 #define INT2PRI8        0xffd400a0
 326 #define INT2PRI9        0xffd400a4
 327 #define INT2PRI10       0xffd400a8
 328 #define INT2PRI11       0xffd400ac
 329 #define INT2PRI12       0xffd400b0
 330 #define INT2PRI13       0xffd400b4
 331 #define INT2PRI14       0xffd400b8
 332 #define INT2PRI15       0xffd400bc
 333 #define INT2PRI16       0xffd10000
 334 #define INT2PRI17       0xffd10004
 335 #define INT2PRI18       0xffd10008
 336 #define INT2PRI19       0xffd1000c
 337 #define INT2PRI20       0xffd10010
 338 #define INT2PRI21       0xffd10014
 339 #define INT2PRI22       0xffd10018
 340 #define INT2PRI23       0xffd1001c
 341 #define INT2PRI24       0xffd100a0
 342 #define INT2PRI25       0xffd100a4
 343 #define INT2PRI26       0xffd100a8
 344 #define INT2PRI27       0xffd100ac
 345 #define INT2PRI28       0xffd100b0
 346 #define INT2PRI29       0xffd100b4
 347 #define INT2PRI30       0xffd100b8
 348 #define INT2PRI31       0xffd100bc
 349
 350 static struct intc_prio_reg prio_registers[] __initdata = {
 351         { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
 352                               IRQ4, IRQ5, IRQ6, IRQ7 } },
 353
 354         { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
 355         { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
 356         { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, WDT0, IRQ8 } },
 357         { INT2PRI3, 0, 32, 8, { HUDI, DMAC0, ADC0, IRQ9 } },
 358         { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
 359         { INT2PRI5, 0, 32, 8, { TMR45, WDT1, FRT, LPC } },
 360         { INT2PRI6, 0, 32, 8, { PECI0I, ETHERC, DMAC1_8, 0 } },
 361         { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
 362         { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
 363         { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
 364         { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2I, PECI1I } },
 365         { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC1_6, IRQ14 } },
 366         { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
 367         { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
 368
 369         { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
 370         { INT2PRI17, 0, 32, 8, { PCIE, 0, 0, IIC1_0 } },
 371         { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
 372         { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
 373         { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
 374         { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
 375         { INT2PRI22, 0, 32, 8, { IIC9_2, 0, 0, 0 } },
 376         { INT2PRI23, 0, 32, 8, { 0, SGPIO, IIC3_2, IIC5_1 } },
 377         { INT2PRI24, 0, 32, 8, { 0, 0, 0, IIC1_1 } },
 378         { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
 379         { INT2PRI26, 0, 32, 8, { 0, 0, 0, IIC9_3 } },
 380         { INT2PRI27, 0, 32, 8, { PCIINTA, IIC6_0, IIC4_0, IIC6_1 } },
 381         { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, 0, IIC6_2 } },
 382         { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
 383         { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, 0 } },
 384         { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
 385 };
 386
 387 static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
 388                          mask_registers, prio_registers, NULL);
 389
 390 /* Support for external interrupt pins in IRQ mode */
 391 static struct intc_vect vectors_irq0123[] __initdata = {
 392         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 393         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 394 };
 395
 396 static struct intc_vect vectors_irq4567[] __initdata = {
 397         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 398         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 399 };
 400
 401 static struct intc_sense_reg sense_registers[] __initdata = {
 402         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 403                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 404 };
 405
 406 static struct intc_mask_reg ack_registers[] __initdata = {
 407         { 0xffd00024, 0, 32, /* INTREQ */
 408           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 409 };
 410
 411 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
 412                              vectors_irq0123, NULL, mask_registers,
 413                              prio_registers, sense_registers, ack_registers);
 414
 415 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
 416                              vectors_irq4567, NULL, mask_registers,
 417                              prio_registers, sense_registers, ack_registers);
 418
 419 /* External interrupt pins in IRL mode */
 420 static struct intc_vect vectors_irl0123[] __initdata = {
 421         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 422         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 423         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 424         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 425         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 426         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 427         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 428         INTC_VECT(IRL0_HHHL, 0x3c0),
 429 };
 430
 431 static struct intc_vect vectors_irl4567[] __initdata = {
 432         INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
 433         INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
 434         INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
 435         INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
 436         INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
 437         INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
 438         INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
 439         INTC_VECT(IRL4_HHHL, 0xcc0),
 440 };
 441
 442 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
 443                          NULL, mask_registers, NULL, NULL);
 444
 445 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
 446                          NULL, mask_registers, NULL, NULL);
 447
 448 #define INTC_ICR0       0xffd00000
 449 #define INTC_INTMSK0    0xffd00044
 450 #define INTC_INTMSK1    0xffd00048
 451 #define INTC_INTMSK2    0xffd40080
 452 #define INTC_INTMSKCLR1 0xffd00068
 453 #define INTC_INTMSKCLR2 0xffd40084
 454
 455 void __init plat_irq_setup(void)
 456 {
 457         /* disable IRQ3-0 + IRQ7-4 */
 458         ctrl_outl(0xff000000, INTC_INTMSK0);
 459
 460         /* disable IRL3-0 + IRL7-4 */
 461         ctrl_outl(0xc0000000, INTC_INTMSK1);
 462         ctrl_outl(0xfffefffe, INTC_INTMSK2);
 463
 464         /* select IRL mode for IRL3-0 + IRL7-4 */
 465         ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 466
 467         /* disable holding function, ie enable "SH-4 Mode" */
 468         ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 469
 470         register_intc_controller(&intc_desc);
 471 }
 472
 473 void __init plat_irq_setup_pins(int mode)
 474 {
 475         switch (mode) {
 476         case IRQ_MODE_IRQ7654:
 477                 /* select IRQ mode for IRL7-4 */
 478                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 479                 register_intc_controller(&intc_desc_irq4567);
 480                 break;
 481         case IRQ_MODE_IRQ3210:
 482                 /* select IRQ mode for IRL3-0 */
 483                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 484                 register_intc_controller(&intc_desc_irq0123);
 485                 break;
 486         case IRQ_MODE_IRL7654:
 487                 /* enable IRL7-4 but don't provide any masking */
 488                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 489                 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
 490                 break;
 491         case IRQ_MODE_IRL3210:
 492                 /* enable IRL0-3 but don't provide any masking */
 493                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 494                 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
 495                 break;
 496         case IRQ_MODE_IRL7654_MASK:
 497                 /* enable IRL7-4 and mask using cpu intc controller */
 498                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 499                 register_intc_controller(&intc_desc_irl4567);
 500                 break;
 501         case IRQ_MODE_IRL3210_MASK:
 502                 /* enable IRL0-3 and mask using cpu intc controller */
 503                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 504                 register_intc_controller(&intc_desc_irl0123);
 505                 break;
 506         default:
 507                 BUG();
 508         }
 509 }
 510
 511 void __init plat_mem_setup(void)
 512 {
 513 }