arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c

   1 /*
   2  * SH7786 Pinmux
   3  *
   4  * Copyright (C) 2008, 2009  Renesas Solutions Corp.
   5  * Kuninori Morimoto <morimoto.kuninori@renesas.com>
   6  *
   7  *  Based on SH7785 pinmux
   8  *
   9  *  Copyright (C) 2008  Magnus Damm
  10  *
  11  * This file is subject to the terms and conditions of the GNU General Public
  12  * License.  See the file "COPYING" in the main directory of this archive
  13  * for more details.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/kernel.h>
  18 #include <linux/gpio.h>
  19 #include <cpu/sh7786.h>
  20
  21 enum {
  22         PINMUX_RESERVED = 0,
  23
  24         PINMUX_DATA_BEGIN,
  25         PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
  26         PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
  27         PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
  28         PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
  29         PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
  30         PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
  31         PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
  32         PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
  33         PE7_DATA, PE6_DATA,
  34         PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
  35         PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
  36         PG7_DATA, PG6_DATA, PG5_DATA,
  37         PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
  38         PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
  39         PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
  40         PJ3_DATA, PJ2_DATA, PJ1_DATA,
  41         PINMUX_DATA_END,
  42
  43         PINMUX_INPUT_BEGIN,
  44         PA7_IN, PA6_IN, PA5_IN, PA4_IN,
  45         PA3_IN, PA2_IN, PA1_IN, PA0_IN,
  46         PB7_IN, PB6_IN, PB5_IN, PB4_IN,
  47         PB3_IN, PB2_IN, PB1_IN, PB0_IN,
  48         PC7_IN, PC6_IN, PC5_IN, PC4_IN,
  49         PC3_IN, PC2_IN, PC1_IN, PC0_IN,
  50         PD7_IN, PD6_IN, PD5_IN, PD4_IN,
  51         PD3_IN, PD2_IN, PD1_IN, PD0_IN,
  52         PE7_IN, PE6_IN,
  53         PF7_IN, PF6_IN, PF5_IN, PF4_IN,
  54         PF3_IN, PF2_IN, PF1_IN, PF0_IN,
  55         PG7_IN, PG6_IN, PG5_IN,
  56         PH7_IN, PH6_IN, PH5_IN, PH4_IN,
  57         PH3_IN, PH2_IN, PH1_IN, PH0_IN,
  58         PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
  59         PJ3_IN, PJ2_IN, PJ1_IN,
  60         PINMUX_INPUT_END,
  61
  62         PINMUX_INPUT_PULLUP_BEGIN,
  63         PA7_IN_PU, PA6_IN_PU, PA5_IN_PU, PA4_IN_PU,
  64         PA3_IN_PU, PA2_IN_PU, PA1_IN_PU, PA0_IN_PU,
  65         PB7_IN_PU, PB6_IN_PU, PB5_IN_PU, PB4_IN_PU,
  66         PB3_IN_PU, PB2_IN_PU, PB1_IN_PU, PB0_IN_PU,
  67         PC7_IN_PU, PC6_IN_PU, PC5_IN_PU, PC4_IN_PU,
  68         PC3_IN_PU, PC2_IN_PU, PC1_IN_PU, PC0_IN_PU,
  69         PD7_IN_PU, PD6_IN_PU, PD5_IN_PU, PD4_IN_PU,
  70         PD3_IN_PU, PD2_IN_PU, PD1_IN_PU, PD0_IN_PU,
  71         PE7_IN_PU, PE6_IN_PU,
  72         PF7_IN_PU, PF6_IN_PU, PF5_IN_PU, PF4_IN_PU,
  73         PF3_IN_PU, PF2_IN_PU, PF1_IN_PU, PF0_IN_PU,
  74         PG7_IN_PU, PG6_IN_PU, PG5_IN_PU,
  75         PH7_IN_PU, PH6_IN_PU, PH5_IN_PU, PH4_IN_PU,
  76         PH3_IN_PU, PH2_IN_PU, PH1_IN_PU, PH0_IN_PU,
  77         PJ7_IN_PU, PJ6_IN_PU, PJ5_IN_PU, PJ4_IN_PU,
  78         PJ3_IN_PU, PJ2_IN_PU, PJ1_IN_PU,
  79         PINMUX_INPUT_PULLUP_END,
  80
  81         PINMUX_OUTPUT_BEGIN,
  82         PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
  83         PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
  84         PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
  85         PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
  86         PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
  87         PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
  88         PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
  89         PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
  90         PE7_OUT, PE6_OUT,
  91         PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
  92         PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
  93         PG7_OUT, PG6_OUT, PG5_OUT,
  94         PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT,
  95         PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
  96         PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
  97         PJ3_OUT, PJ2_OUT, PJ1_OUT,
  98         PINMUX_OUTPUT_END,
  99
 100         PINMUX_FUNCTION_BEGIN,
 101         PA7_FN, PA6_FN, PA5_FN, PA4_FN,
 102         PA3_FN, PA2_FN, PA1_FN, PA0_FN,
 103         PB7_FN, PB6_FN, PB5_FN, PB4_FN,
 104         PB3_FN, PB2_FN, PB1_FN, PB0_FN,
 105         PC7_FN, PC6_FN, PC5_FN, PC4_FN,
 106         PC3_FN, PC2_FN, PC1_FN, PC0_FN,
 107         PD7_FN, PD6_FN, PD5_FN, PD4_FN,
 108         PD3_FN, PD2_FN, PD1_FN, PD0_FN,
 109         PE7_FN, PE6_FN,
 110         PF7_FN, PF6_FN, PF5_FN, PF4_FN,
 111         PF3_FN, PF2_FN, PF1_FN, PF0_FN,
 112         PG7_FN, PG6_FN, PG5_FN,
 113         PH7_FN, PH6_FN, PH5_FN, PH4_FN,
 114         PH3_FN, PH2_FN, PH1_FN, PH0_FN,
 115         PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN,
 116         PJ3_FN, PJ2_FN, PJ1_FN,
 117         P1MSEL14_0, P1MSEL14_1,
 118         P1MSEL13_0, P1MSEL13_1,
 119         P1MSEL12_0, P1MSEL12_1,
 120         P1MSEL11_0, P1MSEL11_1,
 121         P1MSEL10_0, P1MSEL10_1,
 122         P1MSEL9_0, P1MSEL9_1,
 123         P1MSEL8_0, P1MSEL8_1,
 124         P1MSEL7_0, P1MSEL7_1,
 125         P1MSEL6_0, P1MSEL6_1,
 126         P1MSEL5_0, P1MSEL5_1,
 127         P1MSEL4_0, P1MSEL4_1,
 128         P1MSEL3_0, P1MSEL3_1,
 129         P1MSEL2_0, P1MSEL2_1,
 130         P1MSEL1_0, P1MSEL1_1,
 131         P1MSEL0_0, P1MSEL0_1,
 132
 133         P2MSEL15_0, P2MSEL15_1,
 134         P2MSEL14_0, P2MSEL14_1,
 135         P2MSEL13_0, P2MSEL13_1,
 136         P2MSEL12_0, P2MSEL12_1,
 137         P2MSEL11_0, P2MSEL11_1,
 138         P2MSEL10_0, P2MSEL10_1,
 139         P2MSEL9_0, P2MSEL9_1,
 140         P2MSEL8_0, P2MSEL8_1,
 141         P2MSEL7_0, P2MSEL7_1,
 142         P2MSEL6_0, P2MSEL6_1,
 143         P2MSEL5_0, P2MSEL5_1,
 144         P2MSEL4_0, P2MSEL4_1,
 145         P2MSEL3_0, P2MSEL3_1,
 146         P2MSEL2_0, P2MSEL2_1,
 147         P2MSEL1_0, P2MSEL1_1,
 148         P2MSEL0_0, P2MSEL0_1,
 149         PINMUX_FUNCTION_END,
 150
 151         PINMUX_MARK_BEGIN,
 152         CDE_MARK,
 153         ETH_MAGIC_MARK,
 154         DISP_MARK,
 155         ETH_LINK_MARK,
 156         DR5_MARK,
 157         ETH_TX_ER_MARK,
 158         DR4_MARK,
 159         ETH_TX_EN_MARK,
 160         DR3_MARK,
 161         ETH_TXD3_MARK,
 162         DR2_MARK,
 163         ETH_TXD2_MARK,
 164         DR1_MARK,
 165         ETH_TXD1_MARK,
 166         DR0_MARK,
 167         ETH_TXD0_MARK,
 168
 169         VSYNC_MARK,
 170         HSPI_CLK_MARK,
 171         ODDF_MARK,
 172         HSPI_CS_MARK,
 173         DG5_MARK,
 174         ETH_MDIO_MARK,
 175         DG4_MARK,
 176         ETH_RX_CLK_MARK,
 177         DG3_MARK,
 178         ETH_MDC_MARK,
 179         DG2_MARK,
 180         ETH_COL_MARK,
 181         DG1_MARK,
 182         ETH_TX_CLK_MARK,
 183         DG0_MARK,
 184         ETH_CRS_MARK,
 185
 186         DCLKIN_MARK,
 187         HSPI_RX_MARK,
 188         HSYNC_MARK,
 189         HSPI_TX_MARK,
 190         DB5_MARK,
 191         ETH_RXD3_MARK,
 192         DB4_MARK,
 193         ETH_RXD2_MARK,
 194         DB3_MARK,
 195         ETH_RXD1_MARK,
 196         DB2_MARK,
 197         ETH_RXD0_MARK,
 198         DB1_MARK,
 199         ETH_RX_DV_MARK,
 200         DB0_MARK,
 201         ETH_RX_ER_MARK,
 202
 203         DCLKOUT_MARK,
 204         SCIF1_SLK_MARK,
 205         SCIF1_RXD_MARK,
 206         SCIF1_TXD_MARK,
 207         DACK1_MARK,
 208         BACK_MARK,
 209         FALE_MARK,
 210         DACK0_MARK,
 211         FCLE_MARK,
 212         DREQ1_MARK,
 213         BREQ_MARK,
 214         USB_OVC1_MARK,
 215         DREQ0_MARK,
 216         USB_OVC0_MARK,
 217
 218         USB_PENC1_MARK,
 219         USB_PENC0_MARK,
 220
 221         HAC1_SDOUT_MARK,
 222         SSI1_SDATA_MARK,
 223         SDIF1CMD_MARK,
 224         HAC1_SDIN_MARK,
 225         SSI1_SCK_MARK,
 226         SDIF1CD_MARK,
 227         HAC1_SYNC_MARK,
 228         SSI1_WS_MARK,
 229         SDIF1WP_MARK,
 230         HAC1_BITCLK_MARK,
 231         SSI1_CLK_MARK,
 232         SDIF1CLK_MARK,
 233         HAC0_SDOUT_MARK,
 234         SSI0_SDATA_MARK,
 235         SDIF1D3_MARK,
 236         HAC0_SDIN_MARK,
 237         SSI0_SCK_MARK,
 238         SDIF1D2_MARK,
 239         HAC0_SYNC_MARK,
 240         SSI0_WS_MARK,
 241         SDIF1D1_MARK,
 242         HAC0_BITCLK_MARK,
 243         SSI0_CLK_MARK,
 244         SDIF1D0_MARK,
 245
 246         SCIF3_SCK_MARK,
 247         SSI2_SDATA_MARK,
 248         SCIF3_RXD_MARK,
 249         TCLK_MARK,
 250         SSI2_SCK_MARK,
 251         SCIF3_TXD_MARK,
 252         HAC_RES_MARK,
 253         SSI2_WS_MARK,
 254
 255         DACK3_MARK,
 256         SDIF0CMD_MARK,
 257         DACK2_MARK,
 258         SDIF0CD_MARK,
 259         DREQ3_MARK,
 260         SDIF0WP_MARK,
 261         SCIF0_CTS_MARK,
 262         DREQ2_MARK,
 263         SDIF0CLK_MARK,
 264         SCIF0_RTS_MARK,
 265         IRL7_MARK,
 266         SDIF0D3_MARK,
 267         SCIF0_SCK_MARK,
 268         IRL6_MARK,
 269         SDIF0D2_MARK,
 270         SCIF0_RXD_MARK,
 271         IRL5_MARK,
 272         SDIF0D1_MARK,
 273         SCIF0_TXD_MARK,
 274         IRL4_MARK,
 275         SDIF0D0_MARK,
 276
 277         SCIF5_SCK_MARK,
 278         FRB_MARK,
 279         SCIF5_RXD_MARK,
 280         IOIS16_MARK,
 281         SCIF5_TXD_MARK,
 282         CE2B_MARK,
 283         DRAK3_MARK,
 284         CE2A_MARK,
 285         SCIF4_SCK_MARK,
 286         DRAK2_MARK,
 287         SSI3_WS_MARK,
 288         SCIF4_RXD_MARK,
 289         DRAK1_MARK,
 290         SSI3_SDATA_MARK,
 291         FSTATUS_MARK,
 292         SCIF4_TXD_MARK,
 293         DRAK0_MARK,
 294         SSI3_SCK_MARK,
 295         FSE_MARK,
 296         PINMUX_MARK_END,
 297 };
 298
 299 static pinmux_enum_t pinmux_data[] = {
 300
 301         /* PA GPIO */
 302         PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
 303         PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT, PA6_IN_PU),
 304         PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT, PA5_IN_PU),
 305         PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT, PA4_IN_PU),
 306         PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT, PA3_IN_PU),
 307         PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT, PA2_IN_PU),
 308         PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT, PA1_IN_PU),
 309         PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT, PA0_IN_PU),
 310
 311         /* PB GPIO */
 312         PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT, PB7_IN_PU),
 313         PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT, PB6_IN_PU),
 314         PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT, PB5_IN_PU),
 315         PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT, PB4_IN_PU),
 316         PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT, PB3_IN_PU),
 317         PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT, PB2_IN_PU),
 318         PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT, PB1_IN_PU),
 319         PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT, PB0_IN_PU),
 320
 321         /* PC GPIO */
 322         PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT, PC7_IN_PU),
 323         PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT, PC6_IN_PU),
 324         PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT, PC5_IN_PU),
 325         PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT, PC4_IN_PU),
 326         PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT, PC3_IN_PU),
 327         PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT, PC2_IN_PU),
 328         PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT, PC1_IN_PU),
 329         PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT, PC0_IN_PU),
 330
 331         /* PD GPIO */
 332         PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT, PD7_IN_PU),
 333         PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT, PD6_IN_PU),
 334         PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT, PD5_IN_PU),
 335         PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT, PD4_IN_PU),
 336         PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT, PD3_IN_PU),
 337         PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT, PD2_IN_PU),
 338         PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT, PD1_IN_PU),
 339         PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT, PD0_IN_PU),
 340
 341         /* PE GPIO */
 342         PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT, PE7_IN_PU),
 343         PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT, PE6_IN_PU),
 344
 345         /* PF GPIO */
 346         PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT, PF7_IN_PU),
 347         PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT, PF6_IN_PU),
 348         PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT, PF5_IN_PU),
 349         PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT, PF4_IN_PU),
 350         PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT, PF3_IN_PU),
 351         PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT, PF2_IN_PU),
 352         PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT, PF1_IN_PU),
 353         PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT, PF0_IN_PU),
 354
 355         /* PG GPIO */
 356         PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT, PG7_IN_PU),
 357         PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT, PG6_IN_PU),
 358         PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT, PG5_IN_PU),
 359
 360         /* PH GPIO */
 361         PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT, PH7_IN_PU),
 362         PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT, PH6_IN_PU),
 363         PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT, PH5_IN_PU),
 364         PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT, PH4_IN_PU),
 365         PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT, PH3_IN_PU),
 366         PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT, PH2_IN_PU),
 367         PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT, PH1_IN_PU),
 368         PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT, PH0_IN_PU),
 369
 370         /* PJ GPIO */
 371         PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT, PJ7_IN_PU),
 372         PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT, PJ6_IN_PU),
 373         PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT, PJ5_IN_PU),
 374         PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT, PJ4_IN_PU),
 375         PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT, PJ3_IN_PU),
 376         PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT, PJ2_IN_PU),
 377         PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT, PJ1_IN_PU),
 378
 379         /* PA FN */
 380         PINMUX_MARK_BEGIN,
 381         PINMUX_DATA(CDE_MARK,           P1MSEL2_0, PA7_FN),
 382         PINMUX_DATA(DISP_MARK,          P1MSEL2_0, PA6_FN),
 383         PINMUX_DATA(DR5_MARK,           P1MSEL2_0, PA5_FN),
 384         PINMUX_DATA(DR4_MARK,           P1MSEL2_0, PA4_FN),
 385         PINMUX_DATA(DR3_MARK,           P1MSEL2_0, PA3_FN),
 386         PINMUX_DATA(DR2_MARK,           P1MSEL2_0, PA2_FN),
 387         PINMUX_DATA(DR1_MARK,           P1MSEL2_0, PA1_FN),
 388         PINMUX_DATA(DR0_MARK,           P1MSEL2_0, PA0_FN),
 389         PINMUX_DATA(ETH_MAGIC_MARK,     P1MSEL2_1, PA7_FN),
 390         PINMUX_DATA(ETH_LINK_MARK,      P1MSEL2_1, PA6_FN),
 391         PINMUX_DATA(ETH_TX_ER_MARK,     P1MSEL2_1, PA5_FN),
 392         PINMUX_DATA(ETH_TX_EN_MARK,     P1MSEL2_1, PA4_FN),
 393         PINMUX_DATA(ETH_TXD3_MARK,      P1MSEL2_1, PA3_FN),
 394         PINMUX_DATA(ETH_TXD2_MARK,      P1MSEL2_1, PA2_FN),
 395         PINMUX_DATA(ETH_TXD1_MARK,      P1MSEL2_1, PA1_FN),
 396         PINMUX_DATA(ETH_TXD0_MARK,      P1MSEL2_1, PA0_FN),
 397
 398         /* PB FN */
 399         PINMUX_DATA(VSYNC_MARK,         P1MSEL3_0, PB7_FN),
 400         PINMUX_DATA(ODDF_MARK,          P1MSEL3_0, PB6_FN),
 401         PINMUX_DATA(DG5_MARK,           P1MSEL2_0, PB5_FN),
 402         PINMUX_DATA(DG4_MARK,           P1MSEL2_0, PB4_FN),
 403         PINMUX_DATA(DG3_MARK,           P1MSEL2_0, PB3_FN),
 404         PINMUX_DATA(DG2_MARK,           P1MSEL2_0, PB2_FN),
 405         PINMUX_DATA(DG1_MARK,           P1MSEL2_0, PB1_FN),
 406         PINMUX_DATA(DG0_MARK,           P1MSEL2_0, PB0_FN),
 407         PINMUX_DATA(HSPI_CLK_MARK,      P1MSEL3_1, PB7_FN),
 408         PINMUX_DATA(HSPI_CS_MARK,       P1MSEL3_1, PB6_FN),
 409         PINMUX_DATA(ETH_MDIO_MARK,      P1MSEL2_1, PB5_FN),
 410         PINMUX_DATA(ETH_RX_CLK_MARK,    P1MSEL2_1, PB4_FN),
 411         PINMUX_DATA(ETH_MDC_MARK,       P1MSEL2_1, PB3_FN),
 412         PINMUX_DATA(ETH_COL_MARK,       P1MSEL2_1, PB2_FN),
 413         PINMUX_DATA(ETH_TX_CLK_MARK,    P1MSEL2_1, PB1_FN),
 414         PINMUX_DATA(ETH_CRS_MARK,       P1MSEL2_1, PB0_FN),
 415
 416         /* PC FN */
 417         PINMUX_DATA(DCLKIN_MARK,        P1MSEL3_0, PC7_FN),
 418         PINMUX_DATA(HSYNC_MARK,         P1MSEL3_0, PC6_FN),
 419         PINMUX_DATA(DB5_MARK,           P1MSEL2_0, PC5_FN),
 420         PINMUX_DATA(DB4_MARK,           P1MSEL2_0, PC4_FN),
 421         PINMUX_DATA(DB3_MARK,           P1MSEL2_0, PC3_FN),
 422         PINMUX_DATA(DB2_MARK,           P1MSEL2_0, PC2_FN),
 423         PINMUX_DATA(DB1_MARK,           P1MSEL2_0, PC1_FN),
 424         PINMUX_DATA(DB0_MARK,           P1MSEL2_0, PC0_FN),
 425
 426         PINMUX_DATA(HSPI_RX_MARK,       P1MSEL3_1, PC7_FN),
 427         PINMUX_DATA(HSPI_TX_MARK,       P1MSEL3_1, PC6_FN),
 428         PINMUX_DATA(ETH_RXD3_MARK,      P1MSEL2_1, PC5_FN),
 429         PINMUX_DATA(ETH_RXD2_MARK,      P1MSEL2_1, PC4_FN),
 430         PINMUX_DATA(ETH_RXD1_MARK,      P1MSEL2_1, PC3_FN),
 431         PINMUX_DATA(ETH_RXD0_MARK,      P1MSEL2_1, PC2_FN),
 432         PINMUX_DATA(ETH_RX_DV_MARK,     P1MSEL2_1, PC1_FN),
 433         PINMUX_DATA(ETH_RX_ER_MARK,     P1MSEL2_1, PC0_FN),
 434
 435         /* PD FN */
 436         PINMUX_DATA(DCLKOUT_MARK,       PD7_FN),
 437         PINMUX_DATA(SCIF1_SLK_MARK,     PD6_FN),
 438         PINMUX_DATA(SCIF1_RXD_MARK,     PD5_FN),
 439         PINMUX_DATA(SCIF1_TXD_MARK,     PD4_FN),
 440         PINMUX_DATA(DACK1_MARK,         P1MSEL13_1, P1MSEL12_0, PD3_FN),
 441         PINMUX_DATA(BACK_MARK,          P1MSEL13_0, P1MSEL12_1, PD3_FN),
 442         PINMUX_DATA(FALE_MARK,          P1MSEL13_0, P1MSEL12_0, PD3_FN),
 443         PINMUX_DATA(DACK0_MARK,         P1MSEL14_1, PD2_FN),
 444         PINMUX_DATA(FCLE_MARK,          P1MSEL14_0, PD2_FN),
 445         PINMUX_DATA(DREQ1_MARK,         P1MSEL10_0, P1MSEL9_1, PD1_FN),
 446         PINMUX_DATA(BREQ_MARK,          P1MSEL10_1, P1MSEL9_0, PD1_FN),
 447         PINMUX_DATA(USB_OVC1_MARK,      P1MSEL10_0, P1MSEL9_0, PD1_FN),
 448         PINMUX_DATA(DREQ0_MARK,         P1MSEL11_1, PD0_FN),
 449         PINMUX_DATA(USB_OVC0_MARK,      P1MSEL11_0, PD0_FN),
 450
 451         /* PE FN */
 452         PINMUX_DATA(USB_PENC1_MARK,     PE7_FN),
 453         PINMUX_DATA(USB_PENC0_MARK,     PE6_FN),
 454
 455         /* PF FN */
 456         PINMUX_DATA(HAC1_SDOUT_MARK,    P2MSEL15_0, P2MSEL14_0, PF7_FN),
 457         PINMUX_DATA(HAC1_SDIN_MARK,     P2MSEL15_0, P2MSEL14_0, PF6_FN),
 458         PINMUX_DATA(HAC1_SYNC_MARK,     P2MSEL15_0, P2MSEL14_0, PF5_FN),
 459         PINMUX_DATA(HAC1_BITCLK_MARK,   P2MSEL15_0, P2MSEL14_0, PF4_FN),
 460         PINMUX_DATA(HAC0_SDOUT_MARK,    P2MSEL13_0, P2MSEL12_0, PF3_FN),
 461         PINMUX_DATA(HAC0_SDIN_MARK,     P2MSEL13_0, P2MSEL12_0, PF2_FN),
 462         PINMUX_DATA(HAC0_SYNC_MARK,     P2MSEL13_0, P2MSEL12_0, PF1_FN),
 463         PINMUX_DATA(HAC0_BITCLK_MARK,   P2MSEL13_0, P2MSEL12_0, PF0_FN),
 464         PINMUX_DATA(SSI1_SDATA_MARK,    P2MSEL15_0, P2MSEL14_1, PF7_FN),
 465         PINMUX_DATA(SSI1_SCK_MARK,      P2MSEL15_0, P2MSEL14_1, PF6_FN),
 466         PINMUX_DATA(SSI1_WS_MARK,       P2MSEL15_0, P2MSEL14_1, PF5_FN),
 467         PINMUX_DATA(SSI1_CLK_MARK,      P2MSEL15_0, P2MSEL14_1, PF4_FN),
 468         PINMUX_DATA(SSI0_SDATA_MARK,    P2MSEL13_0, P2MSEL12_1, PF3_FN),
 469         PINMUX_DATA(SSI0_SCK_MARK,      P2MSEL13_0, P2MSEL12_1, PF2_FN),
 470         PINMUX_DATA(SSI0_WS_MARK,       P2MSEL13_0, P2MSEL12_1, PF1_FN),
 471         PINMUX_DATA(SSI0_CLK_MARK,      P2MSEL13_0, P2MSEL12_1, PF0_FN),
 472         PINMUX_DATA(SDIF1CMD_MARK,      P2MSEL15_1, P2MSEL14_0, PF7_FN),
 473         PINMUX_DATA(SDIF1CD_MARK,       P2MSEL15_1, P2MSEL14_0, PF6_FN),
 474         PINMUX_DATA(SDIF1WP_MARK,       P2MSEL15_1, P2MSEL14_0, PF5_FN),
 475         PINMUX_DATA(SDIF1CLK_MARK,      P2MSEL15_1, P2MSEL14_0, PF4_FN),
 476         PINMUX_DATA(SDIF1D3_MARK,       P2MSEL13_1, P2MSEL12_0, PF3_FN),
 477         PINMUX_DATA(SDIF1D2_MARK,       P2MSEL13_1, P2MSEL12_0, PF2_FN),
 478         PINMUX_DATA(SDIF1D1_MARK,       P2MSEL13_1, P2MSEL12_0, PF1_FN),
 479         PINMUX_DATA(SDIF1D0_MARK,       P2MSEL13_1, P2MSEL12_0, PF0_FN),
 480
 481         /* PG FN */
 482         PINMUX_DATA(SCIF3_SCK_MARK,     P1MSEL8_0, PG7_FN),
 483         PINMUX_DATA(SSI2_SDATA_MARK,    P1MSEL8_1, PG7_FN),
 484         PINMUX_DATA(SCIF3_RXD_MARK,     P1MSEL7_0, P1MSEL6_0, PG6_FN),
 485         PINMUX_DATA(SSI2_SCK_MARK,      P1MSEL7_1, P1MSEL6_0, PG6_FN),
 486         PINMUX_DATA(TCLK_MARK,          P1MSEL7_0, P1MSEL6_1, PG6_FN),
 487         PINMUX_DATA(SCIF3_TXD_MARK,     P1MSEL5_0, P1MSEL4_0, PG5_FN),
 488         PINMUX_DATA(SSI2_WS_MARK,       P1MSEL5_1, P1MSEL4_0, PG5_FN),
 489         PINMUX_DATA(HAC_RES_MARK,       P1MSEL5_0, P1MSEL4_1, PG5_FN),
 490
 491         /* PH FN */
 492         PINMUX_DATA(DACK3_MARK,         P2MSEL4_0, PH7_FN),
 493         PINMUX_DATA(SDIF0CMD_MARK,      P2MSEL4_1, PH7_FN),
 494         PINMUX_DATA(DACK2_MARK,         P2MSEL4_0, PH6_FN),
 495         PINMUX_DATA(SDIF0CD_MARK,       P2MSEL4_1, PH6_FN),
 496         PINMUX_DATA(DREQ3_MARK,         P2MSEL4_0, PH5_FN),
 497         PINMUX_DATA(SDIF0WP_MARK,       P2MSEL4_1, PH5_FN),
 498         PINMUX_DATA(DREQ2_MARK,         P2MSEL3_0, P2MSEL2_1, PH4_FN),
 499         PINMUX_DATA(SDIF0CLK_MARK,      P2MSEL3_1, P2MSEL2_0, PH4_FN),
 500         PINMUX_DATA(SCIF0_CTS_MARK,     P2MSEL3_0, P2MSEL2_0, PH4_FN),
 501         PINMUX_DATA(SDIF0D3_MARK,       P2MSEL1_1, P2MSEL0_0, PH3_FN),
 502         PINMUX_DATA(SCIF0_RTS_MARK,     P2MSEL1_0, P2MSEL0_0, PH3_FN),
 503         PINMUX_DATA(IRL7_MARK,          P2MSEL1_0, P2MSEL0_1, PH3_FN),
 504         PINMUX_DATA(SDIF0D2_MARK,       P2MSEL1_1, P2MSEL0_0, PH2_FN),
 505         PINMUX_DATA(SCIF0_SCK_MARK,     P2MSEL1_0, P2MSEL0_0, PH2_FN),
 506         PINMUX_DATA(IRL6_MARK,          P2MSEL1_0, P2MSEL0_1, PH2_FN),
 507         PINMUX_DATA(SDIF0D1_MARK,       P2MSEL1_1, P2MSEL0_0, PH1_FN),
 508         PINMUX_DATA(SCIF0_RXD_MARK,     P2MSEL1_0, P2MSEL0_0, PH1_FN),
 509         PINMUX_DATA(IRL5_MARK,          P2MSEL1_0, P2MSEL0_1, PH1_FN),
 510         PINMUX_DATA(SDIF0D0_MARK,       P2MSEL1_1, P2MSEL0_0, PH0_FN),
 511         PINMUX_DATA(SCIF0_TXD_MARK,     P2MSEL1_0, P2MSEL0_0, PH0_FN),
 512         PINMUX_DATA(IRL4_MARK,          P2MSEL1_0, P2MSEL0_1, PH0_FN),
 513
 514         /* PJ FN */
 515         PINMUX_DATA(SCIF5_SCK_MARK,     P2MSEL11_1, PJ7_FN),
 516         PINMUX_DATA(FRB_MARK,           P2MSEL11_0, PJ7_FN),
 517         PINMUX_DATA(SCIF5_RXD_MARK,     P2MSEL10_0, PJ6_FN),
 518         PINMUX_DATA(IOIS16_MARK,        P2MSEL10_1, PJ6_FN),
 519         PINMUX_DATA(SCIF5_TXD_MARK,     P2MSEL10_0, PJ5_FN),
 520         PINMUX_DATA(CE2B_MARK,          P2MSEL10_1, PJ5_FN),
 521         PINMUX_DATA(DRAK3_MARK,         P2MSEL7_0, PJ4_FN),
 522         PINMUX_DATA(CE2A_MARK,          P2MSEL7_1, PJ4_FN),
 523         PINMUX_DATA(SCIF4_SCK_MARK,     P2MSEL9_0, P2MSEL8_0, PJ3_FN),
 524         PINMUX_DATA(DRAK2_MARK,         P2MSEL9_0, P2MSEL8_1, PJ3_FN),
 525         PINMUX_DATA(SSI3_WS_MARK,       P2MSEL9_1, P2MSEL8_0, PJ3_FN),
 526         PINMUX_DATA(SCIF4_RXD_MARK,     P2MSEL6_1, P2MSEL5_0, PJ2_FN),
 527         PINMUX_DATA(DRAK1_MARK,         P2MSEL6_0, P2MSEL5_1, PJ2_FN),
 528         PINMUX_DATA(FSTATUS_MARK,       P2MSEL6_0, P2MSEL5_0, PJ2_FN),
 529         PINMUX_DATA(SSI3_SDATA_MARK,    P2MSEL6_1, P2MSEL5_1, PJ2_FN),
 530         PINMUX_DATA(SCIF4_TXD_MARK,     P2MSEL6_1, P2MSEL5_0, PJ1_FN),
 531         PINMUX_DATA(DRAK0_MARK,         P2MSEL6_0, P2MSEL5_1, PJ1_FN),
 532         PINMUX_DATA(FSE_MARK,           P2MSEL6_0, P2MSEL5_0, PJ1_FN),
 533         PINMUX_DATA(SSI3_SCK_MARK,      P2MSEL6_1, P2MSEL5_1, PJ1_FN),
 534 };
 535
 536 static struct pinmux_gpio pinmux_gpios[] = {
 537         /* PA */
 538         PINMUX_GPIO(GPIO_PA7, PA7_DATA),
 539         PINMUX_GPIO(GPIO_PA6, PA6_DATA),
 540         PINMUX_GPIO(GPIO_PA5, PA5_DATA),
 541         PINMUX_GPIO(GPIO_PA4, PA4_DATA),
 542         PINMUX_GPIO(GPIO_PA3, PA3_DATA),
 543         PINMUX_GPIO(GPIO_PA2, PA2_DATA),
 544         PINMUX_GPIO(GPIO_PA1, PA1_DATA),
 545         PINMUX_GPIO(GPIO_PA0, PA0_DATA),
 546
 547         /* PB */
 548         PINMUX_GPIO(GPIO_PB7, PB7_DATA),
 549         PINMUX_GPIO(GPIO_PB6, PB6_DATA),
 550         PINMUX_GPIO(GPIO_PB5, PB5_DATA),
 551         PINMUX_GPIO(GPIO_PB4, PB4_DATA),
 552         PINMUX_GPIO(GPIO_PB3, PB3_DATA),
 553         PINMUX_GPIO(GPIO_PB2, PB2_DATA),
 554         PINMUX_GPIO(GPIO_PB1, PB1_DATA),
 555         PINMUX_GPIO(GPIO_PB0, PB0_DATA),
 556
 557         /* PC */
 558         PINMUX_GPIO(GPIO_PC7, PC7_DATA),
 559         PINMUX_GPIO(GPIO_PC6, PC6_DATA),
 560         PINMUX_GPIO(GPIO_PC5, PC5_DATA),
 561         PINMUX_GPIO(GPIO_PC4, PC4_DATA),
 562         PINMUX_GPIO(GPIO_PC3, PC3_DATA),
 563         PINMUX_GPIO(GPIO_PC2, PC2_DATA),
 564         PINMUX_GPIO(GPIO_PC1, PC1_DATA),
 565         PINMUX_GPIO(GPIO_PC0, PC0_DATA),
 566
 567         /* PD */
 568         PINMUX_GPIO(GPIO_PD7, PD7_DATA),
 569         PINMUX_GPIO(GPIO_PD6, PD6_DATA),
 570         PINMUX_GPIO(GPIO_PD5, PD5_DATA),
 571         PINMUX_GPIO(GPIO_PD4, PD4_DATA),
 572         PINMUX_GPIO(GPIO_PD3, PD3_DATA),
 573         PINMUX_GPIO(GPIO_PD2, PD2_DATA),
 574         PINMUX_GPIO(GPIO_PD1, PD1_DATA),
 575         PINMUX_GPIO(GPIO_PD0, PD0_DATA),
 576
 577         /* PE */
 578         PINMUX_GPIO(GPIO_PE5, PE7_DATA),
 579         PINMUX_GPIO(GPIO_PE4, PE6_DATA),
 580
 581         /* PF */
 582         PINMUX_GPIO(GPIO_PF7, PF7_DATA),
 583         PINMUX_GPIO(GPIO_PF6, PF6_DATA),
 584         PINMUX_GPIO(GPIO_PF5, PF5_DATA),
 585         PINMUX_GPIO(GPIO_PF4, PF4_DATA),
 586         PINMUX_GPIO(GPIO_PF3, PF3_DATA),
 587         PINMUX_GPIO(GPIO_PF2, PF2_DATA),
 588         PINMUX_GPIO(GPIO_PF1, PF1_DATA),
 589         PINMUX_GPIO(GPIO_PF0, PF0_DATA),
 590
 591         /* PG */
 592         PINMUX_GPIO(GPIO_PG7, PG7_DATA),
 593         PINMUX_GPIO(GPIO_PG6, PG6_DATA),
 594         PINMUX_GPIO(GPIO_PG5, PG5_DATA),
 595
 596         /* PH */
 597         PINMUX_GPIO(GPIO_PH7, PH7_DATA),
 598         PINMUX_GPIO(GPIO_PH6, PH6_DATA),
 599         PINMUX_GPIO(GPIO_PH5, PH5_DATA),
 600         PINMUX_GPIO(GPIO_PH4, PH4_DATA),
 601         PINMUX_GPIO(GPIO_PH3, PH3_DATA),
 602         PINMUX_GPIO(GPIO_PH2, PH2_DATA),
 603         PINMUX_GPIO(GPIO_PH1, PH1_DATA),
 604         PINMUX_GPIO(GPIO_PH0, PH0_DATA),
 605
 606         /* PJ */
 607         PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
 608         PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
 609         PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
 610         PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
 611         PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
 612         PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
 613         PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
 614
 615         /* FN */
 616         PINMUX_GPIO(GPIO_FN_CDE,                CDE_MARK),
 617         PINMUX_GPIO(GPIO_FN_ETH_MAGIC,          ETH_MAGIC_MARK),
 618         PINMUX_GPIO(GPIO_FN_DISP,               DISP_MARK),
 619         PINMUX_GPIO(GPIO_FN_ETH_LINK,           ETH_LINK_MARK),
 620         PINMUX_GPIO(GPIO_FN_DR5,                DR5_MARK),
 621         PINMUX_GPIO(GPIO_FN_ETH_TX_ER,          ETH_TX_ER_MARK),
 622         PINMUX_GPIO(GPIO_FN_DR4,                DR4_MARK),
 623         PINMUX_GPIO(GPIO_FN_ETH_TX_EN,          ETH_TX_EN_MARK),
 624         PINMUX_GPIO(GPIO_FN_DR3,                DR3_MARK),
 625         PINMUX_GPIO(GPIO_FN_ETH_TXD3,           ETH_TXD3_MARK),
 626         PINMUX_GPIO(GPIO_FN_DR2,                DR2_MARK),
 627         PINMUX_GPIO(GPIO_FN_ETH_TXD2,           ETH_TXD2_MARK),
 628         PINMUX_GPIO(GPIO_FN_DR1,                DR1_MARK),
 629         PINMUX_GPIO(GPIO_FN_ETH_TXD1,           ETH_TXD1_MARK),
 630         PINMUX_GPIO(GPIO_FN_DR0,                DR0_MARK),
 631         PINMUX_GPIO(GPIO_FN_ETH_TXD0,           ETH_TXD0_MARK),
 632         PINMUX_GPIO(GPIO_FN_VSYNC,              VSYNC_MARK),
 633         PINMUX_GPIO(GPIO_FN_HSPI_CLK,           HSPI_CLK_MARK),
 634         PINMUX_GPIO(GPIO_FN_ODDF,               ODDF_MARK),
 635         PINMUX_GPIO(GPIO_FN_HSPI_CS,            HSPI_CS_MARK),
 636         PINMUX_GPIO(GPIO_FN_DG5,                DG5_MARK),
 637         PINMUX_GPIO(GPIO_FN_ETH_MDIO,           ETH_MDIO_MARK),
 638         PINMUX_GPIO(GPIO_FN_DG4,                DG4_MARK),
 639         PINMUX_GPIO(GPIO_FN_ETH_RX_CLK,         ETH_RX_CLK_MARK),
 640         PINMUX_GPIO(GPIO_FN_DG3,                DG3_MARK),
 641         PINMUX_GPIO(GPIO_FN_ETH_MDC,            ETH_MDC_MARK),
 642         PINMUX_GPIO(GPIO_FN_DG2,                DG2_MARK),
 643         PINMUX_GPIO(GPIO_FN_ETH_COL,            ETH_COL_MARK),
 644         PINMUX_GPIO(GPIO_FN_DG1,                DG1_MARK),
 645         PINMUX_GPIO(GPIO_FN_ETH_TX_CLK,         ETH_TX_CLK_MARK),
 646         PINMUX_GPIO(GPIO_FN_DG0,                DG0_MARK),
 647         PINMUX_GPIO(GPIO_FN_ETH_CRS,            ETH_CRS_MARK),
 648         PINMUX_GPIO(GPIO_FN_DCLKIN,             DCLKIN_MARK),
 649         PINMUX_GPIO(GPIO_FN_HSPI_RX,            HSPI_RX_MARK),
 650         PINMUX_GPIO(GPIO_FN_HSYNC,              HSYNC_MARK),
 651         PINMUX_GPIO(GPIO_FN_HSPI_TX,            HSPI_TX_MARK),
 652         PINMUX_GPIO(GPIO_FN_DB5,                DB5_MARK),
 653         PINMUX_GPIO(GPIO_FN_ETH_RXD3,           ETH_RXD3_MARK),
 654         PINMUX_GPIO(GPIO_FN_DB4,                DB4_MARK),
 655         PINMUX_GPIO(GPIO_FN_ETH_RXD2,           ETH_RXD2_MARK),
 656         PINMUX_GPIO(GPIO_FN_DB3,                DB3_MARK),
 657         PINMUX_GPIO(GPIO_FN_ETH_RXD1,           ETH_RXD1_MARK),
 658         PINMUX_GPIO(GPIO_FN_DB2,                DB2_MARK),
 659         PINMUX_GPIO(GPIO_FN_ETH_RXD0,           ETH_RXD0_MARK),
 660         PINMUX_GPIO(GPIO_FN_DB1,                DB1_MARK),
 661         PINMUX_GPIO(GPIO_FN_ETH_RX_DV,          ETH_RX_DV_MARK),
 662         PINMUX_GPIO(GPIO_FN_DB0,                DB0_MARK),
 663         PINMUX_GPIO(GPIO_FN_ETH_RX_ER,          ETH_RX_ER_MARK),
 664         PINMUX_GPIO(GPIO_FN_DCLKOUT,            DCLKOUT_MARK),
 665         PINMUX_GPIO(GPIO_FN_SCIF1_SLK,          SCIF1_SLK_MARK),
 666         PINMUX_GPIO(GPIO_FN_SCIF1_RXD,          SCIF1_RXD_MARK),
 667         PINMUX_GPIO(GPIO_FN_SCIF1_TXD,          SCIF1_TXD_MARK),
 668         PINMUX_GPIO(GPIO_FN_DACK1,              DACK1_MARK),
 669         PINMUX_GPIO(GPIO_FN_BACK,               BACK_MARK),
 670         PINMUX_GPIO(GPIO_FN_FALE,               FALE_MARK),
 671         PINMUX_GPIO(GPIO_FN_DACK0,              DACK0_MARK),
 672         PINMUX_GPIO(GPIO_FN_FCLE,               FCLE_MARK),
 673         PINMUX_GPIO(GPIO_FN_DREQ1,              DREQ1_MARK),
 674         PINMUX_GPIO(GPIO_FN_BREQ,               BREQ_MARK),
 675         PINMUX_GPIO(GPIO_FN_USB_OVC1,           USB_OVC1_MARK),
 676         PINMUX_GPIO(GPIO_FN_DREQ0,              DREQ0_MARK),
 677         PINMUX_GPIO(GPIO_FN_USB_OVC0,           USB_OVC0_MARK),
 678         PINMUX_GPIO(GPIO_FN_USB_PENC1,          USB_PENC1_MARK),
 679         PINMUX_GPIO(GPIO_FN_USB_PENC0,          USB_PENC0_MARK),
 680         PINMUX_GPIO(GPIO_FN_HAC1_SDOUT,         HAC1_SDOUT_MARK),
 681         PINMUX_GPIO(GPIO_FN_SSI1_SDATA,         SSI1_SDATA_MARK),
 682         PINMUX_GPIO(GPIO_FN_SDIF1CMD,           SDIF1CMD_MARK),
 683         PINMUX_GPIO(GPIO_FN_HAC1_SDIN,          HAC1_SDIN_MARK),
 684         PINMUX_GPIO(GPIO_FN_SSI1_SCK,           SSI1_SCK_MARK),
 685         PINMUX_GPIO(GPIO_FN_SDIF1CD,            SDIF1CD_MARK),
 686         PINMUX_GPIO(GPIO_FN_HAC1_SYNC,          HAC1_SYNC_MARK),
 687         PINMUX_GPIO(GPIO_FN_SSI1_WS,            SSI1_WS_MARK),
 688         PINMUX_GPIO(GPIO_FN_SDIF1WP,            SDIF1WP_MARK),
 689         PINMUX_GPIO(GPIO_FN_HAC1_BITCLK,        HAC1_BITCLK_MARK),
 690         PINMUX_GPIO(GPIO_FN_SSI1_CLK,           SSI1_CLK_MARK),
 691         PINMUX_GPIO(GPIO_FN_SDIF1CLK,           SDIF1CLK_MARK),
 692         PINMUX_GPIO(GPIO_FN_HAC0_SDOUT,         HAC0_SDOUT_MARK),
 693         PINMUX_GPIO(GPIO_FN_SSI0_SDATA,         SSI0_SDATA_MARK),
 694         PINMUX_GPIO(GPIO_FN_SDIF1D3,            SDIF1D3_MARK),
 695         PINMUX_GPIO(GPIO_FN_HAC0_SDIN,          HAC0_SDIN_MARK),
 696         PINMUX_GPIO(GPIO_FN_SSI0_SCK,           SSI0_SCK_MARK),
 697         PINMUX_GPIO(GPIO_FN_SDIF1D2,            SDIF1D2_MARK),
 698         PINMUX_GPIO(GPIO_FN_HAC0_SYNC,          HAC0_SYNC_MARK),
 699         PINMUX_GPIO(GPIO_FN_SSI0_WS,            SSI0_WS_MARK),
 700         PINMUX_GPIO(GPIO_FN_SDIF1D1,            SDIF1D1_MARK),
 701         PINMUX_GPIO(GPIO_FN_HAC0_BITCLK,        HAC0_BITCLK_MARK),
 702         PINMUX_GPIO(GPIO_FN_SSI0_CLK,           SSI0_CLK_MARK),
 703         PINMUX_GPIO(GPIO_FN_SDIF1D0,            SDIF1D0_MARK),
 704         PINMUX_GPIO(GPIO_FN_SCIF3_SCK,          SCIF3_SCK_MARK),
 705         PINMUX_GPIO(GPIO_FN_SSI2_SDATA,         SSI2_SDATA_MARK),
 706         PINMUX_GPIO(GPIO_FN_SCIF3_RXD,          SCIF3_RXD_MARK),
 707         PINMUX_GPIO(GPIO_FN_TCLK,               TCLK_MARK),
 708         PINMUX_GPIO(GPIO_FN_SSI2_SCK,           SSI2_SCK_MARK),
 709         PINMUX_GPIO(GPIO_FN_SCIF3_TXD,          SCIF3_TXD_MARK),
 710         PINMUX_GPIO(GPIO_FN_HAC_RES,            HAC_RES_MARK),
 711         PINMUX_GPIO(GPIO_FN_SSI2_WS,            SSI2_WS_MARK),
 712         PINMUX_GPIO(GPIO_FN_DACK3,              DACK3_MARK),
 713         PINMUX_GPIO(GPIO_FN_SDIF0CMD,           SDIF0CMD_MARK),
 714         PINMUX_GPIO(GPIO_FN_DACK2,              DACK2_MARK),
 715         PINMUX_GPIO(GPIO_FN_SDIF0CD,            SDIF0CD_MARK),
 716         PINMUX_GPIO(GPIO_FN_DREQ3,              DREQ3_MARK),
 717         PINMUX_GPIO(GPIO_FN_SDIF0WP,            SDIF0WP_MARK),
 718         PINMUX_GPIO(GPIO_FN_SCIF0_CTS,          SCIF0_CTS_MARK),
 719         PINMUX_GPIO(GPIO_FN_DREQ2,              DREQ2_MARK),
 720         PINMUX_GPIO(GPIO_FN_SDIF0CLK,           SDIF0CLK_MARK),
 721         PINMUX_GPIO(GPIO_FN_SCIF0_RTS,          SCIF0_RTS_MARK),
 722         PINMUX_GPIO(GPIO_FN_IRL7,               IRL7_MARK),
 723         PINMUX_GPIO(GPIO_FN_SDIF0D3,            SDIF0D3_MARK),
 724         PINMUX_GPIO(GPIO_FN_SCIF0_SCK,          SCIF0_SCK_MARK),
 725         PINMUX_GPIO(GPIO_FN_IRL6,               IRL6_MARK),
 726         PINMUX_GPIO(GPIO_FN_SDIF0D2,            SDIF0D2_MARK),
 727         PINMUX_GPIO(GPIO_FN_SCIF0_RXD,          SCIF0_RXD_MARK),
 728         PINMUX_GPIO(GPIO_FN_IRL5,               IRL5_MARK),
 729         PINMUX_GPIO(GPIO_FN_SDIF0D1,            SDIF0D1_MARK),
 730         PINMUX_GPIO(GPIO_FN_SCIF0_TXD,          SCIF0_TXD_MARK),
 731         PINMUX_GPIO(GPIO_FN_IRL4,               IRL4_MARK),
 732         PINMUX_GPIO(GPIO_FN_SDIF0D0,            SDIF0D0_MARK),
 733         PINMUX_GPIO(GPIO_FN_SCIF5_SCK,          SCIF5_SCK_MARK),
 734         PINMUX_GPIO(GPIO_FN_FRB,                FRB_MARK),
 735         PINMUX_GPIO(GPIO_FN_SCIF5_RXD,          SCIF5_RXD_MARK),
 736         PINMUX_GPIO(GPIO_FN_IOIS16,             IOIS16_MARK),
 737         PINMUX_GPIO(GPIO_FN_SCIF5_TXD,          SCIF5_TXD_MARK),
 738         PINMUX_GPIO(GPIO_FN_CE2B,               CE2B_MARK),
 739         PINMUX_GPIO(GPIO_FN_DRAK3,              DRAK3_MARK),
 740         PINMUX_GPIO(GPIO_FN_CE2A,               CE2A_MARK),
 741         PINMUX_GPIO(GPIO_FN_SCIF4_SCK,          SCIF4_SCK_MARK),
 742         PINMUX_GPIO(GPIO_FN_DRAK2,              DRAK2_MARK),
 743         PINMUX_GPIO(GPIO_FN_SSI3_WS,            SSI3_WS_MARK),
 744         PINMUX_GPIO(GPIO_FN_SCIF4_RXD,          SCIF4_RXD_MARK),
 745         PINMUX_GPIO(GPIO_FN_DRAK1,              DRAK1_MARK),
 746         PINMUX_GPIO(GPIO_FN_SSI3_SDATA,         SSI3_SDATA_MARK),
 747         PINMUX_GPIO(GPIO_FN_FSTATUS,            FSTATUS_MARK),
 748         PINMUX_GPIO(GPIO_FN_SCIF4_TXD,          SCIF4_TXD_MARK),
 749         PINMUX_GPIO(GPIO_FN_DRAK0,              DRAK0_MARK),
 750         PINMUX_GPIO(GPIO_FN_SSI3_SCK,           SSI3_SCK_MARK),
 751         PINMUX_GPIO(GPIO_FN_FSE,                FSE_MARK),
 752 };
 753
 754 static struct pinmux_cfg_reg pinmux_config_regs[] = {
 755         { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
 756                 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
 757                 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
 758                 PA5_FN, PA5_OUT, PA5_IN, PA5_IN_PU,
 759                 PA4_FN, PA4_OUT, PA4_IN, PA4_IN_PU,
 760                 PA3_FN, PA3_OUT, PA3_IN, PA3_IN_PU,
 761                 PA2_FN, PA2_OUT, PA2_IN, PA2_IN_PU,
 762                 PA1_FN, PA1_OUT, PA1_IN, PA1_IN_PU,
 763                 PA0_FN, PA0_OUT, PA0_IN, PA0_IN_PU }
 764         },
 765         { PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2) {
 766                 PB7_FN, PB7_OUT, PB7_IN, PB7_IN_PU,
 767                 PB6_FN, PB6_OUT, PB6_IN, PB6_IN_PU,
 768                 PB5_FN, PB5_OUT, PB5_IN, PB5_IN_PU,
 769                 PB4_FN, PB4_OUT, PB4_IN, PB4_IN_PU,
 770                 PB3_FN, PB3_OUT, PB3_IN, PB3_IN_PU,
 771                 PB2_FN, PB2_OUT, PB2_IN, PB2_IN_PU,
 772                 PB1_FN, PB1_OUT, PB1_IN, PB1_IN_PU,
 773                 PB0_FN, PB0_OUT, PB0_IN, PB0_IN_PU }
 774         },
 775         { PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2) {
 776                 PC7_FN, PC7_OUT, PC7_IN, PC7_IN_PU,
 777                 PC6_FN, PC6_OUT, PC6_IN, PC6_IN_PU,
 778                 PC5_FN, PC5_OUT, PC5_IN, PC5_IN_PU,
 779                 PC4_FN, PC4_OUT, PC4_IN, PC4_IN_PU,
 780                 PC3_FN, PC3_OUT, PC3_IN, PC3_IN_PU,
 781                 PC2_FN, PC2_OUT, PC2_IN, PC2_IN_PU,
 782                 PC1_FN, PC1_OUT, PC1_IN, PC1_IN_PU,
 783                 PC0_FN, PC0_OUT, PC0_IN, PC0_IN_PU }
 784         },
 785         { PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2) {
 786                 PD7_FN, PD7_OUT, PD7_IN, PD7_IN_PU,
 787                 PD6_FN, PD6_OUT, PD6_IN, PD6_IN_PU,
 788                 PD5_FN, PD5_OUT, PD5_IN, PD5_IN_PU,
 789                 PD4_FN, PD4_OUT, PD4_IN, PD4_IN_PU,
 790                 PD3_FN, PD3_OUT, PD3_IN, PD3_IN_PU,
 791                 PD2_FN, PD2_OUT, PD2_IN, PD2_IN_PU,
 792                 PD1_FN, PD1_OUT, PD1_IN, PD1_IN_PU,
 793                 PD0_FN, PD0_OUT, PD0_IN, PD0_IN_PU }
 794         },
 795         { PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2) {
 796                 PE7_FN, PE7_OUT, PE7_IN, PE7_IN_PU,
 797                 PE6_FN, PE6_OUT, PE6_IN, PE6_IN_PU,
 798                 0, 0, 0, 0,
 799                 0, 0, 0, 0,
 800                 0, 0, 0, 0,
 801                 0, 0, 0, 0,
 802                 0, 0, 0, 0,
 803                 0, 0, 0, 0, }
 804         },
 805         { PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2) {
 806                 PF7_FN, PF7_OUT, PF7_IN, PF7_IN_PU,
 807                 PF6_FN, PF6_OUT, PF6_IN, PF6_IN_PU,
 808                 PF5_FN, PF5_OUT, PF5_IN, PF5_IN_PU,
 809                 PF4_FN, PF4_OUT, PF4_IN, PF4_IN_PU,
 810                 PF3_FN, PF3_OUT, PF3_IN, PF3_IN_PU,
 811                 PF2_FN, PF2_OUT, PF2_IN, PF2_IN_PU,
 812                 PF1_FN, PF1_OUT, PF1_IN, PF1_IN_PU,
 813                 PF0_FN, PF0_OUT, PF0_IN, PF0_IN_PU }
 814         },
 815         { PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2) {
 816                 PG7_FN, PG7_OUT, PG7_IN, PG7_IN_PU,
 817                 PG6_FN, PG6_OUT, PG6_IN, PG6_IN_PU,
 818                 PG5_FN, PG5_OUT, PG5_IN, PG5_IN_PU,
 819                 0, 0, 0, 0,
 820                 0, 0, 0, 0,
 821                 0, 0, 0, 0,
 822                 0, 0, 0, 0,
 823                 0, 0, 0, 0, }
 824         },
 825         { PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2) {
 826                 PH7_FN, PH7_OUT, PH7_IN, PH7_IN_PU,
 827                 PH6_FN, PH6_OUT, PH6_IN, PH6_IN_PU,
 828                 PH5_FN, PH5_OUT, PH5_IN, PH5_IN_PU,
 829                 PH4_FN, PH4_OUT, PH4_IN, PH4_IN_PU,
 830                 PH3_FN, PH3_OUT, PH3_IN, PH3_IN_PU,
 831                 PH2_FN, PH2_OUT, PH2_IN, PH2_IN_PU,
 832                 PH1_FN, PH1_OUT, PH1_IN, PH1_IN_PU,
 833                 PH0_FN, PH0_OUT, PH0_IN, PH0_IN_PU }
 834         },
 835         { PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2) {
 836                 PJ7_FN, PJ7_OUT, PJ7_IN, PJ7_IN_PU,
 837                 PJ6_FN, PJ6_OUT, PJ6_IN, PJ6_IN_PU,
 838                 PJ5_FN, PJ5_OUT, PJ5_IN, PJ5_IN_PU,
 839                 PJ4_FN, PJ4_OUT, PJ4_IN, PJ4_IN_PU,
 840                 PJ3_FN, PJ3_OUT, PJ3_IN, PJ3_IN_PU,
 841                 PJ2_FN, PJ2_OUT, PJ2_IN, PJ2_IN_PU,
 842                 PJ1_FN, PJ1_OUT, PJ1_IN, PJ1_IN_PU,
 843                 0, 0, 0, 0, }
 844         },
 845         { PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1) {
 846                 0, 0,
 847                 P1MSEL14_0, P1MSEL14_1,
 848                 P1MSEL13_0, P1MSEL13_1,
 849                 P1MSEL12_0, P1MSEL12_1,
 850                 P1MSEL11_0, P1MSEL11_1,
 851                 P1MSEL10_0, P1MSEL10_1,
 852                 P1MSEL9_0,  P1MSEL9_1,
 853                 P1MSEL8_0,  P1MSEL8_1,
 854                 P1MSEL7_0,  P1MSEL7_1,
 855                 P1MSEL6_0,  P1MSEL6_1,
 856                 P1MSEL5_0,  P1MSEL5_1,
 857                 P1MSEL4_0,  P1MSEL4_1,
 858                 P1MSEL3_0,  P1MSEL3_1,
 859                 P1MSEL2_0,  P1MSEL2_1,
 860                 P1MSEL1_0,  P1MSEL1_1,
 861                 P1MSEL0_0,  P1MSEL0_1 }
 862         },
 863         { PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1) {
 864                 P2MSEL15_0, P2MSEL15_1,
 865                 P2MSEL14_0, P2MSEL14_1,
 866                 P2MSEL13_0, P2MSEL13_1,
 867                 P2MSEL12_0, P2MSEL12_1,
 868                 P2MSEL11_0, P2MSEL11_1,
 869                 P2MSEL10_0, P2MSEL10_1,
 870                 P2MSEL9_0,  P2MSEL9_1,
 871                 P2MSEL8_0,  P2MSEL8_1,
 872                 P2MSEL7_0,  P2MSEL7_1,
 873                 P2MSEL6_0,  P2MSEL6_1,
 874                 P2MSEL5_0,  P2MSEL5_1,
 875                 P2MSEL4_0,  P2MSEL4_1,
 876                 P2MSEL3_0,  P2MSEL3_1,
 877                 P2MSEL2_0,  P2MSEL2_1,
 878                 P2MSEL1_0,  P2MSEL1_1,
 879                 P2MSEL0_0,  P2MSEL0_1 }
 880         },
 881         {}
 882 };
 883
 884 static struct pinmux_data_reg pinmux_data_regs[] = {
 885         { PINMUX_DATA_REG("PADR", 0xffcc0020, 8) {
 886                 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
 887                 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
 888         },
 889         { PINMUX_DATA_REG("PBDR", 0xffcc0022, 8) {
 890                 PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
 891                 PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA }
 892         },
 893         { PINMUX_DATA_REG("PCDR", 0xffcc0024, 8) {
 894                 PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
 895                 PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
 896         },
 897         { PINMUX_DATA_REG("PDDR", 0xffcc0026, 8) {
 898                 PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
 899                 PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
 900         },
 901         { PINMUX_DATA_REG("PEDR", 0xffcc0028, 8) {
 902                 PE7_DATA, PE6_DATA,
 903                 0, 0, 0, 0, 0, 0 }
 904         },
 905         { PINMUX_DATA_REG("PFDR", 0xffcc002a, 8) {
 906                 PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
 907                 PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
 908         },
 909         { PINMUX_DATA_REG("PGDR", 0xffcc002c, 8) {
 910                 PG7_DATA, PG6_DATA, PG5_DATA, 0,
 911                 0, 0, 0, 0 }
 912         },
 913         { PINMUX_DATA_REG("PHDR", 0xffcc002e, 8) {
 914                 PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
 915                 PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA }
 916         },
 917         { PINMUX_DATA_REG("PJDR", 0xffcc0030, 8) {
 918                 PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
 919                 PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 }
 920         },
 921         { },
 922 };
 923
 924 static struct pinmux_info sh7786_pinmux_info = {
 925         .name = "sh7786_pfc",
 926         .reserved_id = PINMUX_RESERVED,
 927         .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
 928         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
 929         .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
 930         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
 931         .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
 932         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 933
 934         .first_gpio = GPIO_PA7,
 935         .last_gpio = GPIO_FN_FSE,
 936
 937         .gpios = pinmux_gpios,
 938         .cfg_regs = pinmux_config_regs,
 939         .data_regs = pinmux_data_regs,
 940
 941         .gpio_data = pinmux_data,
 942         .gpio_data_size = ARRAY_SIZE(pinmux_data),
 943 };
 944
 945 static int __init plat_pinmux_setup(void)
 946 {
 947         return register_pinmux(&sh7786_pinmux_info);
 948 }
 949
 950 arch_initcall(plat_pinmux_setup);