2 * arch/sh/kernel/cpu/sh4a/clock-sh7723.c
4 * SH7723 clock framework support
6 * Copyright (C) 2009 Magnus Damm
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 #include <linux/init.h>
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <asm/clkdev.h>
26 #include <asm/clock.h>
27 #include <asm/hwblk.h>
28 #include <cpu/sh7723.h>
30 /* SH7723 registers */
31 #define FRQCR 0xa4150000
32 #define VCLKCR 0xa4150004
33 #define SCLKACR 0xa4150008
34 #define SCLKBCR 0xa415000c
35 #define IRDACLKCR 0xa4150018
36 #define PLLCR 0xa4150024
37 #define DLLFRQ 0xa4150050
39 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
40 static struct clk r_clk = {
47 * Default rate for the root input clock, reset this with clk_set_rate()
48 * from the platform code.
50 struct clk extal_clk = {
56 /* The dll multiplies the 32khz r_clk, may be used instead of extal */
57 static unsigned long dll_recalc(struct clk *clk)
61 if (__raw_readl(PLLCR) & 0x1000)
62 mult = __raw_readl(DLLFRQ);
66 return clk->parent->rate * mult;
69 static struct clk_ops dll_clk_ops = {
73 static struct clk dll_clk = {
78 .flags = CLK_ENABLE_ON_INIT,
81 static unsigned long pll_recalc(struct clk *clk)
83 unsigned long mult = 1;
84 unsigned long div = 1;
86 if (__raw_readl(PLLCR) & 0x4000)
87 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
91 return (clk->parent->rate * mult) / div;
94 static struct clk_ops pll_clk_ops = {
98 static struct clk pll_clk = {
102 .flags = CLK_ENABLE_ON_INIT,
105 struct clk *main_clks[] = {
112 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
113 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
115 static struct clk_div_mult_table div4_div_mult_table = {
116 .divisors = divisors,
117 .nr_divisors = ARRAY_SIZE(divisors),
118 .multipliers = multipliers,
119 .nr_multipliers = ARRAY_SIZE(multipliers),
122 static struct clk_div4_table div4_table = {
123 .div_mult_table = &div4_div_mult_table,
126 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
128 #define DIV4(_str, _reg, _bit, _mask, _flags) \
129 SH_CLK_DIV4(_str, &pll_clk, _reg, _bit, _mask, _flags)
131 struct clk div4_clks[DIV4_NR] = {
132 [DIV4_I] = DIV4("cpu_clk", FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
133 [DIV4_U] = DIV4("umem_clk", FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
134 [DIV4_SH] = DIV4("shyway_clk", FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
135 [DIV4_B] = DIV4("bus_clk", FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
136 [DIV4_B3] = DIV4("b3_clk", FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
137 [DIV4_P] = DIV4("peripheral_clk", FRQCR, 0, 0x0dbf, 0),
140 enum { DIV4_IRDA, DIV4_ENABLE_NR };
142 struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
143 [DIV4_IRDA] = DIV4("irda_clk", IRDACLKCR, 0, 0x0dbf, 0),
146 enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
148 struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
149 [DIV4_SIUA] = DIV4("siua_clk", SCLKACR, 0, 0x0dbf, 0),
150 [DIV4_SIUB] = DIV4("siub_clk", SCLKBCR, 0, 0x0dbf, 0),
152 struct clk div6_clks[] = {
153 SH_CLK_DIV6("video_clk", &pll_clk, VCLKCR, 0),
156 #define R_CLK (&r_clk)
157 #define P_CLK (&div4_clks[DIV4_P])
158 #define B_CLK (&div4_clks[DIV4_B])
159 #define U_CLK (&div4_clks[DIV4_U])
160 #define I_CLK (&div4_clks[DIV4_I])
161 #define SH_CLK (&div4_clks[DIV4_SH])
163 static struct clk mstp_clks[] = {
164 /* See page 60 of Datasheet V1.0: Overview -> Block Diagram */
165 SH_HWBLK_CLK("tlb0", -1, I_CLK, HWBLK_TLB, CLK_ENABLE_ON_INIT),
166 SH_HWBLK_CLK("ic0", -1, I_CLK, HWBLK_IC, CLK_ENABLE_ON_INIT),
167 SH_HWBLK_CLK("oc0", -1, I_CLK, HWBLK_OC, CLK_ENABLE_ON_INIT),
168 SH_HWBLK_CLK("l2c0", -1, SH_CLK, HWBLK_L2C, CLK_ENABLE_ON_INIT),
169 SH_HWBLK_CLK("ilmem0", -1, I_CLK, HWBLK_ILMEM, CLK_ENABLE_ON_INIT),
170 SH_HWBLK_CLK("fpu0", -1, I_CLK, HWBLK_FPU, CLK_ENABLE_ON_INIT),
171 SH_HWBLK_CLK("intc0", -1, I_CLK, HWBLK_INTC, CLK_ENABLE_ON_INIT),
172 SH_HWBLK_CLK("dmac0", -1, B_CLK, HWBLK_DMAC0, 0),
173 SH_HWBLK_CLK("sh0", -1, SH_CLK, HWBLK_SHYWAY, CLK_ENABLE_ON_INIT),
174 SH_HWBLK_CLK("hudi0", -1, P_CLK, HWBLK_HUDI, 0),
175 SH_HWBLK_CLK("ubc0", -1, I_CLK, HWBLK_UBC, 0),
176 SH_HWBLK_CLK("tmu012_fck", -1, P_CLK, HWBLK_TMU0, 0),
177 SH_HWBLK_CLK("cmt_fck", -1, R_CLK, HWBLK_CMT, 0),
178 SH_HWBLK_CLK("rwdt0", -1, R_CLK, HWBLK_RWDT, 0),
179 SH_HWBLK_CLK("dmac1", -1, B_CLK, HWBLK_DMAC1, 0),
180 SH_HWBLK_CLK("tmu345_fck", -1, P_CLK, HWBLK_TMU1, 0),
181 SH_HWBLK_CLK("flctl0", -1, P_CLK, HWBLK_FLCTL, 0),
182 SH_HWBLK_CLK("sci_fck", -1, P_CLK, HWBLK_SCIF0, 0),
183 SH_HWBLK_CLK("sci_fck", -1, P_CLK, HWBLK_SCIF1, 0),
184 SH_HWBLK_CLK("sci_fck", -1, P_CLK, HWBLK_SCIF2, 0),
185 SH_HWBLK_CLK("sci_fck", -1, B_CLK, HWBLK_SCIF3, 0),
186 SH_HWBLK_CLK("sci_fck", -1, B_CLK, HWBLK_SCIF4, 0),
187 SH_HWBLK_CLK("sci_fck", -1, B_CLK, HWBLK_SCIF5, 0),
188 SH_HWBLK_CLK("msiof0", -1, B_CLK, HWBLK_MSIOF0, 0),
189 SH_HWBLK_CLK("msiof1", -1, B_CLK, HWBLK_MSIOF1, 0),
190 SH_HWBLK_CLK("meram0", -1, SH_CLK, HWBLK_MERAM, 0),
192 SH_HWBLK_CLK("i2c0", -1, P_CLK, HWBLK_IIC, 0),
193 SH_HWBLK_CLK("rtc0", -1, R_CLK, HWBLK_RTC, 0),
195 SH_HWBLK_CLK("atapi0", -1, SH_CLK, HWBLK_ATAPI, 0),
196 SH_HWBLK_CLK("adc0", -1, P_CLK, HWBLK_ADC, 0),
197 SH_HWBLK_CLK("tpu0", -1, B_CLK, HWBLK_TPU, 0),
198 SH_HWBLK_CLK("irda0", -1, P_CLK, HWBLK_IRDA, 0),
199 SH_HWBLK_CLK("tsif0", -1, B_CLK, HWBLK_TSIF, 0),
200 SH_HWBLK_CLK("icb0", -1, B_CLK, HWBLK_ICB, CLK_ENABLE_ON_INIT),
201 SH_HWBLK_CLK("sdhi0", -1, B_CLK, HWBLK_SDHI0, 0),
202 SH_HWBLK_CLK("sdhi1", -1, B_CLK, HWBLK_SDHI1, 0),
203 SH_HWBLK_CLK("keysc0", -1, R_CLK, HWBLK_KEYSC, 0),
204 SH_HWBLK_CLK("usb0", -1, B_CLK, HWBLK_USB, 0),
205 SH_HWBLK_CLK("2dg0", -1, B_CLK, HWBLK_2DG, 0),
206 SH_HWBLK_CLK("siu0", -1, B_CLK, HWBLK_SIU, 0),
207 SH_HWBLK_CLK("veu1", -1, B_CLK, HWBLK_VEU2H1, 0),
208 SH_HWBLK_CLK("vou0", -1, B_CLK, HWBLK_VOU, 0),
209 SH_HWBLK_CLK("beu0", -1, B_CLK, HWBLK_BEU, 0),
210 SH_HWBLK_CLK("ceu0", -1, B_CLK, HWBLK_CEU, 0),
211 SH_HWBLK_CLK("veu0", -1, B_CLK, HWBLK_VEU2H0, 0),
212 SH_HWBLK_CLK("vpu0", -1, B_CLK, HWBLK_VPU, 0),
213 SH_HWBLK_CLK("lcdc0", -1, B_CLK, HWBLK_LCDC, 0),
216 static struct clk_lookup lookups[] = {
219 .dev_id = "sh_tmu.0",
221 .clk = &mstp_clks[HWBLK_TMU0],
224 .dev_id = "sh_tmu.1",
226 .clk = &mstp_clks[HWBLK_TMU0],
229 .dev_id = "sh_tmu.2",
231 .clk = &mstp_clks[HWBLK_TMU0],
234 .dev_id = "sh_tmu.3",
236 .clk = &mstp_clks[HWBLK_TMU1],
239 .dev_id = "sh_tmu.4",
241 .clk = &mstp_clks[HWBLK_TMU1],
244 .dev_id = "sh_tmu.5",
246 .clk = &mstp_clks[HWBLK_TMU1],
249 .dev_id = "sh-sci.0",
251 .clk = &mstp_clks[HWBLK_SCIF0],
254 .dev_id = "sh-sci.1",
256 .clk = &mstp_clks[HWBLK_SCIF1],
259 .dev_id = "sh-sci.2",
261 .clk = &mstp_clks[HWBLK_SCIF2],
264 .dev_id = "sh-sci.3",
266 .clk = &mstp_clks[HWBLK_SCIF3],
269 .dev_id = "sh-sci.4",
271 .clk = &mstp_clks[HWBLK_SCIF4],
274 .dev_id = "sh-sci.5",
276 .clk = &mstp_clks[HWBLK_SCIF5],
280 int __init arch_clk_init(void)
284 /* autodetect extal or dll configuration */
285 if (__raw_readl(PLLCR) & 0x1000)
286 pll_clk.parent = &dll_clk;
288 pll_clk.parent = &extal_clk;
290 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
291 ret |= clk_register(main_clks[k]);
293 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
296 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
299 ret = sh_clk_div4_enable_register(div4_enable_clks,
300 DIV4_ENABLE_NR, &div4_table);
303 ret = sh_clk_div4_reparent_register(div4_reparent_clks,
304 DIV4_REPARENT_NR, &div4_table);
307 ret = sh_clk_div6_register(div6_clks, ARRAY_SIZE(div6_clks));
310 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);