2 * arch/sh/kernel/cpu/sh4/probe.c
4 * CPU Subtype Probing for SH-4.
6 * Copyright (C) 2001 - 2007 Paul Mundt
7 * Copyright (C) 2003 Richard Curnow
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
15 #include <asm/processor.h>
16 #include <asm/cache.h>
18 int __init detect_cpu_and_cache_system(void)
20 unsigned long pvr, prr, cvr;
23 static unsigned long sizes[16] = {
31 pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff;
32 prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
33 cvr = (ctrl_inl(CCN_CVR));
36 * Setup some sane SH-4 defaults for the icache
38 boot_cpu_data.icache.way_incr = (1 << 13);
39 boot_cpu_data.icache.entry_shift = 5;
40 boot_cpu_data.icache.sets = 256;
41 boot_cpu_data.icache.ways = 1;
42 boot_cpu_data.icache.linesz = L1_CACHE_BYTES;
45 * And again for the dcache ..
47 boot_cpu_data.dcache.way_incr = (1 << 14);
48 boot_cpu_data.dcache.entry_shift = 5;
49 boot_cpu_data.dcache.sets = 512;
50 boot_cpu_data.dcache.ways = 1;
51 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
53 /* We don't know the chip cut */
54 boot_cpu_data.cut_major = boot_cpu_data.cut_minor = -1;
57 * Setup some generic flags we can probe on SH-4A parts
59 if (((pvr >> 16) & 0xff) == 0x10) {
60 if ((cvr & 0x10000000) == 0)
61 boot_cpu_data.flags |= CPU_HAS_DSP;
63 boot_cpu_data.flags |= CPU_HAS_LLSC | CPU_HAS_PERF_COUNTER;
64 boot_cpu_data.cut_major = pvr & 0x7f;
66 boot_cpu_data.icache.ways = 4;
67 boot_cpu_data.dcache.ways = 4;
69 /* And some SH-4 defaults.. */
70 boot_cpu_data.flags |= CPU_HAS_PTEA;
73 /* FPU detection works for everyone */
74 if ((cvr & 0x20000000))
75 boot_cpu_data.flags |= CPU_HAS_FPU;
77 /* Mask off the upper chip ID */
81 * Probe the underlying processor version/revision and
82 * adjust cpu_data setup accordingly.
86 boot_cpu_data.type = CPU_SH7750;
87 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG |
91 boot_cpu_data.type = CPU_SH7750S;
92 boot_cpu_data.flags |= CPU_HAS_P2_FLUSH_BUG |
96 boot_cpu_data.type = CPU_SH7751;
100 boot_cpu_data.type = CPU_SH7770;
105 boot_cpu_data.type = CPU_SH7781;
106 else if (prr == 0xa1)
107 boot_cpu_data.type = CPU_SH7763;
109 boot_cpu_data.type = CPU_SH7780;
115 boot_cpu_data.type = CPU_SH7343;
119 boot_cpu_data.type = CPU_SH7785;
122 boot_cpu_data.type = CPU_SH7786;
123 boot_cpu_data.flags |= CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE;
129 boot_cpu_data.type = CPU_SH7723;
130 boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
133 boot_cpu_data.type = CPU_SH7366;
137 boot_cpu_data.type = CPU_SH7722;
142 boot_cpu_data.type = CPU_SH7724;
143 boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
145 case 0x4000: /* 1st cut */
146 case 0x4001: /* 2nd cut */
147 boot_cpu_data.type = CPU_SHX3;
150 boot_cpu_data.type = CPU_SH4_501;
151 boot_cpu_data.icache.ways = 2;
152 boot_cpu_data.dcache.ways = 2;
155 boot_cpu_data.type = CPU_SH4_202;
156 boot_cpu_data.icache.ways = 2;
157 boot_cpu_data.dcache.ways = 2;
159 case 0x500 ... 0x501:
162 boot_cpu_data.type = CPU_SH7750R;
165 boot_cpu_data.type = CPU_SH7751R;
168 boot_cpu_data.type = CPU_SH7760;
172 boot_cpu_data.icache.ways = 2;
173 boot_cpu_data.dcache.ways = 2;
177 boot_cpu_data.type = CPU_SH_NONE;
182 * On anything that's not a direct-mapped cache, look to the CVR
183 * for I/D-cache specifics.
185 if (boot_cpu_data.icache.ways > 1) {
186 size = sizes[(cvr >> 20) & 0xf];
187 boot_cpu_data.icache.way_incr = (size >> 1);
188 boot_cpu_data.icache.sets = (size >> 6);
192 /* And the rest of the D-cache */
193 if (boot_cpu_data.dcache.ways > 1) {
194 size = sizes[(cvr >> 16) & 0xf];
195 boot_cpu_data.dcache.way_incr = (size >> 1);
196 boot_cpu_data.dcache.sets = (size >> 6);
200 * SH-4A's have an optional PIPT L2.
202 if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
204 * Verify that it really has something hooked up, this
205 * is the safety net for CPUs that have optional L2
206 * support yet do not implement it.
208 if ((cvr & 0xf) == 0)
209 boot_cpu_data.flags &= ~CPU_HAS_L2_CACHE;
212 * Silicon and specifications have clearly never
218 * Size calculation is much more sensible
219 * than it is for the L1.
221 * Sizes are 128KB, 258KB, 512KB, and 1MB.
223 size = (cvr & 0xf) << 17;
225 boot_cpu_data.scache.way_incr = (1 << 16);
226 boot_cpu_data.scache.entry_shift = 5;
227 boot_cpu_data.scache.ways = 4;
228 boot_cpu_data.scache.linesz = L1_CACHE_BYTES;
230 boot_cpu_data.scache.entry_mask =
231 (boot_cpu_data.scache.way_incr -
232 boot_cpu_data.scache.linesz);
234 boot_cpu_data.scache.sets = size /
235 (boot_cpu_data.scache.linesz *
236 boot_cpu_data.scache.ways);
238 boot_cpu_data.scache.way_size =
239 (boot_cpu_data.scache.sets *
240 boot_cpu_data.scache.linesz);