2 * SH7203 and SH7263 Setup
4 * Copyright (C) 2007 - 2009 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
14 #include <linux/sh_cmt.h>
15 #include <linux/sh_mtu2.h>
21 /* interrupt sources */
22 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
23 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
24 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
25 USB, LCDC, CMT0, CMT1, BSC, WDT,
27 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
28 MTU3_ABCD, MTU4_ABCD, MTU2_TCI3V, MTU2_TCI4V,
32 IIC30, IIC31, IIC32, IIC33,
33 SCIF0, SCIF1, SCIF2, SCIF3,
37 SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
39 /* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */
40 ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1,
43 /* interrupt groups */
47 static struct intc_vect vectors[] __initdata = {
48 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
49 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
50 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
51 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
52 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
53 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
54 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
55 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
56 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
57 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
58 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
59 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
60 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
61 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
62 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
63 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
64 INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
65 INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
66 INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
67 INTC_IRQ(MTU0_ABCD, 146), INTC_IRQ(MTU0_ABCD, 147),
68 INTC_IRQ(MTU0_ABCD, 148), INTC_IRQ(MTU0_ABCD, 149),
69 INTC_IRQ(MTU0_VEF, 150),
70 INTC_IRQ(MTU0_VEF, 151), INTC_IRQ(MTU0_VEF, 152),
71 INTC_IRQ(MTU1_AB, 153), INTC_IRQ(MTU1_AB, 154),
72 INTC_IRQ(MTU1_VU, 155), INTC_IRQ(MTU1_VU, 156),
73 INTC_IRQ(MTU2_AB, 157), INTC_IRQ(MTU2_AB, 158),
74 INTC_IRQ(MTU2_VU, 159), INTC_IRQ(MTU2_VU, 160),
75 INTC_IRQ(MTU3_ABCD, 161), INTC_IRQ(MTU3_ABCD, 162),
76 INTC_IRQ(MTU3_ABCD, 163), INTC_IRQ(MTU3_ABCD, 164),
77 INTC_IRQ(MTU2_TCI3V, 165),
78 INTC_IRQ(MTU4_ABCD, 166), INTC_IRQ(MTU4_ABCD, 167),
79 INTC_IRQ(MTU4_ABCD, 168), INTC_IRQ(MTU4_ABCD, 169),
80 INTC_IRQ(MTU2_TCI4V, 170),
81 INTC_IRQ(ADC_ADI, 171),
82 INTC_IRQ(IIC30, 172), INTC_IRQ(IIC30, 173),
83 INTC_IRQ(IIC30, 174), INTC_IRQ(IIC30, 175),
85 INTC_IRQ(IIC31, 177), INTC_IRQ(IIC31, 178),
86 INTC_IRQ(IIC31, 179), INTC_IRQ(IIC31, 180),
88 INTC_IRQ(IIC32, 182), INTC_IRQ(IIC32, 183),
89 INTC_IRQ(IIC32, 184), INTC_IRQ(IIC32, 185),
91 INTC_IRQ(IIC33, 187), INTC_IRQ(IIC33, 188),
92 INTC_IRQ(IIC33, 189), INTC_IRQ(IIC33, 190),
94 INTC_IRQ(SCIF0, 192), INTC_IRQ(SCIF0, 193),
95 INTC_IRQ(SCIF0, 194), INTC_IRQ(SCIF0, 195),
96 INTC_IRQ(SCIF1, 196), INTC_IRQ(SCIF1, 197),
97 INTC_IRQ(SCIF1, 198), INTC_IRQ(SCIF1, 199),
98 INTC_IRQ(SCIF2, 200), INTC_IRQ(SCIF2, 201),
99 INTC_IRQ(SCIF2, 202), INTC_IRQ(SCIF2, 203),
100 INTC_IRQ(SCIF3, 204), INTC_IRQ(SCIF3, 205),
101 INTC_IRQ(SCIF3, 206), INTC_IRQ(SCIF3, 207),
102 INTC_IRQ(SSU0, 208), INTC_IRQ(SSU0, 209),
104 INTC_IRQ(SSU1, 211), INTC_IRQ(SSU1, 212),
106 INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215),
107 INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217),
108 INTC_IRQ(FLCTL, 224), INTC_IRQ(FLCTL, 225),
109 INTC_IRQ(FLCTL, 226), INTC_IRQ(FLCTL, 227),
110 INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232),
112 INTC_IRQ(RCAN0, 234), INTC_IRQ(RCAN0, 235),
113 INTC_IRQ(RCAN0, 236), INTC_IRQ(RCAN0, 237),
114 INTC_IRQ(RCAN0, 238),
115 INTC_IRQ(RCAN1, 239), INTC_IRQ(RCAN1, 240),
116 INTC_IRQ(RCAN1, 241), INTC_IRQ(RCAN1, 242),
117 INTC_IRQ(RCAN1, 243),
119 /* SH7263-specific trash */
120 #ifdef CONFIG_CPU_SUBTYPE_SH7263
121 INTC_IRQ(ROMDEC, 218), INTC_IRQ(ROMDEC, 219),
122 INTC_IRQ(ROMDEC, 220), INTC_IRQ(ROMDEC, 221),
123 INTC_IRQ(ROMDEC, 222), INTC_IRQ(ROMDEC, 223),
125 INTC_IRQ(SDHI, 228), INTC_IRQ(SDHI, 229),
128 INTC_IRQ(SRC, 244), INTC_IRQ(SRC, 245),
135 static struct intc_group groups[] __initdata = {
136 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
137 PINT4, PINT5, PINT6, PINT7),
140 static struct intc_prio_reg prio_registers[] __initdata = {
141 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
142 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
143 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
144 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
145 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
146 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },
147 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
148 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU1_AB, MTU1_VU, MTU2_AB,
150 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD,
152 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } },
153 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } },
154 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } },
155 #ifdef CONFIG_CPU_SUBTYPE_SH7203
156 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
158 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } },
159 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } },
161 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
162 SSI3_SSII, ROMDEC } },
163 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } },
164 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, SRC, IEBI, 0 } },
168 static struct intc_mask_reg mask_registers[] __initdata = {
169 { 0xfffe0808, 0, 16, /* PINTER */
170 { 0, 0, 0, 0, 0, 0, 0, 0,
171 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
174 static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
175 mask_registers, prio_registers, NULL);
177 static struct plat_sci_port sci_platform_data[] = {
179 .mapbase = 0xfffe8000,
180 .flags = UPF_BOOT_AUTOCONF,
182 .irqs = { 192, 192, 192, 192 },
184 .mapbase = 0xfffe8800,
185 .flags = UPF_BOOT_AUTOCONF,
187 .irqs = { 196, 196, 196, 196 },
189 .mapbase = 0xfffe9000,
190 .flags = UPF_BOOT_AUTOCONF,
192 .irqs = { 200, 200, 200, 200 },
194 .mapbase = 0xfffe9800,
195 .flags = UPF_BOOT_AUTOCONF,
197 .irqs = { 204, 204, 204, 204 },
203 static struct platform_device sci_device = {
207 .platform_data = sci_platform_data,
211 static struct sh_cmt_config cmt0_platform_data = {
213 .channel_offset = 0x02,
216 .clockevent_rating = 125,
217 .clocksource_rating = 0, /* disabled due to code generation issues */
220 static struct resource cmt0_resources[] = {
225 .flags = IORESOURCE_MEM,
229 .flags = IORESOURCE_IRQ,
233 static struct platform_device cmt0_device = {
237 .platform_data = &cmt0_platform_data,
239 .resource = cmt0_resources,
240 .num_resources = ARRAY_SIZE(cmt0_resources),
243 static struct sh_cmt_config cmt1_platform_data = {
245 .channel_offset = 0x08,
248 .clockevent_rating = 125,
249 .clocksource_rating = 0, /* disabled due to code generation issues */
252 static struct resource cmt1_resources[] = {
257 .flags = IORESOURCE_MEM,
261 .flags = IORESOURCE_IRQ,
265 static struct platform_device cmt1_device = {
269 .platform_data = &cmt1_platform_data,
271 .resource = cmt1_resources,
272 .num_resources = ARRAY_SIZE(cmt1_resources),
275 static struct sh_mtu2_config mtu2_0_platform_data = {
277 .channel_offset = -0x80,
280 .clockevent_rating = 200,
283 static struct resource mtu2_0_resources[] = {
288 .flags = IORESOURCE_MEM,
292 .flags = IORESOURCE_IRQ,
296 static struct platform_device mtu2_0_device = {
300 .platform_data = &mtu2_0_platform_data,
302 .resource = mtu2_0_resources,
303 .num_resources = ARRAY_SIZE(mtu2_0_resources),
306 static struct sh_mtu2_config mtu2_1_platform_data = {
308 .channel_offset = -0x100,
311 .clockevent_rating = 200,
314 static struct resource mtu2_1_resources[] = {
319 .flags = IORESOURCE_MEM,
323 .flags = IORESOURCE_IRQ,
327 static struct platform_device mtu2_1_device = {
331 .platform_data = &mtu2_1_platform_data,
333 .resource = mtu2_1_resources,
334 .num_resources = ARRAY_SIZE(mtu2_1_resources),
337 static struct resource rtc_resources[] = {
340 .end = 0xffff2000 + 0x58 - 1,
341 .flags = IORESOURCE_IO,
344 /* Shared Period/Carry/Alarm IRQ */
346 .flags = IORESOURCE_IRQ,
350 static struct platform_device rtc_device = {
353 .num_resources = ARRAY_SIZE(rtc_resources),
354 .resource = rtc_resources,
357 static struct platform_device *sh7203_devices[] __initdata = {
366 static int __init sh7203_devices_setup(void)
368 return platform_add_devices(sh7203_devices,
369 ARRAY_SIZE(sh7203_devices));
371 __initcall(sh7203_devices_setup);
373 void __init plat_irq_setup(void)
375 register_intc_controller(&intc_desc);
378 static struct platform_device *sh7203_early_devices[] __initdata = {
385 #define STBCR3 0xfffe0408
386 #define STBCR4 0xfffe040c
388 void __init plat_early_device_setup(void)
390 /* enable CMT clock */
391 __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
393 /* enable MTU2 clock */
394 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
396 early_platform_add_devices(sh7203_early_devices,
397 ARRAY_SIZE(sh7203_early_devices));