arch/sh/kernel/cpu/clock-cpg.c

   1 #include <linux/clk.h>
   2 #include <linux/compiler.h>
   3 #include <linux/slab.h>
   4 #include <linux/io.h>
   5 #include <asm/clkdev.h>
   6 #include <asm/clock.h>
   7
   8 static int sh_clk_mstp32_enable(struct clk *clk)
   9 {
  10         __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit),
  11                      clk->enable_reg);
  12         return 0;
  13 }
  14
  15 static void sh_clk_mstp32_disable(struct clk *clk)
  16 {
  17         __raw_writel(__raw_readl(clk->enable_reg) | (1 << clk->enable_bit),
  18                      clk->enable_reg);
  19 }
  20
  21 static struct clk_ops sh_clk_mstp32_clk_ops = {
  22         .enable         = sh_clk_mstp32_enable,
  23         .disable        = sh_clk_mstp32_disable,
  24         .recalc         = followparent_recalc,
  25 };
  26
  27 int __init sh_clk_mstp32_register(struct clk *clks, int nr)
  28 {
  29         struct clk *clkp;
  30         int ret = 0;
  31         int k;
  32
  33         for (k = 0; !ret && (k < nr); k++) {
  34                 clkp = clks + k;
  35                 clkp->ops = &sh_clk_mstp32_clk_ops;
  36                 ret |= clk_register(clkp);
  37         }
  38
  39         return ret;
  40 }
  41
  42 static long sh_clk_div_round_rate(struct clk *clk, unsigned long rate)
  43 {
  44         return clk_rate_table_round(clk, clk->freq_table, rate);
  45 }
  46
  47 static int sh_clk_div6_divisors[64] = {
  48         1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16,
  49         17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
  50         33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
  51         49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64
  52 };
  53
  54 static struct clk_div_mult_table sh_clk_div6_table = {
  55         .divisors = sh_clk_div6_divisors,
  56         .nr_divisors = ARRAY_SIZE(sh_clk_div6_divisors),
  57 };
  58
  59 static unsigned long sh_clk_div6_recalc(struct clk *clk)
  60 {
  61         struct clk_div_mult_table *table = &sh_clk_div6_table;
  62         unsigned int idx;
  63
  64         clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
  65                              table, NULL);
  66
  67         idx = __raw_readl(clk->enable_reg) & 0x003f;
  68
  69         return clk->freq_table[idx].frequency;
  70 }
  71
  72 static int sh_clk_div6_set_rate(struct clk *clk,
  73                                 unsigned long rate, int algo_id)
  74 {
  75         unsigned long value;
  76         int idx;
  77
  78         idx = clk_rate_table_find(clk, clk->freq_table, rate);
  79         if (idx < 0)
  80                 return idx;
  81
  82         value = __raw_readl(clk->enable_reg);
  83         value &= ~0x3f;
  84         value |= idx;
  85         __raw_writel(value, clk->enable_reg);
  86         return 0;
  87 }
  88
  89 static int sh_clk_div6_enable(struct clk *clk)
  90 {
  91         unsigned long value;
  92         int ret;
  93
  94         ret = sh_clk_div6_set_rate(clk, clk->rate, 0);
  95         if (ret == 0) {
  96                 value = __raw_readl(clk->enable_reg);
  97                 value &= ~0x100; /* clear stop bit to enable clock */
  98                 __raw_writel(value, clk->enable_reg);
  99         }
 100         return ret;
 101 }
 102
 103 static void sh_clk_div6_disable(struct clk *clk)
 104 {
 105         unsigned long value;
 106
 107         value = __raw_readl(clk->enable_reg);
 108         value |= 0x100; /* stop clock */
 109         value |= 0x3f; /* VDIV bits must be non-zero, overwrite divider */
 110         __raw_writel(value, clk->enable_reg);
 111 }
 112
 113 static struct clk_ops sh_clk_div6_clk_ops = {
 114         .recalc         = sh_clk_div6_recalc,
 115         .round_rate     = sh_clk_div_round_rate,
 116         .set_rate       = sh_clk_div6_set_rate,
 117         .enable         = sh_clk_div6_enable,
 118         .disable        = sh_clk_div6_disable,
 119 };
 120
 121 int __init sh_clk_div6_register(struct clk *clks, int nr)
 122 {
 123         struct clk *clkp;
 124         void *freq_table;
 125         int nr_divs = sh_clk_div6_table.nr_divisors;
 126         int freq_table_size = sizeof(struct cpufreq_frequency_table);
 127         int ret = 0;
 128         int k;
 129
 130         freq_table_size *= (nr_divs + 1);
 131         freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
 132         if (!freq_table) {
 133                 pr_err("sh_clk_div6_register: unable to alloc memory\n");
 134                 return -ENOMEM;
 135         }
 136
 137         for (k = 0; !ret && (k < nr); k++) {
 138                 clkp = clks + k;
 139
 140                 clkp->ops = &sh_clk_div6_clk_ops;
 141                 clkp->id = -1;
 142                 clkp->freq_table = freq_table + (k * freq_table_size);
 143                 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
 144
 145                 ret = clk_register(clkp);
 146         }
 147
 148         return ret;
 149 }
 150
 151 static unsigned long sh_clk_div4_recalc(struct clk *clk)
 152 {
 153         struct clk_div4_table *d4t = clk->priv;
 154         struct clk_div_mult_table *table = d4t->div_mult_table;
 155         unsigned int idx;
 156
 157         clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
 158                              table, &clk->arch_flags);
 159
 160         idx = (__raw_readl(clk->enable_reg) >> clk->enable_bit) & 0x000f;
 161
 162         return clk->freq_table[idx].frequency;
 163 }
 164
 165 static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
 166 {
 167         struct clk_div4_table *d4t = clk->priv;
 168         struct clk_div_mult_table *table = d4t->div_mult_table;
 169         u32 value;
 170         int ret;
 171
 172         /* we really need a better way to determine parent index, but for
 173          * now assume internal parent comes with CLK_ENABLE_ON_INIT set,
 174          * no CLK_ENABLE_ON_INIT means external clock...
 175          */
 176
 177         if (parent->flags & CLK_ENABLE_ON_INIT)
 178                 value = __raw_readl(clk->enable_reg) & ~(1 << 7);
 179         else
 180                 value = __raw_readl(clk->enable_reg) | (1 << 7);
 181
 182         ret = clk_reparent(clk, parent);
 183         if (ret < 0)
 184                 return ret;
 185
 186         __raw_writel(value, clk->enable_reg);
 187
 188         /* Rebiuld the frequency table */
 189         clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
 190                              table, &clk->arch_flags);
 191
 192         return 0;
 193 }
 194
 195 static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id)
 196 {
 197         struct clk_div4_table *d4t = clk->priv;
 198         unsigned long value;
 199         int idx = clk_rate_table_find(clk, clk->freq_table, rate);
 200         if (idx < 0)
 201                 return idx;
 202
 203         value = __raw_readl(clk->enable_reg);
 204         value &= ~(0xf << clk->enable_bit);
 205         value |= (idx << clk->enable_bit);
 206         __raw_writel(value, clk->enable_reg);
 207
 208         if (d4t->kick)
 209                 d4t->kick(clk);
 210
 211         return 0;
 212 }
 213
 214 static int sh_clk_div4_enable(struct clk *clk)
 215 {
 216         __raw_writel(__raw_readl(clk->enable_reg) & ~(1 << 8), clk->enable_reg);
 217         return 0;
 218 }
 219
 220 static void sh_clk_div4_disable(struct clk *clk)
 221 {
 222         __raw_writel(__raw_readl(clk->enable_reg) | (1 << 8), clk->enable_reg);
 223 }
 224
 225 static struct clk_ops sh_clk_div4_clk_ops = {
 226         .recalc         = sh_clk_div4_recalc,
 227         .set_rate       = sh_clk_div4_set_rate,
 228         .round_rate     = sh_clk_div_round_rate,
 229 };
 230
 231 static struct clk_ops sh_clk_div4_enable_clk_ops = {
 232         .recalc         = sh_clk_div4_recalc,
 233         .set_rate       = sh_clk_div4_set_rate,
 234         .round_rate     = sh_clk_div_round_rate,
 235         .enable         = sh_clk_div4_enable,
 236         .disable        = sh_clk_div4_disable,
 237 };
 238
 239 static struct clk_ops sh_clk_div4_reparent_clk_ops = {
 240         .recalc         = sh_clk_div4_recalc,
 241         .set_rate       = sh_clk_div4_set_rate,
 242         .round_rate     = sh_clk_div_round_rate,
 243         .enable         = sh_clk_div4_enable,
 244         .disable        = sh_clk_div4_disable,
 245         .set_parent     = sh_clk_div4_set_parent,
 246 };
 247
 248 static int __init sh_clk_div4_register_ops(struct clk *clks, int nr,
 249                         struct clk_div4_table *table, struct clk_ops *ops)
 250 {
 251         struct clk *clkp;
 252         void *freq_table;
 253         int nr_divs = table->div_mult_table->nr_divisors;
 254         int freq_table_size = sizeof(struct cpufreq_frequency_table);
 255         int ret = 0;
 256         int k;
 257
 258         freq_table_size *= (nr_divs + 1);
 259         freq_table = kzalloc(freq_table_size * nr, GFP_KERNEL);
 260         if (!freq_table) {
 261                 pr_err("sh_clk_div4_register: unable to alloc memory\n");
 262                 return -ENOMEM;
 263         }
 264
 265         for (k = 0; !ret && (k < nr); k++) {
 266                 clkp = clks + k;
 267
 268                 clkp->ops = ops;
 269                 clkp->id = -1;
 270                 clkp->priv = table;
 271
 272                 clkp->freq_table = freq_table + (k * freq_table_size);
 273                 clkp->freq_table[nr_divs].frequency = CPUFREQ_TABLE_END;
 274
 275                 ret = clk_register(clkp);
 276         }
 277
 278         return ret;
 279 }
 280
 281 int __init sh_clk_div4_register(struct clk *clks, int nr,
 282                                 struct clk_div4_table *table)
 283 {
 284         return sh_clk_div4_register_ops(clks, nr, table, &sh_clk_div4_clk_ops);
 285 }
 286
 287 int __init sh_clk_div4_enable_register(struct clk *clks, int nr,
 288                                 struct clk_div4_table *table)
 289 {
 290         return sh_clk_div4_register_ops(clks, nr, table,
 291                                         &sh_clk_div4_enable_clk_ops);
 292 }
 293
 294 int __init sh_clk_div4_reparent_register(struct clk *clks, int nr,
 295                                 struct clk_div4_table *table)
 296 {
 297         return sh_clk_div4_register_ops(clks, nr, table,
 298                                         &sh_clk_div4_reparent_clk_ops);
 299 }
 300
 301 #ifdef CONFIG_SH_CLK_CPG_LEGACY
 302 static struct clk master_clk = {
 303         .flags          = CLK_ENABLE_ON_INIT,
 304         .rate           = CONFIG_SH_PCLK_FREQ,
 305 };
 306
 307 static struct clk peripheral_clk = {
 308         .parent         = &master_clk,
 309         .flags          = CLK_ENABLE_ON_INIT,
 310 };
 311
 312 static struct clk bus_clk = {
 313         .parent         = &master_clk,
 314         .flags          = CLK_ENABLE_ON_INIT,
 315 };
 316
 317 static struct clk cpu_clk = {
 318         .parent         = &master_clk,
 319         .flags          = CLK_ENABLE_ON_INIT,
 320 };
 321
 322 /*
 323  * The ordering of these clocks matters, do not change it.
 324  */
 325 static struct clk *onchip_clocks[] = {
 326         &master_clk,
 327         &peripheral_clk,
 328         &bus_clk,
 329         &cpu_clk,
 330 };
 331
 332 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
 333
 334 static struct clk_lookup lookups[] = {
 335         /* main clocks */
 336         CLKDEV_CON_ID("master_clk", &master_clk),
 337         CLKDEV_CON_ID("peripheral_clk", &peripheral_clk),
 338         CLKDEV_CON_ID("bus_clk", &bus_clk),
 339         CLKDEV_CON_ID("cpu_clk", &cpu_clk),
 340 };
 341
 342 int __init __deprecated cpg_clk_init(void)
 343 {
 344         int i, ret = 0;
 345
 346         for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++) {
 347                 struct clk *clk = onchip_clocks[i];
 348                 arch_init_clk_ops(&clk->ops, i);
 349                 if (clk->ops)
 350                         ret |= clk_register(clk);
 351         }
 352
 353         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 354
 355         clk_add_alias("tmu_fck", NULL, "peripheral_clk", NULL);
 356         clk_add_alias("mtu2_fck", NULL, "peripheral_clk", NULL);
 357         clk_add_alias("cmt_fck", NULL, "peripheral_clk", NULL);
 358         clk_add_alias("sci_ick", NULL, "peripheral_clk", NULL);
 359
 360         return ret;
 361 }
 362
 363 /*
 364  * Placeholder for compatability, until the lazy CPUs do this
 365  * on their own.
 366  */
 367 int __init __weak arch_clk_init(void)
 368 {
 369         return cpg_clk_init();
 370 }
 371 #endif /* CONFIG_SH_CPG_CLK_LEGACY */