2 * arch/sh/drivers/dma/dma-sh.c
4 * SuperH On-chip DMAC Support
6 * Copyright (C) 2000 Takashi YOSHII
7 * Copyright (C) 2003, 2004 Paul Mundt
8 * Copyright (C) 2005 Andriy Skulysh
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
15 #include <linux/init.h>
16 #include <linux/irq.h>
17 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <asm/dreamcast/dma.h>
20 #include <asm/signal.h>
26 static inline unsigned int get_dmte_irq(unsigned int chan)
31 * Normally we could just do DMTE0_IRQ + chan outright, though in the
32 * case of the 7751R, the DMTE IRQs for channels > 4 start right above
36 irq = DMTE0_IRQ + chan;
39 irq = DMTE4_IRQ + chan - 4;
47 * We determine the correct shift size based off of the CHCR transmit size
48 * for the given channel. Since we know that it will take:
50 * info->count >> ts_shift[transmit_size]
52 * iterations to complete the transfer.
54 static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
56 u32 chcr = ctrl_inl(CHCR[chan->chan]);
58 return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
62 * The transfer end interrupt must read the chcr register to end the
63 * hardware interrupt active condition.
64 * Besides that it needs to waken any waiting process, which should handle
65 * setting up the next transfer.
67 static irqreturn_t dma_tei(int irq, void *dev_id, struct pt_regs *regs)
69 struct dma_channel *chan = (struct dma_channel *)dev_id;
72 chcr = ctrl_inl(CHCR[chan->chan]);
74 if (!(chcr & CHCR_TE))
77 chcr &= ~(CHCR_IE | CHCR_DE);
78 ctrl_outl(chcr, CHCR[chan->chan]);
80 wake_up(&chan->wait_queue);
85 static int sh_dmac_request_dma(struct dma_channel *chan)
89 snprintf(name, sizeof(name), "DMAC Transfer End (Channel %d)",
92 return request_irq(get_dmte_irq(chan->chan), dma_tei,
93 SA_INTERRUPT, name, chan);
96 static void sh_dmac_free_dma(struct dma_channel *chan)
98 free_irq(get_dmte_irq(chan->chan), chan);
102 sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
105 chcr = RS_DUAL | CHCR_IE;
107 if (chcr & CHCR_IE) {
109 chan->flags |= DMA_TEI_CAPABLE;
111 chan->flags &= ~DMA_TEI_CAPABLE;
114 ctrl_outl(chcr, CHCR[chan->chan]);
116 chan->flags |= DMA_CONFIGURED;
119 static void sh_dmac_enable_dma(struct dma_channel *chan)
124 chcr = ctrl_inl(CHCR[chan->chan]);
127 if (chan->flags & DMA_TEI_CAPABLE)
130 ctrl_outl(chcr, CHCR[chan->chan]);
132 if (chan->flags & DMA_TEI_CAPABLE) {
133 irq = get_dmte_irq(chan->chan);
138 static void sh_dmac_disable_dma(struct dma_channel *chan)
143 if (chan->flags & DMA_TEI_CAPABLE) {
144 irq = get_dmte_irq(chan->chan);
148 chcr = ctrl_inl(CHCR[chan->chan]);
149 chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
150 ctrl_outl(chcr, CHCR[chan->chan]);
153 static int sh_dmac_xfer_dma(struct dma_channel *chan)
156 * If we haven't pre-configured the channel with special flags, use
159 if (unlikely(!(chan->flags & DMA_CONFIGURED)))
160 sh_dmac_configure_channel(chan, 0);
162 sh_dmac_disable_dma(chan);
165 * Single-address mode usage note!
167 * It's important that we don't accidentally write any value to SAR/DAR
168 * (this includes 0) that hasn't been directly specified by the user if
169 * we're in single-address mode.
171 * In this case, only one address can be defined, anything else will
172 * result in a DMA address error interrupt (at least on the SH-4),
173 * which will subsequently halt the transfer.
175 * Channel 2 on the Dreamcast is a special case, as this is used for
176 * cascading to the PVR2 DMAC. In this case, we still need to write
177 * SAR and DAR, regardless of value, in order for cascading to work.
179 if (chan->sar || (mach_is_dreamcast() &&
180 chan->chan == PVR2_CASCADE_CHAN))
181 ctrl_outl(chan->sar, SAR[chan->chan]);
182 if (chan->dar || (mach_is_dreamcast() &&
183 chan->chan == PVR2_CASCADE_CHAN))
184 ctrl_outl(chan->dar, DAR[chan->chan]);
186 ctrl_outl(chan->count >> calc_xmit_shift(chan), DMATCR[chan->chan]);
188 sh_dmac_enable_dma(chan);
193 static int sh_dmac_get_dma_residue(struct dma_channel *chan)
195 if (!(ctrl_inl(CHCR[chan->chan]) & CHCR_DE))
198 return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan);
201 #ifdef CONFIG_CPU_SUBTYPE_SH7780
202 #define dmaor_read_reg() ctrl_inw(DMAOR)
203 #define dmaor_write_reg(data) ctrl_outw(data, DMAOR)
205 #define dmaor_read_reg() ctrl_inl(DMAOR)
206 #define dmaor_write_reg(data) ctrl_outl(data, DMAOR)
209 static inline int dmaor_reset(void)
211 unsigned long dmaor = dmaor_read_reg();
213 /* Try to clear the error flags first, incase they are set */
214 dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
215 dmaor_write_reg(dmaor);
218 dmaor_write_reg(dmaor);
220 /* See if we got an error again */
221 if ((dmaor_read_reg() & (DMAOR_AE | DMAOR_NMIF))) {
222 printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
229 #if defined(CONFIG_CPU_SH4)
230 static irqreturn_t dma_err(int irq, void *dev_id, struct pt_regs *regs)
239 static struct dma_ops sh_dmac_ops = {
240 .request = sh_dmac_request_dma,
241 .free = sh_dmac_free_dma,
242 .get_residue = sh_dmac_get_dma_residue,
243 .xfer = sh_dmac_xfer_dma,
244 .configure = sh_dmac_configure_channel,
247 static struct dma_info sh_dmac_info = {
249 .nr_channels = CONFIG_NR_ONCHIP_DMA_CHANNELS,
251 .flags = DMAC_CHANNELS_TEI_CAPABLE,
254 static int __init sh_dmac_init(void)
256 struct dma_info *info = &sh_dmac_info;
259 #ifdef CONFIG_CPU_SH4
260 make_ipr_irq(DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
261 i = request_irq(DMAE_IRQ, dma_err, SA_INTERRUPT, "DMAC Address Error", 0);
266 for (i = 0; i < info->nr_channels; i++) {
267 int irq = get_dmte_irq(i);
269 make_ipr_irq(irq, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
273 * Initialize DMAOR, and clean up any error flags that may have
280 return register_dmac(info);
283 static void __exit sh_dmac_exit(void)
285 #ifdef CONFIG_CPU_SH4
286 free_irq(DMAE_IRQ, 0);
288 unregister_dmac(&sh_dmac_info);
291 subsys_initcall(sh_dmac_init);
292 module_exit(sh_dmac_exit);
294 MODULE_AUTHOR("Takashi YOSHII, Paul Mundt, Andriy Skulysh");
295 MODULE_DESCRIPTION("SuperH On-Chip DMAC Support");
296 MODULE_LICENSE("GPL");