arch/sh/boards/se/7206/irq.c

   1 /*
   2  * linux/arch/sh/boards/se/7206/irq.c
   3  *
   4  * Copyright (C) 2005,2006 Yoshinori Sato
   5  *
   6  * Hitachi SolutionEngine Support.
   7  *
   8  */
   9 #include <linux/init.h>
  10 #include <linux/irq.h>
  11 #include <linux/io.h>
  12 #include <linux/irq.h>
  13 #include <asm/se7206.h>
  14
  15 #define INTSTS0 0x31800000
  16 #define INTSTS1 0x31800002
  17 #define INTMSK0 0x31800004
  18 #define INTMSK1 0x31800006
  19 #define INTSEL  0x31800008
  20
  21 static void disable_se7206_irq(unsigned int irq)
  22 {
  23         unsigned short val;
  24         unsigned short mask = 0xffff ^ (0x0f << 4 * (3 - (IRQ0_IRQ - irq)));
  25         unsigned short msk0,msk1;
  26
  27         /* Set the priority in IPR to 0 */
  28         val = ctrl_inw(INTC_IPR01);
  29         val &= mask;
  30         ctrl_outw(val, INTC_IPR01);
  31         /* FPGA mask set */
  32         msk0 = ctrl_inw(INTMSK0);
  33         msk1 = ctrl_inw(INTMSK1);
  34
  35         switch (irq) {
  36         case IRQ0_IRQ:
  37                 msk0 |= 0x0010;
  38                 break;
  39         case IRQ1_IRQ:
  40                 msk0 |= 0x000f;
  41                 break;
  42         case IRQ2_IRQ:
  43                 msk0 |= 0x0f00;
  44                 msk1 |= 0x00ff;
  45                 break;
  46         }
  47         ctrl_outw(msk0, INTMSK0);
  48         ctrl_outw(msk1, INTMSK1);
  49 }
  50
  51 static void enable_se7206_irq(unsigned int irq)
  52 {
  53         unsigned short val;
  54         unsigned short value = (0x0001 << 4 * (3 - (IRQ0_IRQ - irq)));
  55         unsigned short msk0,msk1;
  56
  57         /* Set priority in IPR back to original value */
  58         val = ctrl_inw(INTC_IPR01);
  59         val |= value;
  60         ctrl_outw(val, INTC_IPR01);
  61
  62         /* FPGA mask reset */
  63         msk0 = ctrl_inw(INTMSK0);
  64         msk1 = ctrl_inw(INTMSK1);
  65
  66         switch (irq) {
  67         case IRQ0_IRQ:
  68                 msk0 &= ~0x0010;
  69                 break;
  70         case IRQ1_IRQ:
  71                 msk0 &= ~0x000f;
  72                 break;
  73         case IRQ2_IRQ:
  74                 msk0 &= ~0x0f00;
  75                 msk1 &= ~0x00ff;
  76                 break;
  77         }
  78         ctrl_outw(msk0, INTMSK0);
  79         ctrl_outw(msk1, INTMSK1);
  80 }
  81
  82 static void eoi_se7206_irq(unsigned int irq)
  83 {
  84         unsigned short sts0,sts1;
  85
  86         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
  87                 enable_se7206_irq(irq);
  88         /* FPGA isr clear */
  89         sts0 = ctrl_inw(INTSTS0);
  90         sts1 = ctrl_inw(INTSTS1);
  91
  92         switch (irq) {
  93         case IRQ0_IRQ:
  94                 sts0 &= ~0x0010;
  95                 break;
  96         case IRQ1_IRQ:
  97                 sts0 &= ~0x000f;
  98                 break;
  99         case IRQ2_IRQ:
 100                 sts0 &= ~0x0f00;
 101                 sts1 &= ~0x00ff;
 102                 break;
 103         }
 104         ctrl_outw(sts0, INTSTS0);
 105         ctrl_outw(sts1, INTSTS1);
 106 }
 107
 108 static struct irq_chip se7206_irq_chip __read_mostly = {
 109         .name           = "SE7206-FPGA-IRQ",
 110         .mask           = disable_se7206_irq,
 111         .unmask         = enable_se7206_irq,
 112         .mask_ack       = disable_se7206_irq,
 113         .eoi            = eoi_se7206_irq,
 114 };
 115
 116 static void make_se7206_irq(unsigned int irq)
 117 {
 118         disable_irq_nosync(irq);
 119         set_irq_chip_and_handler_name(irq, &se7206_irq_chip,
 120                                       handle_level_irq, "level");
 121         disable_se7206_irq(irq);
 122 }
 123
 124 /*
 125  * Initialize IRQ setting
 126  */
 127 void __init init_se7206_IRQ(void)
 128 {
 129         make_se7206_irq(IRQ0_IRQ); /* SMC91C111 */
 130         make_se7206_irq(IRQ1_IRQ); /* ATA */
 131         make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */
 132         ctrl_outw(inw(INTC_ICR1) | 0x000b ,INTC_ICR1 ) ; /* ICR1 */
 133
 134         /* FPGA System register setup*/
 135         ctrl_outw(0x0000,INTSTS0); /* Clear INTSTS0 */
 136         ctrl_outw(0x0000,INTSTS1); /* Clear INTSTS1 */
 137         /* IRQ0=LAN, IRQ1=ATA, IRQ3=SLT,PCM */
 138         ctrl_outw(0x0001,INTSEL);
 139 }