arch/s390/kernel/head64.S

   1 /*
   2  * arch/s390/kernel/head64.S
   3  *
   4  * Copyright (C) IBM Corp. 1999,2006
   5  *
   6  *   Author(s): Hartmut Penner <hp@de.ibm.com>
   7  *              Martin Schwidefsky <schwidefsky@de.ibm.com>
   8  *              Rob van der Heij <rvdhei@iae.nl>
   9  *              Heiko Carstens <heiko.carstens@de.ibm.com>
  10  *
  11  */
  12
  13         .org    0x11000
  14
  15 startup_continue:
  16         basr    %r13,0                  # get base
  17 .LPG1:  sll     %r13,1                  # remove high order bit
  18         srl     %r13,1
  19         mvi     __LC_AR_MODE_ID,1       # set esame flag
  20         slr     %r0,%r0                 # set cpuid to zero
  21         lhi     %r1,2                   # mode 2 = esame (dump)
  22         sigp    %r1,%r0,0x12            # switch to esame mode
  23         sam64                           # switch to 64 bit mode
  24         llgfr   %r13,%r13               # clear high-order half of base reg
  25         lmh     %r0,%r15,.Lzero64-.LPG1(%r13)   # clear high-order half
  26         lctlg   %c0,%c15,.Lctl-.LPG1(%r13)      # load control registers
  27         lg      %r12,.Lparmaddr-.LPG1(%r13)     # pointer to parameter area
  28                                         # move IPL device to lowcore
  29         lghi    %r0,__LC_PASTE
  30         stg     %r0,__LC_VDSO_PER_CPU
  31 #
  32 # Setup stack
  33 #
  34         larl    %r15,init_thread_union
  35         stg     %r15,__LC_THREAD_INFO   # cache thread info in lowcore
  36         lg      %r14,__TI_task(%r15)    # cache current in lowcore
  37         stg     %r14,__LC_CURRENT
  38         aghi    %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union + THREAD_SIZE
  39         stg     %r15,__LC_KERNEL_STACK  # set end of kernel stack
  40         aghi    %r15,-160
  41 #
  42 # Save ipl parameters, clear bss memory, initialize storage key for kernel pages,
  43 # and create a kernel NSS if the SAVESYS= parm is defined
  44 #
  45         brasl   %r14,startup_init
  46         lpswe   .Lentry-.LPG1(13)       # jump to _stext in primary-space,
  47                                         # virtual and never return ...
  48         .align  16
  49 .Lentry:.quad   0x0000000180000000,_stext
  50 .Lctl:  .quad   0x04350002              # cr0: various things
  51         .quad   0                       # cr1: primary space segment table
  52         .quad   .Lduct                  # cr2: dispatchable unit control table
  53         .quad   0                       # cr3: instruction authorization
  54         .quad   0                       # cr4: instruction authorization
  55         .quad   .Lduct                  # cr5: primary-aste origin
  56         .quad   0                       # cr6:  I/O interrupts
  57         .quad   0                       # cr7:  secondary space segment table
  58         .quad   0                       # cr8:  access registers translation
  59         .quad   0                       # cr9:  tracing off
  60         .quad   0                       # cr10: tracing off
  61         .quad   0                       # cr11: tracing off
  62         .quad   0                       # cr12: tracing off
  63         .quad   0                       # cr13: home space segment table
  64         .quad   0xc0000000              # cr14: machine check handling off
  65         .quad   0                       # cr15: linkage stack operations
  66 .Lpcmsk:.quad   0x0000000180000000
  67 .L4malign:.quad 0xffffffffffc00000
  68 .Lscan2g:.quad  0x80000000 + 0x20000 - 8        # 2GB + 128K - 8
  69 .Lnop:  .long   0x07000700
  70 .Lzero64:.fill  16,4,0x0
  71 .Lparmaddr:
  72         .quad   PARMAREA
  73         .align  64
  74 .Lduct: .long   0,0,0,0,.Lduald,0,0,0
  75         .long   0,0,0,0,0,0,0,0
  76         .align  128
  77 .Lduald:.rept   8
  78         .long   0x80000000,0,0,0        # invalid access-list entries
  79         .endr
  80
  81         .org    0x12000
  82         .globl  _ehead
  83 _ehead:
  84 #ifdef CONFIG_SHARED_KERNEL
  85         .org    0x100000
  86 #endif
  87
  88 #
  89 # startup-code, running in absolute addressing mode
  90 #
  91         .globl  _stext
  92 _stext: basr    %r13,0                  # get base
  93 .LPG3:
  94 # check control registers
  95         stctg   %c0,%c15,0(%r15)
  96         oi      6(%r15),0x40            # enable sigp emergency signal
  97         oi      4(%r15),0x10            # switch on low address proctection
  98         lctlg   %c0,%c15,0(%r15)
  99
 100         lam     0,15,.Laregs-.LPG3(%r13)        # load acrs needed by uaccess
 101         brasl   %r14,start_kernel       # go to C code
 102 #
 103 # We returned from start_kernel ?!? PANIK
 104 #
 105         basr    %r13,0
 106         lpswe   .Ldw-.(%r13)            # load disabled wait psw
 107
 108         .align  8
 109 .Ldw:   .quad   0x0002000180000000,0x0000000000000000
 110 .Laregs:.long   0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0