5 * TLB flushing on s390 is complicated. The following requirement
6 * from the principles of operation is the most arduous:
8 * "A valid table entry must not be changed while it is attached
9 * to any CPU and may be used for translation by that CPU except to
10 * (1) invalidate the entry by using INVALIDATE PAGE TABLE ENTRY,
11 * or INVALIDATE DAT TABLE ENTRY, (2) alter bits 56-63 of a page
12 * table entry, or (3) make a change by means of a COMPARE AND SWAP
13 * AND PURGE instruction that purges the TLB."
15 * The modification of a pte of an active mm struct therefore is
16 * a two step process: i) invalidate the pte, ii) store the new pte.
17 * This is true for the page protection bit as well.
18 * The only possible optimization is to flush at the beginning of
19 * a tlb_gather_mmu cycle if the mm_struct is currently not in use.
21 * Pages used for the page tables is a different story. FIXME: more
25 #include <linux/swap.h>
26 #include <asm/processor.h>
27 #include <asm/pgalloc.h>
29 #include <asm/tlbflush.h>
34 #define TLB_NR_PTRS 508
42 void *array[TLB_NR_PTRS];
45 DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
47 static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm,
48 unsigned int full_mm_flush)
50 struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
53 tlb->fullmm = full_mm_flush;
55 tlb->nr_pxds = TLB_NR_PTRS;
61 static inline void tlb_flush_mmu(struct mmu_gather *tlb,
62 unsigned long start, unsigned long end)
64 if (!tlb->fullmm && (tlb->nr_ptes > 0 || tlb->nr_pxds < TLB_NR_PTRS))
65 __tlb_flush_mm(tlb->mm);
66 while (tlb->nr_ptes > 0)
67 pte_free(tlb->mm, tlb->array[--tlb->nr_ptes]);
68 while (tlb->nr_pxds < TLB_NR_PTRS)
69 /* pgd_free frees the pointer as region or segment table */
70 pgd_free(tlb->mm, tlb->array[tlb->nr_pxds++]);
73 static inline void tlb_finish_mmu(struct mmu_gather *tlb,
74 unsigned long start, unsigned long end)
76 tlb_flush_mmu(tlb, start, end);
78 /* keep the page table cache within bounds */
81 put_cpu_var(mmu_gathers);
85 * Release the page cache reference for a pte removed by
86 * tlb_ptep_clear_flush. In both flush modes the tlb fo a page cache page
87 * has already been freed, so just do free_page_and_swap_cache.
89 static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
91 free_page_and_swap_cache(page);
95 * pte_free_tlb frees a pte table and clears the CRSTE for the
96 * page table from the tlb.
98 static inline void pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
99 unsigned long address)
102 tlb->array[tlb->nr_ptes++] = pte;
103 if (tlb->nr_ptes >= tlb->nr_pxds)
104 tlb_flush_mmu(tlb, 0, 0);
106 pte_free(tlb->mm, pte);
110 * pmd_free_tlb frees a pmd table and clears the CRSTE for the
111 * segment table entry from the tlb.
112 * If the mm uses a two level page table the single pmd is freed
113 * as the pgd. pmd_free_tlb checks the asce_limit against 2GB
114 * to avoid the double free of the pmd in this case.
116 static inline void pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmd,
117 unsigned long address)
120 if (tlb->mm->context.asce_limit <= (1UL << 31))
123 tlb->array[--tlb->nr_pxds] = pmd;
124 if (tlb->nr_ptes >= tlb->nr_pxds)
125 tlb_flush_mmu(tlb, 0, 0);
127 pmd_free(tlb->mm, pmd);
132 * pud_free_tlb frees a pud table and clears the CRSTE for the
133 * region third table entry from the tlb.
134 * If the mm uses a three level page table the single pud is freed
135 * as the pgd. pud_free_tlb checks the asce_limit against 4TB
136 * to avoid the double free of the pud in this case.
138 static inline void pud_free_tlb(struct mmu_gather *tlb, pud_t *pud,
139 unsigned long address)
142 if (tlb->mm->context.asce_limit <= (1UL << 42))
145 tlb->array[--tlb->nr_pxds] = pud;
146 if (tlb->nr_ptes >= tlb->nr_pxds)
147 tlb_flush_mmu(tlb, 0, 0);
149 pud_free(tlb->mm, pud);
153 #define tlb_start_vma(tlb, vma) do { } while (0)
154 #define tlb_end_vma(tlb, vma) do { } while (0)
155 #define tlb_remove_tlb_entry(tlb, ptep, addr) do { } while (0)
156 #define tlb_migrate_finish(mm) do { } while (0)
158 #endif /* _S390_TLB_H */