2 * arch/ppc/kernel/setup.c
4 * Copyright (C) 1995 Linus Torvalds
5 * Adapted from 'alpha' version by Gary Thomas
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 * Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
8 * Further modified for generic 8xx by Dan.
12 * bootup setup stuff..
15 #include <linux/config.h>
16 #include <linux/errno.h>
17 #include <linux/sched.h>
18 #include <linux/kernel.h>
20 #include <linux/stddef.h>
21 #include <linux/unistd.h>
22 #include <linux/ptrace.h>
23 #include <linux/slab.h>
24 #include <linux/user.h>
25 #include <linux/a.out.h>
26 #include <linux/tty.h>
27 #include <linux/major.h>
28 #include <linux/interrupt.h>
29 #include <linux/reboot.h>
30 #include <linux/init.h>
31 #include <linux/initrd.h>
32 #include <linux/ioport.h>
33 #include <linux/bootmem.h>
34 #include <linux/seq_file.h>
35 #include <linux/root_dev.h>
39 #include <asm/residual.h>
41 #include <asm/pgtable.h>
42 #include <asm/mpc8xx.h>
43 #include <asm/8xx_immap.h>
44 #include <asm/machdep.h>
45 #include <asm/bootinfo.h>
48 #include <asm/ppc_sys.h>
50 #include "ppc8xx_pic.h"
52 static int m8xx_set_rtc_time(unsigned long time);
53 static unsigned long m8xx_get_rtc_time(void);
54 void m8xx_calibrate_decr(void);
56 unsigned char __res[sizeof(bd_t)];
58 extern void m8xx_ide_init(void);
60 extern unsigned long find_available_memory(void);
61 extern void m8xx_cpm_reset(void);
62 extern void m8xx_wdt_handler_install(bd_t *bp);
63 extern void rpxfb_alloc_pages(void);
64 extern void cpm_interrupt_init(void);
66 void __attribute__ ((weak))
74 /* Reset the Communication Processor Module.
83 ROOT_DEV = Root_HDA1; /* hda1 */
86 #ifdef CONFIG_BLK_DEV_INITRD
88 ROOT_DEV = Root_FD0; /* floppy */
93 #if 0 /* XXX this may need to be updated for the new bootmem stuff,
94 or possibly just deleted (see set_phys_avail() in init.c).
96 /* initrd_start and size are setup by boot/head.S and kernel/head.S */
99 if (initrd_end > *memory_end_p)
101 printk("initrd extends beyond end of memory "
102 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
103 initrd_end,*memory_end_p);
118 machine_restart(NULL);
124 /* A place holder for time base interrupts, if they are ever enabled. */
125 irqreturn_t timebase_interrupt(int irq, void * dev, struct pt_regs * regs)
127 printk ("timebase_interrupt()\n");
132 static struct irqaction tbint_irqaction = {
133 .handler = timebase_interrupt,
134 .mask = CPU_MASK_NONE,
138 /* per-board overridable init_internal_rtc() function. */
139 void __init __attribute__ ((weak))
140 init_internal_rtc(void)
142 /* Disable the RTC one second and alarm interrupts. */
143 clrbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
146 setbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
150 /* The decrementer counts at the system (internal) clock frequency divided by
151 * sixteen, or external oscillator divided by four. We force the processor
152 * to use system clock divided by sixteen.
154 void __init m8xx_calibrate_decr(void)
156 bd_t *binfo = (bd_t *)__res;
157 int freq, fp, divisor;
159 /* Unlock the SCCR. */
160 out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, ~KAPWR_KEY);
161 out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, KAPWR_KEY);
163 /* Force all 8xx processors to use divide by 16 processor clock. */
164 setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr, 0x02000000);
165 /* Processor frequency is MHz.
166 * The value 'fp' is the number of decrementer ticks per second.
168 fp = binfo->bi_intfreq / 16;
169 freq = fp*60; /* try to make freq/1e6 an integer */
171 printk("Decrementer Frequency = %d/%d\n", freq, divisor);
172 tb_ticks_per_jiffy = freq / HZ / divisor;
173 tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
175 /* Perform some more timer/timebase initialization. This used
176 * to be done elsewhere, but other changes caused it to get
177 * called more than once....that is a bad thing.
179 * First, unlock all of the registers we are going to modify.
180 * To protect them from corruption during power down, registers
181 * that are maintained by keep alive power are "locked". To
182 * modify these registers we have to write the key value to
183 * the key location associated with the register.
184 * Some boards power up with these unlocked, while others
185 * are locked. Writing anything (including the unlock code?)
186 * to the unlocked registers will lock them again. So, here
187 * we guarantee the registers are locked, then we unlock them
190 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk, ~KAPWR_KEY);
191 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, ~KAPWR_KEY);
192 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, ~KAPWR_KEY);
193 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk, KAPWR_KEY);
194 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, KAPWR_KEY);
195 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, KAPWR_KEY);
199 /* Enabling the decrementer also enables the timebase interrupts
200 * (or from the other point of view, to get decrementer interrupts
201 * we have to enable the timebase). The decrementer interrupt
202 * is wired into the vector table, nothing to do here for that.
204 out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_tbscr, (mk_int_int_mask(DEC_INTERRUPT) << 8) | (TBSCR_TBF | TBSCR_TBE));
206 if (setup_irq(DEC_INTERRUPT, &tbint_irqaction))
207 panic("Could not allocate timer IRQ!");
209 #ifdef CONFIG_8xx_WDT
210 /* Install watchdog timer handler early because it might be
211 * already enabled by the bootloader
213 m8xx_wdt_handler_install(binfo);
217 /* The RTC on the MPC8xx is an internal register.
218 * We want to protect this during power down, so we need to unlock,
219 * modify, and re-lock.
222 m8xx_set_rtc_time(unsigned long time)
224 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck, KAPWR_KEY);
225 out_be32(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtc, time);
226 out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck, ~KAPWR_KEY);
231 m8xx_get_rtc_time(void)
233 /* Get time from the RTC. */
234 return (unsigned long) in_be32(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtc);
238 m8xx_restart(char *cmd)
240 __volatile__ unsigned char dummy;
244 setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, 0x00000080);
245 /* Clear the ME bit in MSR to cause checkstop on machine check
247 mtmsr(mfmsr() & ~0x1000);
249 dummy = in_8(&((immap_t *)IMAP_ADDR)->im_clkrst.res[0]);
250 printk("Restart failed\n");
268 m8xx_show_percpuinfo(struct seq_file *m, int i)
274 seq_printf(m, "clock\t\t: %uMHz\n"
275 "bus clock\t: %uMHz\n",
276 bp->bi_intfreq / 1000000,
277 bp->bi_busfreq / 1000000);
283 static struct irqaction mbx_i8259_irqaction = {
284 .handler = mbx_i8259_action,
285 .mask = CPU_MASK_NONE,
286 .name = "i8259 cascade",
290 /* Initialize the internal interrupt controller. The number of
291 * interrupts supported can vary with the processor type, and the
292 * 82xx family can have up to 64.
293 * External interrupts can be either edge or level triggered, and
294 * need to be initialized by the appropriate driver.
301 for (i = SIU_IRQ_OFFSET ; i < SIU_IRQ_OFFSET + NR_SIU_INTS ; i++)
302 irq_desc[i].handler = &ppc8xx_pic;
304 cpm_interrupt_init();
306 #if defined(CONFIG_PCI)
307 for (i = I8259_IRQ_OFFSET ; i < I8259_IRQ_OFFSET + NR_8259_INTS ; i++)
308 irq_desc[i].handler = &i8259_pic;
310 i8259_pic_irq_offset = I8259_IRQ_OFFSET;
313 /* The i8259 cascade interrupt must be level sensitive. */
315 clrbits32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, (0x80000000 >> ISA_BRIDGE_INT));
316 if (setup_irq(ISA_BRIDGE_INT, &mbx_i8259_irqaction))
317 enable_irq(ISA_BRIDGE_INT);
318 #endif /* CONFIG_PCI */
321 /* -------------------------------------------------------------------- */
324 * This is a big hack right now, but it may turn into something real
327 * For the 8xx boards (at this time anyway), there is nothing to initialize
328 * associated the PROM. Rather than include all of the prom.c
329 * functions in the image just to get prom_init, all we really need right
330 * now is the initialization of the physical memory region.
332 static unsigned long __init
333 m8xx_find_end_of_memory(void)
336 extern unsigned char __res[];
338 binfo = (bd_t *)__res;
340 return binfo->bi_memsize;
344 * Now map in some of the I/O space that is generically needed
345 * or shared with multiple devices.
346 * All of this fits into the same 4Mbyte region, so it only
347 * requires one page table page. (or at least it used to -- paulus)
352 io_block_mapping(IMAP_ADDR, IMAP_ADDR, IMAP_SIZE, _PAGE_IO);
354 io_block_mapping(NVRAM_ADDR, NVRAM_ADDR, NVRAM_SIZE, _PAGE_IO);
355 io_block_mapping(MBX_CSR_ADDR, MBX_CSR_ADDR, MBX_CSR_SIZE, _PAGE_IO);
356 io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO);
358 /* Map some of the PCI/ISA I/O space to get the IDE interface.
360 io_block_mapping(PCI_ISA_IO_ADDR, PCI_ISA_IO_ADDR, 0x4000, _PAGE_IO);
361 io_block_mapping(PCI_IDE_ADDR, PCI_IDE_ADDR, 0x4000, _PAGE_IO);
363 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
364 io_block_mapping(RPX_CSR_ADDR, RPX_CSR_ADDR, RPX_CSR_SIZE, _PAGE_IO);
365 #if !defined(CONFIG_PCI)
366 io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
369 #if defined(CONFIG_HTDMSOUND) || defined(CONFIG_RPXTOUCH) || defined(CONFIG_FB_RPX)
370 io_block_mapping(HIOX_CSR_ADDR, HIOX_CSR_ADDR, HIOX_CSR_SIZE, _PAGE_IO);
373 io_block_mapping(BCSR_ADDR, BCSR_ADDR, BCSR_SIZE, _PAGE_IO);
376 io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO);
378 #if defined(CONFIG_NETTA)
379 io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
384 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
385 unsigned long r6, unsigned long r7)
387 parse_bootinfo(find_bootinfo());
390 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
393 m8xx_setup_pci_ptrs();
396 #ifdef CONFIG_BLK_DEV_INITRD
397 /* take care of initrd if we have one */
400 initrd_start = r4 + KERNELBASE;
401 initrd_end = r5 + KERNELBASE;
403 #endif /* CONFIG_BLK_DEV_INITRD */
404 /* take care of cmd line */
407 *(char *)(r7+KERNELBASE) = 0;
408 strcpy(cmd_line, (char *)(r6+KERNELBASE));
411 identify_ppc_sys_by_name(BOARD_CHIP_NAME);
413 ppc_md.setup_arch = m8xx_setup_arch;
414 ppc_md.show_percpuinfo = m8xx_show_percpuinfo;
415 ppc_md.init_IRQ = m8xx_init_IRQ;
416 ppc_md.get_irq = m8xx_get_irq;
419 ppc_md.restart = m8xx_restart;
420 ppc_md.power_off = m8xx_power_off;
421 ppc_md.halt = m8xx_halt;
423 ppc_md.time_init = NULL;
424 ppc_md.set_rtc_time = m8xx_set_rtc_time;
425 ppc_md.get_rtc_time = m8xx_get_rtc_time;
426 ppc_md.calibrate_decr = m8xx_calibrate_decr;
428 ppc_md.find_end_of_memory = m8xx_find_end_of_memory;
429 ppc_md.setup_io_mappings = m8xx_map_io;
431 #if defined(CONFIG_BLK_DEV_MPC8xx_IDE)