arch/powerpc/sysdev/qe_lib/ucc_slow.c

   1 /*
   2  * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
   3  *
   4  * Authors:     Shlomi Gridish <gridish@freescale.com>
   5  *              Li Yang <leoli@freescale.com>
   6  *
   7  * Description:
   8  * QE UCC Slow API Set - UCC Slow specific routines implementations.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/errno.h>
  18 #include <linux/slab.h>
  19 #include <linux/stddef.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/err.h>
  22
  23 #include <asm/io.h>
  24 #include <asm/immap_qe.h>
  25 #include <asm/qe.h>
  26
  27 #include <asm/ucc.h>
  28 #include <asm/ucc_slow.h>
  29
  30 u32 ucc_slow_get_qe_cr_subblock(int uccs_num)
  31 {
  32         switch (uccs_num) {
  33         case 0: return QE_CR_SUBBLOCK_UCCSLOW1;
  34         case 1: return QE_CR_SUBBLOCK_UCCSLOW2;
  35         case 2: return QE_CR_SUBBLOCK_UCCSLOW3;
  36         case 3: return QE_CR_SUBBLOCK_UCCSLOW4;
  37         case 4: return QE_CR_SUBBLOCK_UCCSLOW5;
  38         case 5: return QE_CR_SUBBLOCK_UCCSLOW6;
  39         case 6: return QE_CR_SUBBLOCK_UCCSLOW7;
  40         case 7: return QE_CR_SUBBLOCK_UCCSLOW8;
  41         default: return QE_CR_SUBBLOCK_INVALID;
  42         }
  43 }
  44
  45 void ucc_slow_poll_transmitter_now(struct ucc_slow_private * uccs)
  46 {
  47         out_be16(&uccs->us_regs->utodr, UCC_SLOW_TOD);
  48 }
  49
  50 void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs)
  51 {
  52         struct ucc_slow_info *us_info = uccs->us_info;
  53         u32 id;
  54
  55         id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
  56         qe_issue_cmd(QE_GRACEFUL_STOP_TX, id,
  57                          QE_CR_PROTOCOL_UNSPECIFIED, 0);
  58 }
  59
  60 void ucc_slow_stop_tx(struct ucc_slow_private * uccs)
  61 {
  62         struct ucc_slow_info *us_info = uccs->us_info;
  63         u32 id;
  64
  65         id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
  66         qe_issue_cmd(QE_STOP_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
  67 }
  68
  69 void ucc_slow_restart_tx(struct ucc_slow_private * uccs)
  70 {
  71         struct ucc_slow_info *us_info = uccs->us_info;
  72         u32 id;
  73
  74         id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
  75         qe_issue_cmd(QE_RESTART_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
  76 }
  77
  78 void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
  79 {
  80         struct ucc_slow *us_regs;
  81         u32 gumr_l;
  82
  83         us_regs = uccs->us_regs;
  84
  85         /* Enable reception and/or transmission on this UCC. */
  86         gumr_l = in_be32(&us_regs->gumr_l);
  87         if (mode & COMM_DIR_TX) {
  88                 gumr_l |= UCC_SLOW_GUMR_L_ENT;
  89                 uccs->enabled_tx = 1;
  90         }
  91         if (mode & COMM_DIR_RX) {
  92                 gumr_l |= UCC_SLOW_GUMR_L_ENR;
  93                 uccs->enabled_rx = 1;
  94         }
  95         out_be32(&us_regs->gumr_l, gumr_l);
  96 }
  97
  98 void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
  99 {
 100         struct ucc_slow *us_regs;
 101         u32 gumr_l;
 102
 103         us_regs = uccs->us_regs;
 104
 105         /* Disable reception and/or transmission on this UCC. */
 106         gumr_l = in_be32(&us_regs->gumr_l);
 107         if (mode & COMM_DIR_TX) {
 108                 gumr_l &= ~UCC_SLOW_GUMR_L_ENT;
 109                 uccs->enabled_tx = 0;
 110         }
 111         if (mode & COMM_DIR_RX) {
 112                 gumr_l &= ~UCC_SLOW_GUMR_L_ENR;
 113                 uccs->enabled_rx = 0;
 114         }
 115         out_be32(&us_regs->gumr_l, gumr_l);
 116 }
 117
 118 /* Initialize the UCC for Slow operations
 119  *
 120  * The caller should initialize the following us_info
 121  */
 122 int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret)
 123 {
 124         struct ucc_slow_private *uccs;
 125         u32 i;
 126         struct ucc_slow __iomem *us_regs;
 127         u32 gumr;
 128         struct qe_bd *bd;
 129         u32 id;
 130         u32 command;
 131         int ret = 0;
 132
 133         if (!us_info)
 134                 return -EINVAL;
 135
 136         /* check if the UCC port number is in range. */
 137         if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) {
 138                 printk(KERN_ERR "%s: illegal UCC number\n", __FUNCTION__);
 139                 return -EINVAL;
 140         }
 141
 142         /*
 143          * Set mrblr
 144          * Check that 'max_rx_buf_length' is properly aligned (4), unless
 145          * rfw is 1, meaning that QE accepts one byte at a time, unlike normal
 146          * case when QE accepts 32 bits at a time.
 147          */
 148         if ((!us_info->rfw) &&
 149                 (us_info->max_rx_buf_length & (UCC_SLOW_MRBLR_ALIGNMENT - 1))) {
 150                 printk(KERN_ERR "max_rx_buf_length not aligned.\n");
 151                 return -EINVAL;
 152         }
 153
 154         uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL);
 155         if (!uccs) {
 156                 printk(KERN_ERR "%s: Cannot allocate private data\n",
 157                         __FUNCTION__);
 158                 return -ENOMEM;
 159         }
 160
 161         /* Fill slow UCC structure */
 162         uccs->us_info = us_info;
 163         /* Set the PHY base address */
 164         uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow));
 165         if (uccs->us_regs == NULL) {
 166                 printk(KERN_ERR "%s: Cannot map UCC registers\n", __FUNCTION__);
 167                 return -ENOMEM;
 168         }
 169
 170         uccs->saved_uccm = 0;
 171         uccs->p_rx_frame = 0;
 172         us_regs = uccs->us_regs;
 173         uccs->p_ucce = (u16 *) & (us_regs->ucce);
 174         uccs->p_uccm = (u16 *) & (us_regs->uccm);
 175 #ifdef STATISTICS
 176         uccs->rx_frames = 0;
 177         uccs->tx_frames = 0;
 178         uccs->rx_discarded = 0;
 179 #endif                          /* STATISTICS */
 180
 181         /* Get PRAM base */
 182         uccs->us_pram_offset =
 183                 qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM);
 184         if (IS_ERR_VALUE(uccs->us_pram_offset)) {
 185                 printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __FUNCTION__);
 186                 ucc_slow_free(uccs);
 187                 return -ENOMEM;
 188         }
 189         id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
 190         qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, us_info->protocol,
 191                      uccs->us_pram_offset);
 192
 193         uccs->us_pram = qe_muram_addr(uccs->us_pram_offset);
 194
 195         /* Set UCC to slow type */
 196         ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW);
 197         if (ret) {
 198                 printk(KERN_ERR "%s: cannot set UCC type", __FUNCTION__);
 199                 ucc_slow_free(uccs);
 200                 return ret;
 201         }
 202
 203         out_be16(&uccs->us_pram->mrblr, us_info->max_rx_buf_length);
 204
 205         INIT_LIST_HEAD(&uccs->confQ);
 206
 207         /* Allocate BDs. */
 208         uccs->rx_base_offset =
 209                 qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd),
 210                                 QE_ALIGNMENT_OF_BD);
 211         if (IS_ERR_VALUE(uccs->rx_base_offset)) {
 212                 printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __FUNCTION__,
 213                         us_info->rx_bd_ring_len);
 214                 uccs->rx_base_offset = 0;
 215                 ucc_slow_free(uccs);
 216                 return -ENOMEM;
 217         }
 218
 219         uccs->tx_base_offset =
 220                 qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd),
 221                         QE_ALIGNMENT_OF_BD);
 222         if (IS_ERR_VALUE(uccs->tx_base_offset)) {
 223                 printk(KERN_ERR "%s: cannot allocate TX BDs", __FUNCTION__);
 224                 uccs->tx_base_offset = 0;
 225                 ucc_slow_free(uccs);
 226                 return -ENOMEM;
 227         }
 228
 229         /* Init Tx bds */
 230         bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
 231         for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) {
 232                 /* clear bd buffer */
 233                 out_be32(&bd->buf, 0);
 234                 /* set bd status and length */
 235                 out_be32((u32 *) bd, 0);
 236                 bd++;
 237         }
 238         /* for last BD set Wrap bit */
 239         out_be32(&bd->buf, 0);
 240         out_be32((u32 *) bd, cpu_to_be32(T_W));
 241
 242         /* Init Rx bds */
 243         bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
 244         for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) {
 245                 /* set bd status and length */
 246                 out_be32((u32*)bd, 0);
 247                 /* clear bd buffer */
 248                 out_be32(&bd->buf, 0);
 249                 bd++;
 250         }
 251         /* for last BD set Wrap bit */
 252         out_be32((u32*)bd, cpu_to_be32(R_W));
 253         out_be32(&bd->buf, 0);
 254
 255         /* Set GUMR (For more details see the hardware spec.). */
 256         /* gumr_h */
 257         gumr = us_info->tcrc;
 258         if (us_info->cdp)
 259                 gumr |= UCC_SLOW_GUMR_H_CDP;
 260         if (us_info->ctsp)
 261                 gumr |= UCC_SLOW_GUMR_H_CTSP;
 262         if (us_info->cds)
 263                 gumr |= UCC_SLOW_GUMR_H_CDS;
 264         if (us_info->ctss)
 265                 gumr |= UCC_SLOW_GUMR_H_CTSS;
 266         if (us_info->tfl)
 267                 gumr |= UCC_SLOW_GUMR_H_TFL;
 268         if (us_info->rfw)
 269                 gumr |= UCC_SLOW_GUMR_H_RFW;
 270         if (us_info->txsy)
 271                 gumr |= UCC_SLOW_GUMR_H_TXSY;
 272         if (us_info->rtsm)
 273                 gumr |= UCC_SLOW_GUMR_H_RTSM;
 274         out_be32(&us_regs->gumr_h, gumr);
 275
 276         /* gumr_l */
 277         gumr = us_info->tdcr | us_info->rdcr | us_info->tenc | us_info->renc |
 278                 us_info->diag | us_info->mode;
 279         if (us_info->tci)
 280                 gumr |= UCC_SLOW_GUMR_L_TCI;
 281         if (us_info->rinv)
 282                 gumr |= UCC_SLOW_GUMR_L_RINV;
 283         if (us_info->tinv)
 284                 gumr |= UCC_SLOW_GUMR_L_TINV;
 285         if (us_info->tend)
 286                 gumr |= UCC_SLOW_GUMR_L_TEND;
 287         out_be32(&us_regs->gumr_l, gumr);
 288
 289         /* Function code registers */
 290
 291         /* if the data is in cachable memory, the 'global' */
 292         /* in the function code should be set. */
 293         uccs->us_pram->tbmr = UCC_BMR_BO_BE;
 294         uccs->us_pram->rbmr = UCC_BMR_BO_BE;
 295
 296         /* rbase, tbase are offsets from MURAM base */
 297         out_be16(&uccs->us_pram->rbase, uccs->rx_base_offset);
 298         out_be16(&uccs->us_pram->tbase, uccs->tx_base_offset);
 299
 300         /* Mux clocking */
 301         /* Grant Support */
 302         ucc_set_qe_mux_grant(us_info->ucc_num, us_info->grant_support);
 303         /* Breakpoint Support */
 304         ucc_set_qe_mux_bkpt(us_info->ucc_num, us_info->brkpt_support);
 305         /* Set Tsa or NMSI mode. */
 306         ucc_set_qe_mux_tsa(us_info->ucc_num, us_info->tsa);
 307         /* If NMSI (not Tsa), set Tx and Rx clock. */
 308         if (!us_info->tsa) {
 309                 /* Rx clock routing */
 310                 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock,
 311                                         COMM_DIR_RX)) {
 312                         printk(KERN_ERR "%s: illegal value for RX clock\n",
 313                                __FUNCTION__);
 314                         ucc_slow_free(uccs);
 315                         return -EINVAL;
 316                 }
 317                 /* Tx clock routing */
 318                 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock,
 319                                         COMM_DIR_TX)) {
 320                         printk(KERN_ERR "%s: illegal value for TX clock\n",
 321                                __FUNCTION__);
 322                         ucc_slow_free(uccs);
 323                         return -EINVAL;
 324                 }
 325         }
 326
 327         /* Set interrupt mask register at UCC level. */
 328         out_be16(&us_regs->uccm, us_info->uccm_mask);
 329
 330         /* First, clear anything pending at UCC level,
 331          * otherwise, old garbage may come through
 332          * as soon as the dam is opened. */
 333
 334         /* Writing '1' clears */
 335         out_be16(&us_regs->ucce, 0xffff);
 336
 337         /* Issue QE Init command */
 338         if (us_info->init_tx && us_info->init_rx)
 339                 command = QE_INIT_TX_RX;
 340         else if (us_info->init_tx)
 341                 command = QE_INIT_TX;
 342         else
 343                 command = QE_INIT_RX;   /* We know at least one is TRUE */
 344
 345         qe_issue_cmd(command, id, us_info->protocol, 0);
 346
 347         *uccs_ret = uccs;
 348         return 0;
 349 }
 350
 351 void ucc_slow_free(struct ucc_slow_private * uccs)
 352 {
 353         if (!uccs)
 354                 return;
 355
 356         if (uccs->rx_base_offset)
 357                 qe_muram_free(uccs->rx_base_offset);
 358
 359         if (uccs->tx_base_offset)
 360                 qe_muram_free(uccs->tx_base_offset);
 361
 362         if (uccs->us_pram) {
 363                 qe_muram_free(uccs->us_pram_offset);
 364                 uccs->us_pram = NULL;
 365         }
 366
 367         kfree(uccs);
 368 }
 369
 370