4 * Copyright (c) MontaVista Software, Inc. 2008.
6 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
14 #include <linux/kernel.h>
15 #include <linux/spinlock.h>
18 #include <linux/of_gpio.h>
19 #include <linux/gpio.h>
23 struct of_mm_gpio_chip mm_gc;
26 /* shadowed data register to clear/set bits safely */
30 static inline struct qe_gpio_chip *
31 to_qe_gpio_chip(struct of_mm_gpio_chip *mm_gc)
33 return container_of(mm_gc, struct qe_gpio_chip, mm_gc);
36 static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
38 struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
39 struct qe_pio_regs __iomem *regs = mm_gc->regs;
41 qe_gc->cpdata = in_be32(®s->cpdata);
44 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
46 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
47 struct qe_pio_regs __iomem *regs = mm_gc->regs;
48 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
50 return in_be32(®s->cpdata) & pin_mask;
53 static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
55 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
56 struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
57 struct qe_pio_regs __iomem *regs = mm_gc->regs;
59 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
61 spin_lock_irqsave(&qe_gc->lock, flags);
64 qe_gc->cpdata |= pin_mask;
66 qe_gc->cpdata &= ~pin_mask;
68 out_be32(®s->cpdata, qe_gc->cpdata);
70 spin_unlock_irqrestore(&qe_gc->lock, flags);
73 static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
75 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
76 struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
79 spin_lock_irqsave(&qe_gc->lock, flags);
81 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
83 spin_unlock_irqrestore(&qe_gc->lock, flags);
88 static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
90 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
91 struct qe_gpio_chip *qe_gc = to_qe_gpio_chip(mm_gc);
94 spin_lock_irqsave(&qe_gc->lock, flags);
96 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
98 spin_unlock_irqrestore(&qe_gc->lock, flags);
100 qe_gpio_set(gc, gpio, val);
105 void __init qe_add_gpiochips(void)
107 struct device_node *np;
109 for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
111 struct qe_gpio_chip *qe_gc;
112 struct of_mm_gpio_chip *mm_gc;
113 struct of_gpio_chip *of_gc;
114 struct gpio_chip *gc;
116 qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
122 spin_lock_init(&qe_gc->lock);
124 mm_gc = &qe_gc->mm_gc;
125 of_gc = &mm_gc->of_gc;
128 mm_gc->save_regs = qe_gpio_save_regs;
129 of_gc->gpio_cells = 2;
130 gc->ngpio = QE_PIO_PINS;
131 gc->direction_input = qe_gpio_dir_in;
132 gc->direction_output = qe_gpio_dir_out;
133 gc->get = qe_gpio_get;
134 gc->set = qe_gpio_set;
136 ret = of_mm_gpiochip_add(np, mm_gc);
141 pr_err("%s: registration failed with status %d\n",
144 /* try others anyway */