2 * arch/powerpc/kernel/mpic.c
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 * Copyright 2010-2011 Freescale Semiconductor, Inc.
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file COPYING in the main directory of this archive
21 #include <linux/types.h>
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/irq.h>
25 #include <linux/smp.h>
26 #include <linux/interrupt.h>
27 #include <linux/bootmem.h>
28 #include <linux/spinlock.h>
29 #include <linux/pci.h>
30 #include <linux/slab.h>
31 #include <linux/syscore_ops.h>
32 #include <linux/ratelimit.h>
34 #include <asm/ptrace.h>
35 #include <asm/signal.h>
37 #include <asm/pgtable.h>
39 #include <asm/machdep.h>
46 #define DBG(fmt...) printk(fmt)
51 static struct mpic *mpics;
52 static struct mpic *mpic_primary;
53 static DEFINE_RAW_SPINLOCK(mpic_lock);
55 #ifdef CONFIG_PPC32 /* XXX for now */
56 #ifdef CONFIG_IRQ_ALL_CPUS
57 #define distribute_irqs (1)
59 #define distribute_irqs (0)
63 #ifdef CONFIG_MPIC_WEIRD
64 static u32 mpic_infos[][MPIC_IDX_END] = {
65 [0] = { /* Original OpenPIC compatible MPIC */
68 MPIC_GREG_GLOBAL_CONF_0,
70 MPIC_GREG_IPI_VECTOR_PRI_0,
77 MPIC_TIMER_CURRENT_CNT,
79 MPIC_TIMER_VECTOR_PRI,
80 MPIC_TIMER_DESTINATION,
84 MPIC_CPU_IPI_DISPATCH_0,
85 MPIC_CPU_IPI_DISPATCH_STRIDE,
86 MPIC_CPU_CURRENT_TASK_PRI,
95 MPIC_VECPRI_VECTOR_MASK,
96 MPIC_VECPRI_POLARITY_POSITIVE,
97 MPIC_VECPRI_POLARITY_NEGATIVE,
98 MPIC_VECPRI_SENSE_LEVEL,
99 MPIC_VECPRI_SENSE_EDGE,
100 MPIC_VECPRI_POLARITY_MASK,
101 MPIC_VECPRI_SENSE_MASK,
104 [1] = { /* Tsi108/109 PIC */
106 TSI108_GREG_FEATURE_0,
107 TSI108_GREG_GLOBAL_CONF_0,
108 TSI108_GREG_VENDOR_ID,
109 TSI108_GREG_IPI_VECTOR_PRI_0,
110 TSI108_GREG_IPI_STRIDE,
111 TSI108_GREG_SPURIOUS,
112 TSI108_GREG_TIMER_FREQ,
116 TSI108_TIMER_CURRENT_CNT,
117 TSI108_TIMER_BASE_CNT,
118 TSI108_TIMER_VECTOR_PRI,
119 TSI108_TIMER_DESTINATION,
123 TSI108_CPU_IPI_DISPATCH_0,
124 TSI108_CPU_IPI_DISPATCH_STRIDE,
125 TSI108_CPU_CURRENT_TASK_PRI,
133 TSI108_IRQ_VECTOR_PRI,
134 TSI108_VECPRI_VECTOR_MASK,
135 TSI108_VECPRI_POLARITY_POSITIVE,
136 TSI108_VECPRI_POLARITY_NEGATIVE,
137 TSI108_VECPRI_SENSE_LEVEL,
138 TSI108_VECPRI_SENSE_EDGE,
139 TSI108_VECPRI_POLARITY_MASK,
140 TSI108_VECPRI_SENSE_MASK,
141 TSI108_IRQ_DESTINATION
145 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
147 #else /* CONFIG_MPIC_WEIRD */
149 #define MPIC_INFO(name) MPIC_##name
151 #endif /* CONFIG_MPIC_WEIRD */
153 static inline unsigned int mpic_processor_id(struct mpic *mpic)
155 unsigned int cpu = 0;
157 if (mpic->flags & MPIC_PRIMARY)
158 cpu = hard_smp_processor_id();
164 * Register accessor functions
168 static inline u32 _mpic_read(enum mpic_reg_type type,
169 struct mpic_reg_bank *rb,
173 #ifdef CONFIG_PPC_DCR
174 case mpic_access_dcr:
175 return dcr_read(rb->dhost, reg);
177 case mpic_access_mmio_be:
178 return in_be32(rb->base + (reg >> 2));
179 case mpic_access_mmio_le:
181 return in_le32(rb->base + (reg >> 2));
185 static inline void _mpic_write(enum mpic_reg_type type,
186 struct mpic_reg_bank *rb,
187 unsigned int reg, u32 value)
190 #ifdef CONFIG_PPC_DCR
191 case mpic_access_dcr:
192 dcr_write(rb->dhost, reg, value);
195 case mpic_access_mmio_be:
196 out_be32(rb->base + (reg >> 2), value);
198 case mpic_access_mmio_le:
200 out_le32(rb->base + (reg >> 2), value);
205 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
207 enum mpic_reg_type type = mpic->reg_type;
208 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
209 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
211 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
212 type = mpic_access_mmio_be;
213 return _mpic_read(type, &mpic->gregs, offset);
216 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
218 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
219 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
221 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
224 static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
226 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
227 ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
230 offset += 0x1000 / 4;
232 return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
235 static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
237 unsigned int offset = MPIC_INFO(TIMER_VECTOR_PRI) +
238 ((tm & 3) * MPIC_INFO(TIMER_STRIDE));
241 offset += 0x1000 / 4;
243 _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
246 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
248 unsigned int cpu = mpic_processor_id(mpic);
250 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
253 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
255 unsigned int cpu = mpic_processor_id(mpic);
257 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
260 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
262 unsigned int isu = src_no >> mpic->isu_shift;
263 unsigned int idx = src_no & mpic->isu_mask;
266 val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
267 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
268 #ifdef CONFIG_MPIC_BROKEN_REGREAD
270 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
271 mpic->isu_reg0_shadow[src_no];
276 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
277 unsigned int reg, u32 value)
279 unsigned int isu = src_no >> mpic->isu_shift;
280 unsigned int idx = src_no & mpic->isu_mask;
282 _mpic_write(mpic->reg_type, &mpic->isus[isu],
283 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
285 #ifdef CONFIG_MPIC_BROKEN_REGREAD
287 mpic->isu_reg0_shadow[src_no] =
288 value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
292 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
293 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
294 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
295 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
296 #define mpic_tm_read(i) _mpic_tm_read(mpic,(i))
297 #define mpic_tm_write(i,v) _mpic_tm_write(mpic,(i),(v))
298 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
299 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
300 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
301 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
305 * Low level utility functions
309 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
310 struct mpic_reg_bank *rb, unsigned int offset,
313 rb->base = ioremap(phys_addr + offset, size);
314 BUG_ON(rb->base == NULL);
317 #ifdef CONFIG_PPC_DCR
318 static void _mpic_map_dcr(struct mpic *mpic, struct device_node *node,
319 struct mpic_reg_bank *rb,
320 unsigned int offset, unsigned int size)
324 dbasep = of_get_property(node, "dcr-reg", NULL);
326 rb->dhost = dcr_map(node, *dbasep + offset, size);
327 BUG_ON(!DCR_MAP_OK(rb->dhost));
330 static inline void mpic_map(struct mpic *mpic, struct device_node *node,
331 phys_addr_t phys_addr, struct mpic_reg_bank *rb,
332 unsigned int offset, unsigned int size)
334 if (mpic->flags & MPIC_USES_DCR)
335 _mpic_map_dcr(mpic, node, rb, offset, size);
337 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
339 #else /* CONFIG_PPC_DCR */
340 #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
341 #endif /* !CONFIG_PPC_DCR */
345 /* Check if we have one of those nice broken MPICs with a flipped endian on
346 * reads from IPI registers
348 static void __init mpic_test_broken_ipi(struct mpic *mpic)
352 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
353 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
355 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
356 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
357 mpic->flags |= MPIC_BROKEN_IPI;
361 #ifdef CONFIG_MPIC_U3_HT_IRQS
363 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
364 * to force the edge setting on the MPIC and do the ack workaround.
366 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
368 if (source >= 128 || !mpic->fixups)
370 return mpic->fixups[source].base != NULL;
374 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
376 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
378 if (fixup->applebase) {
379 unsigned int soff = (fixup->index >> 3) & ~3;
380 unsigned int mask = 1U << (fixup->index & 0x1f);
381 writel(mask, fixup->applebase + soff);
383 raw_spin_lock(&mpic->fixup_lock);
384 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
385 writel(fixup->data, fixup->base + 4);
386 raw_spin_unlock(&mpic->fixup_lock);
390 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
393 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
397 if (fixup->base == NULL)
400 DBG("startup_ht_interrupt(0x%x) index: %d\n",
401 source, fixup->index);
402 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
403 /* Enable and configure */
404 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
405 tmp = readl(fixup->base + 4);
409 writel(tmp, fixup->base + 4);
410 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
413 /* use the lowest bit inverted to the actual HW,
414 * set if this fixup was enabled, clear otherwise */
415 mpic->save_data[source].fixup_data = tmp | 1;
419 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
421 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
425 if (fixup->base == NULL)
428 DBG("shutdown_ht_interrupt(0x%x)\n", source);
431 raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
432 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
433 tmp = readl(fixup->base + 4);
435 writel(tmp, fixup->base + 4);
436 raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
439 /* use the lowest bit inverted to the actual HW,
440 * set if this fixup was enabled, clear otherwise */
441 mpic->save_data[source].fixup_data = tmp & ~1;
445 #ifdef CONFIG_PCI_MSI
446 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
453 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
454 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
455 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
456 if (id == PCI_CAP_ID_HT) {
457 id = readb(devbase + pos + 3);
458 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
466 base = devbase + pos;
468 flags = readb(base + HT_MSI_FLAGS);
469 if (!(flags & HT_MSI_FLAGS_FIXED)) {
470 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
471 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
474 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
475 PCI_SLOT(devfn), PCI_FUNC(devfn),
476 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
478 if (!(flags & HT_MSI_FLAGS_ENABLE))
479 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
482 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
489 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
490 unsigned int devfn, u32 vdid)
497 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
498 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
499 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
500 if (id == PCI_CAP_ID_HT) {
501 id = readb(devbase + pos + 3);
502 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
509 base = devbase + pos;
510 writeb(0x01, base + 2);
511 n = (readl(base + 4) >> 16) & 0xff;
513 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
515 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
517 for (i = 0; i <= n; i++) {
518 writeb(0x10 + 2 * i, base + 2);
519 tmp = readl(base + 4);
520 irq = (tmp >> 16) & 0xff;
521 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
522 /* mask it , will be unmasked later */
524 writel(tmp, base + 4);
525 mpic->fixups[irq].index = i;
526 mpic->fixups[irq].base = base;
527 /* Apple HT PIC has a non-standard way of doing EOIs */
528 if ((vdid & 0xffff) == 0x106b)
529 mpic->fixups[irq].applebase = devbase + 0x60;
531 mpic->fixups[irq].applebase = NULL;
532 writeb(0x11 + 2 * i, base + 2);
533 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
538 static void __init mpic_scan_ht_pics(struct mpic *mpic)
541 u8 __iomem *cfgspace;
543 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
545 /* Allocate fixups array */
546 mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
547 BUG_ON(mpic->fixups == NULL);
550 raw_spin_lock_init(&mpic->fixup_lock);
552 /* Map U3 config space. We assume all IO-APICs are on the primary bus
553 * so we only need to map 64kB.
555 cfgspace = ioremap(0xf2000000, 0x10000);
556 BUG_ON(cfgspace == NULL);
558 /* Now we scan all slots. We do a very quick scan, we read the header
559 * type, vendor ID and device ID only, that's plenty enough
561 for (devfn = 0; devfn < 0x100; devfn++) {
562 u8 __iomem *devbase = cfgspace + (devfn << 8);
563 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
564 u32 l = readl(devbase + PCI_VENDOR_ID);
567 DBG("devfn %x, l: %x\n", devfn, l);
569 /* If no device, skip */
570 if (l == 0xffffffff || l == 0x00000000 ||
571 l == 0x0000ffff || l == 0xffff0000)
573 /* Check if is supports capability lists */
574 s = readw(devbase + PCI_STATUS);
575 if (!(s & PCI_STATUS_CAP_LIST))
578 mpic_scan_ht_pic(mpic, devbase, devfn, l);
579 mpic_scan_ht_msi(mpic, devbase, devfn);
582 /* next device, if function 0 */
583 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
588 #else /* CONFIG_MPIC_U3_HT_IRQS */
590 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
595 static void __init mpic_scan_ht_pics(struct mpic *mpic)
599 #endif /* CONFIG_MPIC_U3_HT_IRQS */
601 /* Find an mpic associated with a given linux interrupt */
602 static struct mpic *mpic_find(unsigned int irq)
604 if (irq < NUM_ISA_INTERRUPTS)
607 return irq_get_chip_data(irq);
610 /* Determine if the linux irq is an IPI */
611 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
613 unsigned int src = virq_to_hw(irq);
615 return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
618 /* Determine if the linux irq is a timer */
619 static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
621 unsigned int src = virq_to_hw(irq);
623 return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
626 /* Convert a cpu mask from logical to physical cpu numbers. */
627 static inline u32 mpic_physmask(u32 cpumask)
632 for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
633 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
638 /* Get the mpic structure from the IPI number */
639 static inline struct mpic * mpic_from_ipi(struct irq_data *d)
641 return irq_data_get_irq_chip_data(d);
645 /* Get the mpic structure from the irq number */
646 static inline struct mpic * mpic_from_irq(unsigned int irq)
648 return irq_get_chip_data(irq);
651 /* Get the mpic structure from the irq data */
652 static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
654 return irq_data_get_irq_chip_data(d);
658 static inline void mpic_eoi(struct mpic *mpic)
660 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
661 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
665 * Linux descriptor level callbacks
669 void mpic_unmask_irq(struct irq_data *d)
671 unsigned int loops = 100000;
672 struct mpic *mpic = mpic_from_irq_data(d);
673 unsigned int src = irqd_to_hwirq(d);
675 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
677 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
678 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
680 /* make sure mask gets to controller before we return to user */
683 printk(KERN_ERR "%s: timeout on hwirq %u\n",
687 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
690 void mpic_mask_irq(struct irq_data *d)
692 unsigned int loops = 100000;
693 struct mpic *mpic = mpic_from_irq_data(d);
694 unsigned int src = irqd_to_hwirq(d);
696 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
698 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
699 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
702 /* make sure mask gets to controller before we return to user */
705 printk(KERN_ERR "%s: timeout on hwirq %u\n",
709 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
712 void mpic_end_irq(struct irq_data *d)
714 struct mpic *mpic = mpic_from_irq_data(d);
717 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
719 /* We always EOI on end_irq() even for edge interrupts since that
720 * should only lower the priority, the MPIC should have properly
721 * latched another edge interrupt coming in anyway
727 #ifdef CONFIG_MPIC_U3_HT_IRQS
729 static void mpic_unmask_ht_irq(struct irq_data *d)
731 struct mpic *mpic = mpic_from_irq_data(d);
732 unsigned int src = irqd_to_hwirq(d);
736 if (irqd_is_level_type(d))
737 mpic_ht_end_irq(mpic, src);
740 static unsigned int mpic_startup_ht_irq(struct irq_data *d)
742 struct mpic *mpic = mpic_from_irq_data(d);
743 unsigned int src = irqd_to_hwirq(d);
746 mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
751 static void mpic_shutdown_ht_irq(struct irq_data *d)
753 struct mpic *mpic = mpic_from_irq_data(d);
754 unsigned int src = irqd_to_hwirq(d);
756 mpic_shutdown_ht_interrupt(mpic, src);
760 static void mpic_end_ht_irq(struct irq_data *d)
762 struct mpic *mpic = mpic_from_irq_data(d);
763 unsigned int src = irqd_to_hwirq(d);
766 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
768 /* We always EOI on end_irq() even for edge interrupts since that
769 * should only lower the priority, the MPIC should have properly
770 * latched another edge interrupt coming in anyway
773 if (irqd_is_level_type(d))
774 mpic_ht_end_irq(mpic, src);
777 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
781 static void mpic_unmask_ipi(struct irq_data *d)
783 struct mpic *mpic = mpic_from_ipi(d);
784 unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
786 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
787 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
790 static void mpic_mask_ipi(struct irq_data *d)
792 /* NEVER disable an IPI... that's just plain wrong! */
795 static void mpic_end_ipi(struct irq_data *d)
797 struct mpic *mpic = mpic_from_ipi(d);
800 * IPIs are marked IRQ_PER_CPU. This has the side effect of
801 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
802 * applying to them. We EOI them late to avoid re-entering.
807 #endif /* CONFIG_SMP */
809 static void mpic_unmask_tm(struct irq_data *d)
811 struct mpic *mpic = mpic_from_irq_data(d);
812 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
814 DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
815 mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
819 static void mpic_mask_tm(struct irq_data *d)
821 struct mpic *mpic = mpic_from_irq_data(d);
822 unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
824 mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
828 int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
831 struct mpic *mpic = mpic_from_irq_data(d);
832 unsigned int src = irqd_to_hwirq(d);
834 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
835 int cpuid = irq_choose_cpu(cpumask);
837 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
839 u32 mask = cpumask_bits(cpumask)[0];
841 mask &= cpumask_bits(cpu_online_mask)[0];
843 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
844 mpic_physmask(mask));
850 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
852 /* Now convert sense value */
853 switch(type & IRQ_TYPE_SENSE_MASK) {
854 case IRQ_TYPE_EDGE_RISING:
855 return MPIC_INFO(VECPRI_SENSE_EDGE) |
856 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
857 case IRQ_TYPE_EDGE_FALLING:
858 case IRQ_TYPE_EDGE_BOTH:
859 return MPIC_INFO(VECPRI_SENSE_EDGE) |
860 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
861 case IRQ_TYPE_LEVEL_HIGH:
862 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
863 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
864 case IRQ_TYPE_LEVEL_LOW:
866 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
867 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
871 int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
873 struct mpic *mpic = mpic_from_irq_data(d);
874 unsigned int src = irqd_to_hwirq(d);
875 unsigned int vecpri, vold, vnew;
877 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
878 mpic, d->irq, src, flow_type);
880 if (src >= mpic->irq_count)
883 if (flow_type == IRQ_TYPE_NONE)
884 if (mpic->senses && src < mpic->senses_count)
885 flow_type = mpic->senses[src];
886 if (flow_type == IRQ_TYPE_NONE)
887 flow_type = IRQ_TYPE_LEVEL_LOW;
889 irqd_set_trigger_type(d, flow_type);
891 if (mpic_is_ht_interrupt(mpic, src))
892 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
893 MPIC_VECPRI_SENSE_EDGE;
895 vecpri = mpic_type_to_vecpri(mpic, flow_type);
897 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
898 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
899 MPIC_INFO(VECPRI_SENSE_MASK));
902 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
904 return IRQ_SET_MASK_OK_NOCOPY;;
907 void mpic_set_vector(unsigned int virq, unsigned int vector)
909 struct mpic *mpic = mpic_from_irq(virq);
910 unsigned int src = virq_to_hw(virq);
913 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
914 mpic, virq, src, vector);
916 if (src >= mpic->irq_count)
919 vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
920 vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
922 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
925 void mpic_set_destination(unsigned int virq, unsigned int cpuid)
927 struct mpic *mpic = mpic_from_irq(virq);
928 unsigned int src = virq_to_hw(virq);
930 DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
931 mpic, virq, src, cpuid);
933 if (src >= mpic->irq_count)
936 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
939 static struct irq_chip mpic_irq_chip = {
940 .irq_mask = mpic_mask_irq,
941 .irq_unmask = mpic_unmask_irq,
942 .irq_eoi = mpic_end_irq,
943 .irq_set_type = mpic_set_irq_type,
947 static struct irq_chip mpic_ipi_chip = {
948 .irq_mask = mpic_mask_ipi,
949 .irq_unmask = mpic_unmask_ipi,
950 .irq_eoi = mpic_end_ipi,
952 #endif /* CONFIG_SMP */
954 static struct irq_chip mpic_tm_chip = {
955 .irq_mask = mpic_mask_tm,
956 .irq_unmask = mpic_unmask_tm,
957 .irq_eoi = mpic_end_irq,
960 #ifdef CONFIG_MPIC_U3_HT_IRQS
961 static struct irq_chip mpic_irq_ht_chip = {
962 .irq_startup = mpic_startup_ht_irq,
963 .irq_shutdown = mpic_shutdown_ht_irq,
964 .irq_mask = mpic_mask_irq,
965 .irq_unmask = mpic_unmask_ht_irq,
966 .irq_eoi = mpic_end_ht_irq,
967 .irq_set_type = mpic_set_irq_type,
969 #endif /* CONFIG_MPIC_U3_HT_IRQS */
972 static int mpic_host_match(struct irq_host *h, struct device_node *node)
974 /* Exact match, unless mpic node is NULL */
975 return h->of_node == NULL || h->of_node == node;
978 static int mpic_host_map(struct irq_host *h, unsigned int virq,
981 struct mpic *mpic = h->host_data;
982 struct irq_chip *chip;
984 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
986 if (hw == mpic->spurious_vec)
988 if (mpic->protected && test_bit(hw, mpic->protected))
992 else if (hw >= mpic->ipi_vecs[0]) {
993 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
995 DBG("mpic: mapping as IPI\n");
996 irq_set_chip_data(virq, mpic);
997 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1001 #endif /* CONFIG_SMP */
1003 if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1004 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
1006 DBG("mpic: mapping as timer\n");
1007 irq_set_chip_data(virq, mpic);
1008 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1009 handle_fasteoi_irq);
1013 if (hw >= mpic->irq_count)
1016 mpic_msi_reserve_hwirq(mpic, hw);
1019 chip = &mpic->hc_irq;
1021 #ifdef CONFIG_MPIC_U3_HT_IRQS
1022 /* Check for HT interrupts, override vecpri */
1023 if (mpic_is_ht_interrupt(mpic, hw))
1024 chip = &mpic->hc_ht_irq;
1025 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1027 DBG("mpic: mapping to irq chip @%p\n", chip);
1029 irq_set_chip_data(virq, mpic);
1030 irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1032 /* Set default irq type */
1033 irq_set_irq_type(virq, IRQ_TYPE_NONE);
1035 /* If the MPIC was reset, then all vectors have already been
1036 * initialized. Otherwise, a per source lazy initialization
1039 if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1040 mpic_set_vector(virq, hw);
1041 mpic_set_destination(virq, mpic_processor_id(mpic));
1042 mpic_irq_set_priority(virq, 8);
1048 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
1049 const u32 *intspec, unsigned int intsize,
1050 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1053 struct mpic *mpic = h->host_data;
1054 static unsigned char map_mpic_senses[4] = {
1055 IRQ_TYPE_EDGE_RISING,
1057 IRQ_TYPE_LEVEL_HIGH,
1058 IRQ_TYPE_EDGE_FALLING,
1061 *out_hwirq = intspec[0];
1062 if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1064 * Freescale MPIC with extended intspec:
1065 * First two cells are as usual. Third specifies
1066 * an "interrupt type". Fourth is type-specific data.
1068 * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1070 switch (intspec[2]) {
1072 case 1: /* no EISR/EIMR support for now, treat as shared IRQ */
1075 if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1078 *out_hwirq = mpic->ipi_vecs[intspec[0]];
1081 if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1084 *out_hwirq = mpic->timer_vecs[intspec[0]];
1087 pr_debug("%s: unknown irq type %u\n",
1088 __func__, intspec[2]);
1092 *out_flags = map_mpic_senses[intspec[1] & 3];
1093 } else if (intsize > 1) {
1096 /* Apple invented a new race of encoding on machines with
1097 * an HT APIC. They encode, among others, the index within
1098 * the HT APIC. We don't care about it here since thankfully,
1099 * it appears that they have the APIC already properly
1100 * configured, and thus our current fixup code that reads the
1101 * APIC config works fine. However, we still need to mask out
1102 * bits in the specifier to make sure we only get bit 0 which
1103 * is the level/edge bit (the only sense bit exposed by Apple),
1104 * as their bit 1 means something else.
1106 if (machine_is(powermac))
1108 *out_flags = map_mpic_senses[intspec[1] & mask];
1110 *out_flags = IRQ_TYPE_NONE;
1112 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1113 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1118 static struct irq_host_ops mpic_host_ops = {
1119 .match = mpic_host_match,
1120 .map = mpic_host_map,
1121 .xlate = mpic_host_xlate,
1124 static int mpic_reset_prohibited(struct device_node *node)
1126 return node && of_get_property(node, "pic-no-reset", NULL);
1130 * Exported functions
1133 struct mpic * __init mpic_alloc(struct device_node *node,
1134 phys_addr_t phys_addr,
1136 unsigned int isu_size,
1137 unsigned int irq_count,
1145 u64 paddr = phys_addr;
1147 mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1153 mpic->hc_irq = mpic_irq_chip;
1154 mpic->hc_irq.name = name;
1155 if (flags & MPIC_PRIMARY)
1156 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1157 #ifdef CONFIG_MPIC_U3_HT_IRQS
1158 mpic->hc_ht_irq = mpic_irq_ht_chip;
1159 mpic->hc_ht_irq.name = name;
1160 if (flags & MPIC_PRIMARY)
1161 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1162 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1165 mpic->hc_ipi = mpic_ipi_chip;
1166 mpic->hc_ipi.name = name;
1167 #endif /* CONFIG_SMP */
1169 mpic->hc_tm = mpic_tm_chip;
1170 mpic->hc_tm.name = name;
1172 mpic->flags = flags;
1173 mpic->isu_size = isu_size;
1174 mpic->irq_count = irq_count;
1175 mpic->num_sources = 0; /* so far */
1177 if (flags & MPIC_LARGE_VECTORS)
1182 mpic->timer_vecs[0] = intvec_top - 12;
1183 mpic->timer_vecs[1] = intvec_top - 11;
1184 mpic->timer_vecs[2] = intvec_top - 10;
1185 mpic->timer_vecs[3] = intvec_top - 9;
1186 mpic->timer_vecs[4] = intvec_top - 8;
1187 mpic->timer_vecs[5] = intvec_top - 7;
1188 mpic->timer_vecs[6] = intvec_top - 6;
1189 mpic->timer_vecs[7] = intvec_top - 5;
1190 mpic->ipi_vecs[0] = intvec_top - 4;
1191 mpic->ipi_vecs[1] = intvec_top - 3;
1192 mpic->ipi_vecs[2] = intvec_top - 2;
1193 mpic->ipi_vecs[3] = intvec_top - 1;
1194 mpic->spurious_vec = intvec_top;
1196 /* Check for "big-endian" in device-tree */
1197 if (node && of_get_property(node, "big-endian", NULL) != NULL)
1198 mpic->flags |= MPIC_BIG_ENDIAN;
1199 if (node && of_device_is_compatible(node, "fsl,mpic"))
1200 mpic->flags |= MPIC_FSL;
1202 /* Look for protected sources */
1205 unsigned int bits, mapsize;
1207 of_get_property(node, "protected-sources", &psize);
1210 bits = intvec_top + 1;
1211 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1212 mpic->protected = kzalloc(mapsize, GFP_KERNEL);
1213 BUG_ON(mpic->protected == NULL);
1214 for (i = 0; i < psize; i++) {
1215 if (psrc[i] > intvec_top)
1217 __set_bit(psrc[i], mpic->protected);
1222 #ifdef CONFIG_MPIC_WEIRD
1223 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1226 /* default register type */
1227 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1228 mpic_access_mmio_be : mpic_access_mmio_le;
1230 /* If no physical address is passed in, a device-node is mandatory */
1231 BUG_ON(paddr == 0 && node == NULL);
1233 /* If no physical address passed in, check if it's dcr based */
1234 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL) {
1235 #ifdef CONFIG_PPC_DCR
1236 mpic->flags |= MPIC_USES_DCR;
1237 mpic->reg_type = mpic_access_dcr;
1240 #endif /* CONFIG_PPC_DCR */
1243 /* If the MPIC is not DCR based, and no physical address was passed
1244 * in, try to obtain one
1246 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1247 const u32 *reg = of_get_property(node, "reg", NULL);
1248 BUG_ON(reg == NULL);
1249 paddr = of_translate_address(node, reg);
1250 BUG_ON(paddr == OF_BAD_ADDR);
1253 /* Map the global registers */
1254 mpic_map(mpic, node, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1255 mpic_map(mpic, node, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1259 /* When using a device-node, reset requests are only honored if the MPIC
1260 * is allowed to reset.
1262 if (mpic_reset_prohibited(node))
1263 mpic->flags |= MPIC_NO_RESET;
1265 if ((flags & MPIC_WANTS_RESET) && !(mpic->flags & MPIC_NO_RESET)) {
1266 printk(KERN_DEBUG "mpic: Resetting\n");
1267 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1268 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1269 | MPIC_GREG_GCONF_RESET);
1270 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1271 & MPIC_GREG_GCONF_RESET)
1276 if (flags & MPIC_ENABLE_COREINT)
1277 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1278 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1279 | MPIC_GREG_GCONF_COREINT);
1281 if (flags & MPIC_ENABLE_MCK)
1282 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1283 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1284 | MPIC_GREG_GCONF_MCK);
1287 * Read feature register. For non-ISU MPICs, num sources as well. On
1288 * ISU MPICs, sources are counted as ISUs are added
1290 greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1291 if (isu_size == 0) {
1292 if (flags & MPIC_BROKEN_FRR_NIRQS)
1293 mpic->num_sources = mpic->irq_count;
1296 ((greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1297 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1301 * The MPIC driver will crash if there are more cores than we
1302 * can initialize, so we may as well catch that problem here.
1304 BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
1306 /* Map the per-CPU registers */
1307 for_each_possible_cpu(i) {
1308 unsigned int cpu = get_hard_smp_processor_id(i);
1310 mpic_map(mpic, node, paddr, &mpic->cpuregs[cpu],
1311 MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
1315 /* Initialize main ISU if none provided */
1316 if (mpic->isu_size == 0) {
1317 mpic->isu_size = mpic->num_sources;
1318 mpic_map(mpic, node, paddr, &mpic->isus[0],
1319 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1321 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1322 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1324 mpic->irqhost = irq_alloc_host(node, IRQ_HOST_MAP_LINEAR,
1325 isu_size ? isu_size : mpic->num_sources,
1327 flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1328 if (mpic->irqhost == NULL)
1331 mpic->irqhost->host_data = mpic;
1333 /* Display version */
1334 switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1348 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1350 name, vers, (unsigned long long)paddr, num_possible_cpus());
1351 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1352 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1357 if (flags & MPIC_PRIMARY) {
1358 mpic_primary = mpic;
1359 irq_set_default_host(mpic->irqhost);
1365 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1368 unsigned int isu_first = isu_num * mpic->isu_size;
1370 BUG_ON(isu_num >= MPIC_MAX_ISU);
1372 mpic_map(mpic, mpic->irqhost->of_node,
1373 paddr, &mpic->isus[isu_num], 0,
1374 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1376 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1377 mpic->num_sources = isu_first + mpic->isu_size;
1380 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1382 mpic->senses = senses;
1383 mpic->senses_count = count;
1386 void __init mpic_init(struct mpic *mpic)
1391 BUG_ON(mpic->num_sources == 0);
1393 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1395 /* Set current processor priority to max */
1396 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1398 /* Initialize timers to our reserved vectors and mask them for now */
1399 for (i = 0; i < 4; i++) {
1400 mpic_write(mpic->tmregs,
1401 i * MPIC_INFO(TIMER_STRIDE) +
1402 MPIC_INFO(TIMER_DESTINATION),
1403 1 << hard_smp_processor_id());
1404 mpic_write(mpic->tmregs,
1405 i * MPIC_INFO(TIMER_STRIDE) +
1406 MPIC_INFO(TIMER_VECTOR_PRI),
1408 (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1409 (mpic->timer_vecs[0] + i));
1412 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1413 mpic_test_broken_ipi(mpic);
1414 for (i = 0; i < 4; i++) {
1417 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1418 (mpic->ipi_vecs[0] + i));
1421 /* Initialize interrupt sources */
1422 if (mpic->irq_count == 0)
1423 mpic->irq_count = mpic->num_sources;
1425 /* Do the HT PIC fixups on U3 broken mpic */
1426 DBG("MPIC flags: %x\n", mpic->flags);
1427 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1428 mpic_scan_ht_pics(mpic);
1429 mpic_u3msi_init(mpic);
1432 mpic_pasemi_msi_init(mpic);
1434 cpu = mpic_processor_id(mpic);
1436 if (!(mpic->flags & MPIC_NO_RESET)) {
1437 for (i = 0; i < mpic->num_sources; i++) {
1438 /* start with vector = source number, and masked */
1439 u32 vecpri = MPIC_VECPRI_MASK | i |
1440 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1442 /* check if protected */
1443 if (mpic->protected && test_bit(i, mpic->protected))
1446 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1447 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1451 /* Init spurious vector */
1452 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1454 /* Disable 8259 passthrough, if supported */
1455 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1456 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1457 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1458 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1460 if (mpic->flags & MPIC_NO_BIAS)
1461 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1462 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1463 | MPIC_GREG_GCONF_NO_BIAS);
1465 /* Set current processor priority to 0 */
1466 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1469 /* allocate memory to save mpic state */
1470 mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1472 BUG_ON(mpic->save_data == NULL);
1476 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1480 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1481 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1482 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1483 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1486 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1488 unsigned long flags;
1491 raw_spin_lock_irqsave(&mpic_lock, flags);
1492 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1494 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1496 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1497 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1498 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1501 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1503 struct mpic *mpic = mpic_find(irq);
1504 unsigned int src = virq_to_hw(irq);
1505 unsigned long flags;
1511 raw_spin_lock_irqsave(&mpic_lock, flags);
1512 if (mpic_is_ipi(mpic, irq)) {
1513 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1514 ~MPIC_VECPRI_PRIORITY_MASK;
1515 mpic_ipi_write(src - mpic->ipi_vecs[0],
1516 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1517 } else if (mpic_is_tm(mpic, irq)) {
1518 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1519 ~MPIC_VECPRI_PRIORITY_MASK;
1520 mpic_tm_write(src - mpic->timer_vecs[0],
1521 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1523 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1524 & ~MPIC_VECPRI_PRIORITY_MASK;
1525 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1526 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1528 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1531 void mpic_setup_this_cpu(void)
1534 struct mpic *mpic = mpic_primary;
1535 unsigned long flags;
1536 u32 msk = 1 << hard_smp_processor_id();
1539 BUG_ON(mpic == NULL);
1541 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1543 raw_spin_lock_irqsave(&mpic_lock, flags);
1545 /* let the mpic know we want intrs. default affinity is 0xffffffff
1546 * until changed via /proc. That's how it's done on x86. If we want
1547 * it differently, then we should make sure we also change the default
1548 * values of irq_desc[].affinity in irq.c.
1550 if (distribute_irqs) {
1551 for (i = 0; i < mpic->num_sources ; i++)
1552 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1553 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1556 /* Set current processor priority to 0 */
1557 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1559 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1560 #endif /* CONFIG_SMP */
1563 int mpic_cpu_get_priority(void)
1565 struct mpic *mpic = mpic_primary;
1567 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1570 void mpic_cpu_set_priority(int prio)
1572 struct mpic *mpic = mpic_primary;
1574 prio &= MPIC_CPU_TASKPRI_MASK;
1575 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1578 void mpic_teardown_this_cpu(int secondary)
1580 struct mpic *mpic = mpic_primary;
1581 unsigned long flags;
1582 u32 msk = 1 << hard_smp_processor_id();
1585 BUG_ON(mpic == NULL);
1587 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1588 raw_spin_lock_irqsave(&mpic_lock, flags);
1590 /* let the mpic know we don't want intrs. */
1591 for (i = 0; i < mpic->num_sources ; i++)
1592 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1593 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1595 /* Set current processor priority to max */
1596 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1597 /* We need to EOI the IPI since not all platforms reset the MPIC
1598 * on boot and new interrupts wouldn't get delivered otherwise.
1602 raw_spin_unlock_irqrestore(&mpic_lock, flags);
1606 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1610 src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1612 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1614 if (unlikely(src == mpic->spurious_vec)) {
1615 if (mpic->flags & MPIC_SPV_EOI)
1619 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1620 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1621 mpic->name, (int)src);
1626 return irq_linear_revmap(mpic->irqhost, src);
1629 unsigned int mpic_get_one_irq(struct mpic *mpic)
1631 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1634 unsigned int mpic_get_irq(void)
1636 struct mpic *mpic = mpic_primary;
1638 BUG_ON(mpic == NULL);
1640 return mpic_get_one_irq(mpic);
1643 unsigned int mpic_get_coreint_irq(void)
1646 struct mpic *mpic = mpic_primary;
1649 BUG_ON(mpic == NULL);
1651 src = mfspr(SPRN_EPR);
1653 if (unlikely(src == mpic->spurious_vec)) {
1654 if (mpic->flags & MPIC_SPV_EOI)
1658 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1659 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1660 mpic->name, (int)src);
1664 return irq_linear_revmap(mpic->irqhost, src);
1670 unsigned int mpic_get_mcirq(void)
1672 struct mpic *mpic = mpic_primary;
1674 BUG_ON(mpic == NULL);
1676 return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1680 void mpic_request_ipis(void)
1682 struct mpic *mpic = mpic_primary;
1684 BUG_ON(mpic == NULL);
1686 printk(KERN_INFO "mpic: requesting IPIs...\n");
1688 for (i = 0; i < 4; i++) {
1689 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1690 mpic->ipi_vecs[0] + i);
1691 if (vipi == NO_IRQ) {
1692 printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1695 smp_request_message_ipi(vipi, i);
1699 void smp_mpic_message_pass(int cpu, int msg)
1701 struct mpic *mpic = mpic_primary;
1704 BUG_ON(mpic == NULL);
1706 /* make sure we're sending something that translates to an IPI */
1707 if ((unsigned int)msg > 3) {
1708 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1709 smp_processor_id(), msg);
1714 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1717 physmask = 1 << get_hard_smp_processor_id(cpu);
1719 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1720 msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1723 int __init smp_mpic_probe(void)
1727 DBG("smp_mpic_probe()...\n");
1729 nr_cpus = cpumask_weight(cpu_possible_mask);
1731 DBG("nr_cpus: %d\n", nr_cpus);
1734 mpic_request_ipis();
1739 void __devinit smp_mpic_setup_cpu(int cpu)
1741 mpic_setup_this_cpu();
1744 void mpic_reset_core(int cpu)
1746 struct mpic *mpic = mpic_primary;
1748 int cpuid = get_hard_smp_processor_id(cpu);
1751 /* Set target bit for core reset */
1752 pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1753 pir |= (1 << cpuid);
1754 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1755 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1757 /* Restore target bit after reset complete */
1758 pir &= ~(1 << cpuid);
1759 mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1760 mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1762 /* Perform 15 EOI on each reset core to clear pending interrupts.
1763 * This is required for FSL CoreNet based devices */
1764 if (mpic->flags & MPIC_FSL) {
1765 for (i = 0; i < 15; i++) {
1766 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1771 #endif /* CONFIG_SMP */
1774 static void mpic_suspend_one(struct mpic *mpic)
1778 for (i = 0; i < mpic->num_sources; i++) {
1779 mpic->save_data[i].vecprio =
1780 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1781 mpic->save_data[i].dest =
1782 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1786 static int mpic_suspend(void)
1788 struct mpic *mpic = mpics;
1791 mpic_suspend_one(mpic);
1798 static void mpic_resume_one(struct mpic *mpic)
1802 for (i = 0; i < mpic->num_sources; i++) {
1803 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1804 mpic->save_data[i].vecprio);
1805 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1806 mpic->save_data[i].dest);
1808 #ifdef CONFIG_MPIC_U3_HT_IRQS
1810 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1813 /* we use the lowest bit in an inverted meaning */
1814 if ((mpic->save_data[i].fixup_data & 1) == 0)
1817 /* Enable and configure */
1818 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1820 writel(mpic->save_data[i].fixup_data & ~1,
1825 } /* end for loop */
1828 static void mpic_resume(void)
1830 struct mpic *mpic = mpics;
1833 mpic_resume_one(mpic);
1838 static struct syscore_ops mpic_syscore_ops = {
1839 .resume = mpic_resume,
1840 .suspend = mpic_suspend,
1843 static int mpic_init_sys(void)
1845 register_syscore_ops(&mpic_syscore_ops);
1849 device_initcall(mpic_init_sys);